J-K - To - D Flip-Flop Conversion VHDL Code

This document contains VHDL code to convert a JK flip flop to a D flip flop. It declares library and component modules for the JK and D flip flops. The architecture maps the JK flip flop component to the D, clock and reset ports, with J and K inputs tied to D and not D respectively, to perform the functionality of a D flip flop. Graphical RTL and output waveform views are provided to demonstrate the design and operation of the converted flip flop.

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J-K - To - D Flip-Flop Conversion VHDL Code

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J-K_TO_D FLIP FLOP CONVERSION VHDL CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
--------------------------------------------------------entity JK_to_D is
Port ( D,clock,reset : in STD_LOGIC;
Q,Q1 : inout STD_LOGIC);
end JK_to_D;

Library ieee declaration.

In ieee library std_logic_1164 package is
declared for std_logic data types (predefined data
types).

Entity describes circuit external ports.

D, clock, reset: - input port to D flip flop.
Q, Q1: - output port to D flips flop.

--------------------------------------------------------architecture structural_con of JK_to_D is

--------------------------------------------------------component jk_ff
Component (jk_ff) declaration.
Declarative part of D flip-flops architecture.
port (j,k,clk,rst:in std_logic;
Components represent the structure of
x,y:inout std_logic);
converted flip-flop.
end component;
---------------------------------------------------------Architecture begins.
begin
------------------------------------------------------------------------

ff: jk_ff port map (D,not D,clock,reset,Q,Q1);

-------------------------------------------------------------------------end structural_con;

RTL VIEW:-

INFOOP2R.WIX.COM/OP2R

Statements part of the architecture.

Components are port mapped to
perform D flip flop operation.

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OUTPUT WAVEFORM:-

INFOOP2R.WIX.COM/OP2R

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J-K - To - D Flip-Flop Conversion VHDL Code

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J-K - To - D Flip-Flop Conversion VHDL Code

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ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

J-K_TO_D FLIP FLOP CONVERSION VHDL CODE

Library ieee declaration.

Entity describes circuit external ports.

--------------------------------------------------------architecture structural_con of JK_to_D is

ff: jk_ff port map (D,not D,clock,reset,Q,Q1);

Statements part of the architecture.

ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

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