INTERRUPTS

8086-80486

INTERRUPT SOURCES
Hardware Interrupt
External input applied at non-maskable interrupt NMI External input applied at maskable interrupt INTR

Software Interrupt
Execution of INT instruction Exception in program execution Trap

INTERRUPT VECTOR TABLE IVT REAL MODES

Int Vector No. INT 00H INT 01H . INT FFH Physical Address 00000H 00002H 00004H 00006H Contains IP0 CS0 IP1 CS1

003FCH 003FEH

IP255 CS255

IDT PROTECTED MODE

IDTR stores physical base address of IDT and length in bytes of IDT Each Entry (interrupt descriptor) 8 bytes long Size- 2KB (256x8 bytes)
Offset (A16 A31) P DPL 01110 Segment selector Offset (A0 A15 ) 00H

INTERRUPT VECTORS 80X86

Lowest 17 vectors are dedicated to specific interrupts Interrupts 18 to 31 are reserved by INTEL for complex processors /BIOS Upper 224 interrupt types (32 to 255) available to a user for hardware/software interrupts DOS uses 21H (33)

INTERRUPTS - 8086
Interrupt Type zero INT 0
Divide by zero interrupt If the quotient is too large to fit into AL/AX Divide by zero interrupt invoked

Interrupt Type one INT 1

Single step Interrupt If trap flag is set 80X86 will do a type 1 interrupt after every instruction execution

INTERRUPTS- 8086
INT 2 When 8086 receives a low to high transition on its NMI input

Type 2 interrupt response cannot be disabled (masked) by any program instruction

INTERRUPTS - 8086
Break Point Interrupt Type 3
INT 3 instruction to implement breakpoint routines The system execute instruction up to break point and then goes to break point routine Debugging

Overflow Interrupt Type 4

INTO Invoking an interrupt after overflow in an arithmetic operation If no overflow it will be a NOP instruction

INTERRUPTS -80286
INT 5
BOUND BOUND AX, [SI]

INT 6
Invalid opcode

INT 7
Co-processor not available

INT 8
Double Fault

INT 9
Co-processor segment overrun Real mode co-processor offset address FFFFH

INTERRUPTS - 80286
INT A
Invalid Task Segment

INT B
Segment not present

INT C
Stack Segment overrun SS not present in protected Size exceeded in protected or real

INTERRUPT - 80286
INT D
GPL

Limit Exceeded Privilege rules violated Invalid descriptor segment type Write to code sent Read from execute only segment Write to Read only segment

INTERRUPTS 80386
INT E
Page Fault

INTERRUPT - 80486
INT 17
Alignment Check

INTERRUPTS

8086-80486

80X86 - INTR
Allows some external signal to interrupt execution of a program INTR can be masked ( disabled) Clearing IF flag disables INTR CLI STI - clears IF - sets IF flag

80x86 when reset IF = 0 When 80x86 branches to ISR IF - 0 IRET/IRETD IF -1

80X86 - INTERRUPTS
In response to INTR 80X86 expects a vector number External hardware device required It enters into INTA machine cycle
INTR INTA D7-D0
Vector number

D0 D1 D2 D3 D4 D5 D6 D7
O7 O6 O5 O4 O3 O2 O1 O0 LS 244 I7 I6 I5 I4 I3 I2 I1 I0

Tri State Buffer to generate Vector No.

vCC
G1 G2

INTA

D0 D1 D2 D3 D4 D5 D6 D7
O7 O6 O5 O4 O3 O2 O1 O0 LS 244 I7 I6 I5 I4 I3 I2 I1 I0 G1 G2 IRQ0

INTA INTR
IRQ7

IRQ 7 1 1 1 1 1 1 1 0 6 1 1 1 1 1 1 0 1 5 1 1 1 1 1 0 1 1 4 1 1 1 1 0 1 1 1 3 1 1 1 0 1 1 1 1 2 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1

Vector No. FEH FDH FBH F7H EFH DFH BFH 7FH

I/O INTERFACING

I/O INTERFACING
Isolated I/O (or I/O mapped I/O)
Memory address space is different from I/O address space Signals used are IOR and IOW for peripherals and MEMR and MEMW for memory Instructions used are IN and OUT

Memory mapped I/O

IN and OUT instructions are not used. Signals used are MEMR and MEMW both for memory and peripherals Memory address space is same as I/O address space

FFFFFH FFFFH

FFFFFH

64Kx8 1Mx8 I/O 0000H I/O

00000H Memory

00000H Memory+I/O

I/O INSTRUCTIONS
IN and OUT instructions INS and OUTS instructions

IN AL,p8 IN AX,p8 IN EAX,p8 IN AL,DX IN AX,DX IN EAX,DX OUT p8,AL OUT p8,AX OUT p8,EAX OUT DX,AL OUT DX,AX OUT DX,EAX

I/O INTERFACING
Input Device
E.g. Switch

VCC R 1 0 S1 A

I/O INTERFACING
Output Device
E.g. LED

A 0 1

WHY BUFFERS ?
Input devices must be isolated from the global data bus Else unwanted data (garbage) may be transferred on to the data bus Tri-state buffers provide isolation as well as strengthen the signal Why not use latches and buffers with Memory Interfacing ? Memory has such latches and buffers internally present

I/O DESIGN IN 8086

In any P-based system when data is sent out by P, the data on the data-bus must be latched by the receiver/output device Memories have internal latches store data Latching system must be designed for ports Data provided by the P is available only for short period of time (50-1000ns) data must be latched else it will be lost Similarly, when data comes in from a port/memory, data must be input through a tri-state buffer

Port/ Interface Controller

I/O

DESIGN
IN AL, 9CH

LSB D0 To 8086 D7 Digital I/P

74LS244

G1

G2

MSB

9CH
RD IO/M

DESIGN
OUT 9CH, AL

D0 From 8086 D7

LSB

74LS373

OE

MSB

9CH
WR IO/M

Interfacing input devices like switches require buffers. Interfacing output devices like LEDs require latches. Programmable Peripheral Interface ( PPI) device provides these features.

I/O INTERFACING

8255

8255 PROGRAMMABLE PERIPHERAL INTERFACE (PPI)

Intel has developed several peripheral control chips for 80x86 family Intent provide complete I/O interface to x86 chip 8255 PPI PPI provides 3, 8-bit I/O ports in one package Chip can be directly interfaced to the data bus of 8086 Other Peripheral Devices 8253/8254 Programmable Interval Timer (PIT) 8259 Programmable Interrupt Controller (PIC) 8237 Direct memory Access Controller (DMAC)

Port A

PA3 PA2 PA1 PA0 RD CS GND A1 A0 PC4 PC5 PC6 PC7 PC0 PC1 PC2 PC3 PB0 PB1 PB2

Upper Port C Lower Port C Port B

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

8255

40 39 38 37 36 37 35 33 32 31 30 29 28 27 26 25 24 23 22 21

PA4 PA5 PA6 PA7 WR

Port A

D0 D1 D2 D3 D4 D5 D6 D7
VCC PB7 PB6 PB5 PB4 PB3

Port B

Power Supply

+ 5V GND Group A Control Group A Port A (8) PA0 PA7

D0 D7

Data Bus Buffer

8 bit internal data bus

Group A Port C Upper(4)

PC4 PC7

RD WR A0 A1 RESET CS R/W Control Logic Group B Control

Group B Port C Lower(4)

PC0 PC3

Group B Port B(8)

PB0 PB7

8255A Internal

CS 0 0 0 0 1

A1 0 0 1 1 X

A0 0 1 0 1 X

Selected Port A Port B Port C Control Register 8255 Not Selected

Selecting Port / Programming 8255

D7

D6

D5

D4
Port A

D3
Port C Upper 1 - I/P 0 - O/P

D2
Port B Mode

D1
Port

D0
Port C Lower 1 - I/P 0 - O/P

Port A Mode Always 1 for I/O Mode 0 0 - Mode 0 0 1 - Mode 1 1 x Mode 2

1 - I/P 0 - O/P

0-Mode0 1 - I/P 1-Mode1 0 -O/P

Group A

Group B

Control Word Format for I/O Mode

MODES OF OPERATION 8255

D7

0 BSR

1 I/O

Mode 0

Mode 1

Mode 2

Simple I/O (A, B, C)

Handshake I/O (A, B)

C Handshake

Handshake BiDirectional I/O (A)

C Handshake

Mode 0, 1 (B)

I/O INTERFACING

BSR Mode Example

BSR MODE OF 8255 PORT C

Example: Connect 3 LEDs to Port C. Blink one LED after another at regular intervals of 1ms 8255- Base address 00H

D7

D6 D5 D4 x x

D3 Bit2 PC B0 B1 B2 0 0 0 0

D2 Bit1 1 1 0 0 2 0 1 0 3 1 1 0 4 0 0 1

D1 Bit0 5 1 0 1 6 0 1 1

D0 Bit Set/Reset 7 0 - Reset 1 1 1

1 Set

0 -BSR x

Dont Care Condition

I/F 8255

Interface to the Processor

OUTPUT DEVICE
E.g. LED

A 0 1

OUTPUT DEVICE
E.g. LED

A 1 0

R VCC

0 PC0 1 PC1 PC2 8255 0 1 1 0 5V

Interface to the I/O Devices

creg

equ 06h moval,80h out creg,al creg, al creg, al creg, al al,01 creg, al al,02

out mov out call mov out mov out mov out call jmp al,01

creg, al al,05 creg, al

x1: moval,00 out out out calldelay_1ms mov out mov moval,03 moval,05

delay_1ms creg, al al,03 creg, al al,04 creg, al x1

delay_1ms

I/O INTERFACING

Basic I/O example

MODE 0 : SIMPLE INPUT/OUTPUT

O/P Are Latched Any of the Ports A, B & C can be used I/P Buffered Any of the Ports A, B & C can be used Interrupts/Handshake Not Possible

Read 12 switches and display switch condition on 12 LEDs with 8255H and Base Address 00H

Interface to the 8255

Interface to the Processor

creg porta portb portc mov out in out in and mov ror out

equ 06h equ 00h equ 02h equ 04h al,10011000b creg,al al,porta portb,al al,portc al,0f0h cl,04h al,cl portc,al

I/O INTERFACING KEYPAD

MATRIX KEYPAD INTERFACING

In most keyboards, key switches are connected in a matrix of rows and columns. Getting meaningful data from keyboard, requires following steps: Detect a key press De-bounce the key press Encode the key press (produce a standard code for the key press)

KEY DE-BOUNCE
When a mechanical key is pressed or released- the metallic contacts bounce before they make steady state contact Bouncing is noise and should not be treated as i/p

De-bounce s/w using software delay of 10-20 ms h/w dedicated hardware device

Mode 0 Matrix Keypad

0 1 2 3

5V

O0
8255 I/P port Pc4 Pc7

1 1 1 1
4 8 C 5 9 D 6 A E 7 B F

O1 O2 O3

8255 O/P port Pc0 Pc3

I0 I1 I2 I3

keyboard Output zero to one column Read rows Read rows NO All Keys Open ? yes Read rows detect NO Key pressed ? yes Wait 20 ms De-bounce return encode Key found? yes Convert to hex

Zero to all columns

NO

Read rows

NO

Key pressed ? yes

E.g. Mode 0 Keypad I/f

0 1 2 3

5V

O0
8255 I/P port Pc4 Pc7

1 0 1 1 1
4 8 C 5 9 D 6 A E 7 B F

O1 O2 O3

8255 O/P port Pc0 Pc3

I0 I1 I2 I3

0011 0101 0110 0111

Key 0 1 2 3 4 5 6 7 8 9 A B C D E F

O3 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0

O2 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1

O1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1

O0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

I3 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0

I2 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1

I1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1

I0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1

HEX EE ED EB E7 DE DD DB D7 BE BD BB B7 7E 7D 7B 77

BITS Pilani, Pilani Campus

D0 D7 System I/f

PC0 PC3

A0 PC4 PC7 A1 RD 8255 WR CS PB0 PB7 RESET PA0 PA7

Column I/ps Row O/ps

Not Used

BITS Pilani, Pilani Campus

I/O INTERFACING
Display Interfacing

a f b

e d

D0 D7 System I/f A0 A1 RD WR CS RESET

PC0 PC3 PC4 PC7

8255 PB0 PB7 7447

Vcc

STATIC DISPLAY
For a common anode display, a segment is turned on by applying a logic low to it. The 7447 converts a BCD code to its inputs to the pattern of lows required to display the number represented by the BCD code. This is referred to as static display because current is being passed through the display at all times.

Drawbacks:

When using the scheme to drive multiple digits. Power consumption say, 8 devices displaying digit 8 at the same time. Seven segments are lit in one device. Current drawn = 7 segments x 8 devices x 20 mA = 1.12 A Each seven segment display device, requires a separate 7447 decoder and each decoder draws a current of 13 mA. Current required by decoder and LED displays is huge.
Solution: Software-multiplexed or Scanned display (uses only one 7447 decoder to drive multiple devices)

A0 A3 A4

A5 A6 A7

LT RBO RBI

150 D0

D1

D2

D3

5V
CS D0 D7 IOR IOW A1 A2 PB0 PB1 PB2 PB3

A B C D

Vcc
GND

Vcc 5V

D0 D7 RD 8255 WR PC 0 PC A0 1 PC2 A1 RESET

PC3

7447

0 1 1 1

1 0 1 1

1 1 0 1

1 1 1 0

690

I/O INTERFACING

Example: Keypad Interface

Input a data from a keyboard Input data is a valid one digit Hex number Use a lookup table to convert it into seven segment code Output data on seven-segment display

E.g. Mode 0 Keypad I/f

0 1 5 9 D 2 6 A E 3 7 B F

5V

O0
PC4 PC7 Row O/ps

1 1 1 0 1
4 8 C

O1 O2 O3
0 1 1 0 0 1 0 1

PC0 PC3 Column I/ps

I0 I1 I2 I3

PC4 PC7 D0 D7 System I/f A0 A1 RD WR CS RESET PC0 PC3

Row O/ps Column I/ps

8255 PB0 PB7 PA0 PA7 Not Used

KEY 0 1 2 3 4 5 6 7 8 9 A B C D E F

O3 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0

O2 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1

O1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1

O0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

I3 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0

I2 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1

I1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1

I0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1

HEX EE ED EB E7 DE DD DB D7 BE BD BB B7 7E 7D 7B 77

a f b

e d

C O M M O N C A T H O D E D I S P L A Y C O D E S

Display h 0 1 2 3 4 5 6 7 8 9 A B C D E F 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0

g 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1

f 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1

e 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

d 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0

c 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1

b 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1

a 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1

HEX 3F 06 5B 4F 66 6D 7D 07 7F 67 77 7C 39 5E 79 71

PC4 PC7 D0 D7 System I/f A0 A1 RD WR CS RESET PC0 PC3

Row O/ps Column I/ps

8255 PB0 PB7

BUFFER

GND

.Model Tiny .DATA TABLE_D DB DB DB 3FH,06H,5BH,4FH,66H,6DH,7DH, 07H,7FH,67H,77H,7CH,39H,5EH, 79H,71H

TABLE_K

DB DB DB

EEH,, EDH, EBH, E7H, DEH, DDH, DBH, D7H, BEH, BDH, BBH, B7H 7EH, 7DH, 7BH, 77H,

.CODE

.STARTUP MOV OUT X0: X1: MOV OUT IN AND CMP JNZ CALL AL,10011000B 06H,AL AL,00H 04H,AL AL, 04H AL,F0H AL,F0H X1 DELAY_20MS Debounce Check for key release Initialize 8255

X2:

MOV OUT IN AND CMP JZ CALL MOV OUT IN AND CMP JZ

AL,00H 04H ,AL AL, 04H AL,F0H AL,F0H X2 DELAY_20MS AL,00H 04H ,AL AL, 04H AL,F0H AL,F0H X2

Check for Key press

Check for Key press

MOV MOV OUT IN AND CMP JNZ MOV MOV OUT IN AND CMP JNZ

AL, 0EH BL,AL 04H,AL AL,04H AL,F0H AL,F0H X3 AL, 0DH BL,AL 04H ,AL AL,04H AL,F0H AL,F0H X3

Check for Key press Column1

Check for Key press Column2

MOV MOV OUT IN AND CMP JNZ MOV MOV OUT IN AND CMP JZ

AL, 0BH BL,AL 04H,AL AL,04H AL,F0H AL,F0H X3 AL, 07H BL,AL 04H,AL AL,04H AL,F0H AL,F0H X2

Check for Key press Column3

Check for Key press Column4

X3: X4:

X5:

.EXIT END

OR MOV MOV CMP JZ INC LOOP MOV LEA XLAT OUT JMP

AL,BL CX,0FH DI,00H AL,TABLE_K[DI] X5 DI X4 AX,DI BX, TABLE_D 02H,AL X0

Decode key

Display

ADC

I/O Interfaci ng

Interfacing A/D Converter

5V

Vcc Data Ready Analog I/p Unipolar: 0V to + 10V Bipolar: - 5V to + 5V Analog Com AD570 D0 D7 Blank/ Convert Bi-polar Digital Com VEE

Analog I/p

-15V

B/C

Removes/blanks previous data

2s

Start conv

Start conv

1.5 s

25s Conversion Time

1.5 s Data Ready

500ns

Data lines become active with new data

10 V 256

= 39.0625 mV

O0 O7

I0 I7

Vcc D0 D7 AI

5V

Analog I/p

LS244 G1
IOR
Select address from decoder IOW

ACom AD570 DCom B/C BI System Gnd

G2

INTR

DR

VEE

-15V

1.048 MHz

CLK

D0 D7 A1 A2 A3 INTR IOR
A0 A4 A5 A6 A7

DB0 DB7 AD0 AD1 AD2 EOC OE

IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 VREF+ VREFVcc GND 5V 0V

Analog I/ps

Supply

SOC ALE

5 V = 19.5312 mV 256

IOW

ADC 0808

1.048 MHz

CLK

PB0 PB7 PC0 PC1 PC2 INTR PC3 PC4 PC5

DB0DB7 AD0 AD1 AD2

IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 VREF+ VREFVcc GND 5V 0V

Analog I/ps

EOC OE SOC ALE

Supply

ADC 0808

PA0 PA7
WR' RD'

8 2 5 5

A D C
100 ns

Ain

PC7 PC0

SOC EOC

A1

A0

0 8 0 8

Base Address of 8255 =80H

I/O Control Word: 10010001 = 91H BSR Control Word: 00001110 = 0EH ;for resetting PC7 00001111 = 0FH ;for setting PC7 MOV AL,91H OUT 86H,AL MOV AL,0EH OUT 86H,AL CALL DELAY MOV AL,0FH OUT 86H,AL BACK: IN AL,84H AND AL,01H ; TO CHECK IF EOC = 1 JZ BACK IN AL,80H

Programmabl e Interval Timer

8253/8254

Counting/ Generation of Timing Signals Software delay routines Adv Flexibility Disadv Less precision Hardware 555/ RC Adv Precision Disadv Not Flexible

S/w Controlled hardware Timer- 8253/8254

FEATURES OF 8253/8254
Three 16 bit counters Max frequency
2.6MHz 8MHz 8254 10MHz 8254-2 8253

Down Counters Count value to be loaded in counter can be a Binary/BCD Number Can operate in one of 6 possible Modes

D0 D7 CS RD WR A0 A1 VCC GND

CLK0 GATE0 OUT0 CLK1 GATE1 OUT1 CLK2 GATE2 OUT2

8253 Pin Out of 8253

8253 TIMING
Counter Output freq = Count 16-bit BCD/ Binary

Input clk freq

Count value

Power Supply D0 D7 RD WR A0 A1 CS

+ 5V GND Data Bus Buffer

Counter 0 8 bit internal data bus

CLK0 GATE0 OUT0

CLK1 Counter 1 GATE1 OUT1

R/W Control Logic

CLK2

Control Reg

Counter 2

GATE2 OUT2

8253 Internal

CS 0 0 0 0 1

A1 0 0 1 1 X

A0 0 1 0 1 X

Selected Counter 0 Counter 1 Counter 2 Control Register 8253/8254 Not Selected

D7 SC1

D6 SC0

D5 RW1

D4 RW0

D3 M2
000 001 010 011 1x0 1x1

D2 M1

D1 M0

D0 BCD
0 binary 0000h FFFFh 1 BCD 0000 9999

Selects Counter
00 01 10 11 Counter 0 Counter 1 Counter 2 Read Back Command

Read/Write Control
00 01 10 11 Latch Counter R/W LSB R/W MSB
R/W LSB followed by MSB

Timer Mode

Interrupt on T/C h/w re-Triggerable one shot rate generator Square wave generator s/w triggered strobe h/w triggered strobe

Before you can use 1. 2. 3. 4. 5. 6. Initialize the mode of every counter planned to be used This is done by sending individual command words for every counter These CWs are sent at A1A0 =11 Send counts to the counters This is done at counter addresses Enable gates for counting to start

Ex: 8253 interfaced starting at 50H C0 used in mode 1, MSB+LSB, binary To be loaded with 4000H C1 used in mode 0, LSB only, BCD To be loaded with 99

A2
A0 A3 A5 A7 A4 A6

A0 A1 CS

A1

M/IO

8253 RD WR D0 D7 RD WR D0 D7

Interface to the processor

cnt0 cnt1 creg

equ equ equ mov out mov out mov out mov out mov out

50h 52h 56h al,00110010b 56h,al al,01010001b 56h,al al,0 50h,al al,40h 50h,al al,99h 52h,al

8253 Timer Modes Mode 0

MODE 0
Event Counter Interrupt on reaching Terminal Count

WR

CW=10 LSB = 4 H
4 CLK 3 2 1 0 FF FE FD FC FB

GATE OUT

5V 2.3 V

7407

LM139

L E D

Port 5V 0V comparator

P D

WR

CW

LSB = 4
4 3 2 2 2 2 2 1 0 FF FE

CLK

GATE OUT

WR

CW

LSB = 4
4 3

LSB = 4
2 4 3 2 1 0 FF FE

CLK

GATE OUT

Mode 0
Interrupt on terminal count (event counter) Out pin goes low when mode word or new count is written Now if clock is applied and gate=1, countdown begins Countdown stops if gate=0: resumes if gate=1 If count written is N then OUT becomes high after N+1 clocks OUT remains high till a new count is written Countdown continues as FFH, FEH if gate =1 Application object counting

8253 Timer Modes Mode 1

MODE 1
H/w Re-Triggerable One-Shot (Programmable One- Shot)

WR

CW=10 LSB = 4 H
CLK GATE

FF

FE

OUT

WR

CW

LSB = 4
4 3 2 1 4 3 2 1 0

CLK GATE

OUT

WR

CW

LSB = 4
4 3

LSB = 2
2 1 0 FF FE 2 1

CLK GATE

OUT

AC Power Failure Detection

Mode 1
Programmable one-shot- also h/w retriggerable one-shot Two step process Load count register Send 0-to-1 pulse on GATE to trigger it When triggered o/p goes low after one clock cycle & stays low for N clock cycles goes high If gate is made low it does not stop counter A +ve transition at gate reloads the counter & countdown begins afresh A new count is not loaded till gate is triggered Application detect ac power failure

8253 Timer Modes Mode 2

MODE 2
Rate Generator (Divide-by-N Counter)

WR

CW

LSB = 3
3 2 1 3 2 1 3 2 1 3 2

CLK

GATE OUT

WR

CW

LSB = 3
3 2 1 3 2 2 3 2 1 3 2

CLK

GATE OUT

WR

CW

LSB = 4
4

LSB = 5
3 2 1 5 4 3 2 1 5 4

CLK

GATE OUT

Mode 2
Rate generator or divide-by-N counter Countdown starts one clock cycle after the gate is made high (or one cycle after the count is written if gate is already high) On reaching a count of one, the OUT goes low for one cycle. If the counter is loaded with a number N, then OUT pin will go low for one clock cycle every N input clock pulses. Now count is automatically reloaded and whole process repeats If a new count is written then it is loaded only after previous countdown finishes If gate is made low during countdown then counting stops and OUT is made immediately high Application : frequency generation, real time clock

8253 Timer Modes Mode 3

MODE 3
Square Wave Generator

WR

CW

LSB = 4
4 2 4 2 4 2 4 2 4 2 4

CLK

GATE OUT

WR

CW

LSB = 5
4 2 0 4 2 4 2 0 4 2 4

CLK

GATE OUT

WR

CW

LSB = 5
4 2 0 4 2 4 4 2 0 4 2

CLK

GATE OUT

Mode 3
Square wave generator If GATE = 1, OUT is a square wave (50% duty, or slightly off if N is odd) If N is odd then will be high for (N+1)/2 and low for (N-1)/2 Each clock pulse decrements the counter by 2 Count is automatically reloaded on 2 If gate is made low during countdown then counting stops and when gate is made high again, counting continues. Application: clock input generation for other devices, audio tone generator

8253 Timer Modes Mode 4

MODE 4
Software Triggered Strobe

WR

CW

LSB = 4
4 3 2 1 0 FF FE

CLK

GATE

OUT

WR

CW

LSB = 4
4 3 2 2 2 2 2 1 0 FF FE

CLK

GATE

OUT

WR

CW

LSB = 4
4 3

LSB = 4
2 4 3 2 1 0 FF FE

CLK

GATE

OUT

Mode 4
Software triggered strobe If GATE =1, OUT goes low N+1 cycles after the count is written. OUT is low for one clock cycle Count must be reloaded to repeat the strobe not automatically reloaded If GATElow, the OUT high and count stops; count resumes (from where it stopped) when GATEhigh Application : I/O strobe

8253 Timer Modes

Mode 5 and read back

MODE 5
Hardware Triggered Strobe

WR

CW

LSB = 4
4 3 2 1 0 FF FE 4 3

CLK GATE

OUT

WR

CW

LSB = 4
4 3 2 1 4 3 2 1 0 FF

CLK GATE

OUT

WR

CW

LSB = 4
4 3

LSB = 2
2 1 0 FF FE 2 1

CLK GATE

OUT

Mode 5

Hardware triggered strobe Like mode 4, but triggering is done with GATE instead Count begins when 0-1 pulse hits GATE OUT goes low N+1 cycles after gate is triggered. OUT is low for one clock cycle Gate must be triggered again to repeat the strobe not automatically reloaded If GATElow, it does not stop countdown A trigger on gate in between countdown will reload the count and keep OUT high Application: I/O handshake

Reading Count value of counter (s)

8254 counters have latches on their outputs. Normally enabled during counting, so that latch outputs follow counter outputs. When reading the current count value, we read data on outputs of these latches. For reading the correct count.Counting must be stopped. Can be done by removing clock, gate requires extra hardware.. So. Latch the count before reading..by Sending counter latch command word at CR (A1 A0 =11) and then read. etc.but not preferred as

Read back command word (8254 only) 1 1 Count Status C2

Select counter bits

C1

C0

Latch count of Latch status of selected counters selcted counters

Status Register (8254 only) OUT NULL RW1 RW0

Read/write operation

Logic 1 for BCD Counter mode counter

M2

M1

M0

BCD

Level of OUT pin

PROGRAMMABLE INTERRUPT CONTROLLER

8259

80X86 - INTERRUPTS
In response to INTR 80X86 expects a vector number External hardware device required It enters into INTA machine cycle
INTR INTA D7-D0
Vector number

D0-D7 RD WR A0 CS
CAS0 CAS1 CAS2 SP/ EN

Data Bus Buffer

INTA Control Logic

INT

Read/ Write Control Logic

ISR
Cascade Buffer/ Comparator

Priority Resolver

IRR

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

IMR

A15 A14 A13 A12 A11 A10 A9 A8 M/IO A7 A6 A5 A0 A4 A3

74LS138
G2A

G2B G1 C B A

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0V

CS A0 D0 D1 D2 D3 D4 D5 D6 D7 SP/EN RD WR INTA

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 CAS0 CAS1 CAS2 INT

Slave

External Interrupt signal

8259 #2

A1 D0 D1 D2 D3 D4 D5 D6 D7 RD WR INTA

+5 V

CS A0 D0 D1 D2 D3 D4 D5 D6 D7 SP/EN RD WR INTA

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 CAS0 CAS1 CAS2 INT

8259 #1

INTR

Interfacing with 8259

Master

INT

INTA

0 0 0 0 1 0 0 1 0 0

Priority Resolver

IRR 0 0 0 0 1 0 0 1 0 0 IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

nxt

IMR 0 0 0 0 0 0 1 1

Mainline STI

IR4-ISR- STI IR2-ISR- STI

bck

Mainline STI

IR4-ISR

IR2-ISR

INITIALIZING 8259
Base Address FF00h 2 addresses are FF00H, FF02H

4 ICWs 3 OCWs Order of writing important for ICWs

ICW1 ICW2 Cascade? ICW3 ICW4? ICW4 Ready to accept Interrupts

PROGRAMMABLE INTERRUPT CONTROLLER

8259Command Words

ICWx

A0 D7

D6

D5
X for 8086

D4

D3

1=ICW4 needed 1=level triggered 1=interval of 4 0=cascade mode 0=no ICW4 needed 0=edge triggered 0=interval of 8 X for 8086

D2CALL ADDR D1 D Interval 1=single 0

A7

A6

A5

LTIM ADI

SNGL IC4

A15 T7 0

A14 T6 0

A13 T5 0

A12 A11 A10 A9 1=Special Fully Nested Mode T4 T3Buffered Mode Master/Slave
0

1=Automatic End of Interrupt 1 for 8086

A8

SFNM

BUF
0 1 1

M/S AEOI PM
X 0 1
Non buffered Mode Buffered Mode/Slave Buffered Mode/Master

ICWx 3 3S

A0 D7 1 1 S7 0

D6 S6 0

D5 S5 0

D4 S4 0

D3 S3 0

D2 S2 ID2

D1 S1 ID1

D0 S0 ID0

ICW3 used for cascade

INT IR0 INTA 8259M

CAS0 CAS1 CAS2

INT
CAS0 CAS1 CAS2

SP/EN 5V

8259S INTA SP/EN

1 0

INT IR0 INTA 8259M

CAS0 CAS1 CAS2

SP/EN 5V

0 0 0

INT
CAS0 CAS1 CAS2

Vector No.

8259S INTA SP/EN

OCWx A0 D7 1 2 1 0 M7 R R

D6 M6 SL SL

D5 M5 EOI EOI

D4 M4 0

D3 M3 0

D2 M2 L2

D1 M1 L1

D0 M0 L0

0 0 1 1 1 1

0 1 0 0 1 1

1 1 1 0 1 0

Purpose Non-specific EOI Specific EOI Rotate on non-specific EOI Rotate on AEOI Rotate on specific EOI Set priority

D7

D6

D5 IS5 0 5

D4 IS4 1 4

D3 IS3 0 3

D2 IS2 0 2

D1 IS1 0 1

D0 IS0 0 0

IS7 IS6 0 7 0 6

ISR4 SERVICED EOI/AEOI 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3

OCWx 3

A0 0

D7 0

D6 ESMM

D5 SMM

D4 0

D3 1

D2 P P

D1 RR RR

D0 RIS RIS

Purpose Read IRR on next RD Read ISR on next RD Poll Purpose No Action Reset SMM Set SMM

0 0 1

1 1 x
ESMM

0 1 x
SMM

0 1 1

x 0 1

16650 PCI

UART

COMMUNICATION
Parallel Serial
Synchronous Asynchronous

SERIAL COMMUNICATION
Simplex Half Duplex Full Duplex

SERIAL COMMUNICATION

8086

16650

MODEM

MODEM

16650

16650-MODEM
DSR DTR CTS RTS RI DCD

SERIAL COMMUNICATION- NULL MODEM

8086

16650

16650

NULL MODEM
DTR RTS CTS 16650 DSR DCD

SERIAL DATA LINES

SIN SOUT

INTERFACE TO 8086
A0, A1, A2 CS0 CS1 CS2 ADS RD,RD WR, WR RXRDY TXRDY MR INTR DDIS D0- D7

ADDRESSES
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Function RXB/TXB Int Enable Int Indentification/ FIFO Control Line Control Modem Control Line Status Modem Status Scratch

CLOCK
X1,X2 BAUDOUT RCLK OUT1, OUT2

FORMAT OF SERIAL DATA

Start D0 D1 D2 D3 D4 D5 D6 D7 P

INITIALIZING 16650
Program LCR Program BRG

LCR

DL

SB

ST

PE

L1

L0

BDR 18.432MHZ
BR 110 300 1200 2400 4800 9600 19,200 38,400 57,600 115,200 Divisor Value 10,473 3840 920 480 240 120 60 20 20 10

16650 PCI

UART

16650-MODEM
DSR DTR CTS RTS RI DCD

NULL MODEM
DTR RTS CTS 16650 DSR DCD

SERIAL DATA LINES

SIN SOUT

INTERFACE TO 8086
A0, A1, A2 CS0 CS1 CS2 ADS RD,RD WR, WR RXRDY TXRDY MR INTR DDIS D0- D7

ADDRESSES
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Function RXB/TXB/BRL Int Enable/BRH Int Indentification/ FIFO Control Line Control Modem Control Line Status Modem Status Scratch

CLOCK
X1,X2 BAUDOUT RCLK OUT1, OUT2

FORMAT OF SERIAL DATA

Start D0 D1 D2 D3 D4 D5 D6 D7 P

INITIALIZING 16650
Program LCR Program BRG

LCR

DL

SB

ST

PE

L1

L0

BDR 18.432MHZ
BR 110 300 1200 2400 4800 9600 19,200 38,400 57,600 115,200 Divisor Value 10,473 3840 920 480 240 120 60 20 20 10

FIFO CONTROL REGISTER

RT1

RT0

DMA

XMIT RST

REVC RST

EN

SAMPLE INITIALIZATION
9600 baud 8 data Odd parity 1 stop SA F0H

SAMPLE INITIALIZATION
LINE LSB MSB FIFO INIT:
MOV OUT MOV OUT MOV OUT AL,10001011B LINE,AL AL,120 LSB,AL AL,0 MSB,AL

EQU EQU EQU EQU

0F6H 0F0H 0F2H 0F4H

SAMPLE INITIALIZATION
;contd
MOV OUT MOV OUT AL,00001011B LINE,AL AL,00000111B FIFO,AL

LINE STATUS REGISTER

ER TE TH BI FE PE OE DR

SEND DATA
LSTAT DATA SEND: X1: EQU EQU IN AND JZ MOV OUT 0FAH 0F0H AL,LSTAT AL,20H X1 AL,DAT DATA,AL

RECEIVE DATA
LSTAT DATA READ: X1: EQU EQU IN MOV AND JZ MOV AND JZ MOV JMP IN MOV 0FAH 0F0H AL,LSTAT AH,AL AL,01H X1 AL,AH AL,80H X2 AL,0 X3 AL,DATA DAT,AL

X2: X3:

INTERRUPT CONTROL REGISTER

0 0 0 0 EM EL ET ER

INTERRUPT ID REGISTER
ID ID ID PN

INTERRUPT ID
BITS 0001 0110 0100 1100 0010 0000 Priority 1 2 2 3 4 Type No Interrupt Receiver Error Receiver Data Character timeout Nothing has been read from RX FIFO for at least 4 characters time Transmitter Empty Modem Status

I/O INTERFACING

DMAC - 8237

DIRECT MEMORY ACCESS

Interrupt driven and programmed I/O require active CPU intervention

Transfer rate is limited CPU is tied up

DMA is the answer

Direct Memory Access is a method of transferring data between peripherals (I/O) and memory without using the CPU Maximum frequency of operation 15 MHz

DMA PROCESS
Data is transferred between memory and disk directly without involving the processor
Interrupt still tells CPU when such a transfer has started and finished

For DMA transfers

CPU tells the device controller the operation to perform and addresses involved. Device controller then carries out the operation without bothering the CPU, using DMA Bus controller arbitrates for the system bus Device controller informs the CPU when complete via an interrupt

DMA MODES
DMA can operate in one of two modes Bus master Mode Bus Slave Mode

DMA can do data transfers mainly using two modes Byte Mode Burst Mode

AD0- AD15 ALE

Addr latches

Addr Bus Data Bus MEMW Control Bus IOR

DREQ DACK

Mem

HLDA HOLD

Control Bus 1 0

HRQ

Address

Data Bus

DMAC

I/O

1 1

CLK RESET

ADSTB AEN A4 A7 MEMR MEMW DREQ0 DACK0 DREQ1 DACK1 DREQ2 DACK2 DREQ3 DACK3 EOP

DB0 - /A8 DB7/A15

HREQ HLDA CS READY IOR IOW A0 A1 A2 A3

8237

A16-A19 S6-S3 BHE/S7

LS373 G
OE

A16-A19 BHE AEN A8-A15

ALE AD8-AD15

8086

LS373 G OE LS373 G OE 5V

AD0-AD7

A0-A7

MN/MX

RD WR IO/M

MEMR LS244
OE

LOGIC CIRCUIT

MEMW IOR IOW

AEN
AD8-AD15 DT/R DEN AD0-AD7

8086

LS245
DIR OE

D8-D15

LS245
DIR OE

D0-D7 5V

AEN

MN/MX

MEMR MEMW IOR IOW 8237 A8-A15 LS373 G OE A0-A7

MN/MX

A8/D0A15/D7
ADSTB

5V

LS 373 D0- D3
DI DO

A16-A19

Produced manually(hardwire these inputs to ground or +5 V to produce a fixed address or connect them to an output port and specify these bits under program control.

OE AEN

+5 V

I/O INTERFACING

DMAC 8237 Registers

REGISTERS
Current Address Register Base Address Register Base Word Count register 0000, 0010, 0100, 0110 Current Word Count Register -0001, 0011, 0101 ,0111
DMA channel I/O port addresses

COMMAND REGISTER- 1000

0--DREQ sense active high 1--DREQ sense active low 0--Fixed priority 1--Rotating priority 0-- Memory-to memory disable 0--Controller enable 1-- Memory-to-memory enable 1--Controller disable

DACK

DREQ

LWR

PRT

NT/CT

CTRE

CH0H

MTME

0--DACK sense active low 0--Late write selection 1--DACK sense active high1--Extended write selection X--If bit 3 = 1

0--Normal timing 1--Compressed timing X--If bit 0 = 1

0--Channel 0 address hold disable 1--Channel 0 address hold enable X--If bit 0 = 0

MODE REGISTER- 1011

00-Demand mode select 01--Single mode select 10--Block mode select 0--Address increment select 11--Cascade mode select 1--Address decrement select

00--Verify transfer 01--Write transfer 10--Read transfer 11--Illegal Xx--If bits 6 and 7 = 11

00--Channel 0 select 01--Channel 1 select 10--Channel 2 select 11--Channel 3 select

MS1

MS0

ADI/D

AINIT

TYP1

TYP0

CS1

CS0

0--Autoinitialization disable 1--Autoinitialization enable

BUS REQUEST REGISTER- 1001

X X X X X S/R CS1

00--Select channel 0 01--Select channel 1 10--Select channel 2 11--Select channel 3

CS0

0--Reset request bit 1--Set request bit

MASK SET/RESET REGISTER- 1010

S/C CS1

00--Select channel 0 mask bit 01--Select channel 1 mask bit 10--Select channel 2 mask bit 11--Select channel 3 mask bit

CS0

0--Reset request bit 1--Set request bit

MASK REGISTER- 1111

0--Clear channel 2 mask bit 1--Set channel 2 mask bit 0--Clear channel 0 mask bit 1--Set channel 0 mask bit

CH3

CH2

CH1

CH0

0--Clear channel 3 mask bit 1--Set channel 3 mask bit

0--Clear channel 1 mask bit 1--Set channel 1 mask bit

STATUS REGISTER- 1000

1 -- Channel 2 request 1 -- Channel 0 request 1--Channel 2 has reached TC 1--Channel 0 has reached TC

REQ3

REQ2

REQ1

REQ0

TC3

TC2

TC1

TC0

1 -- Channel 3 request

1-- Channel 3 has reached TC1-- Channel 1 has reached TC 1 -- Channel 1 request

ADDITIONAL ADDRESSES AND S/W COMMANDS

Three additional software commands are used to control the operation of the 8237. These commands do not have a binary bit pattern. A simple output to the correct port number enables the software command. These commands are:
1100 clear first/last FF: 1101 Master Clear 1110 Clear Mask Register

ADDRESSES
Reg CH0AR CH0CR CHIAR CH1CR CH2AR CH2CR CH3AR CH3CR Addr 0000 0001 0010 0011 0100 0101 0110 0111 Reg CR/SR BR MRSR MR CFF MC/TR CMR MASKS Addr 1000 1001 1010 1011 1100 1101 1110 1111

EXAMPLE
Program DMAC for memory to memory transfer Contents of memory location 01000-013FF to 02000-023FF Base Address 70H

ALP
CH0 CH0C CH1 CH1C CR REQ MR CFF MASKS STATUS Calling parameters: DS = segment of source ES = segment of destination EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 70H 71H 72H 73H 78H 79H 7BH 7CH 7FH 78H ;channel 0 base and CAR address ;channel 0 CWCR address ;channel 1 base and CAR address ;channel 1 CWCR address ;command register address ;request register address ;Mode register address ;clear byte pointer F/F address ;MSR address ;status register

TRANS PROC NEAR MOV AX,DS ;program source address SHL AX,4 ADD AX,SI OUT CH0,AL MOV AL,AH OUT CH0,AL MOV AX,ES ;program destination address SHL AX,4 ADD AX,DI OUT CH1,AL MOV AL,AH OUT CH1,AL

MOV AX,CX ;program count DEC AX OUT CH1C,AL MOV AL,AH OUT CH1C,AL MOV AL,88H ;program mode OUT MR,AL MOV AL,85H OUT MR,AL MOV AL,1 ;enable mem to mem transfer OUT CR,AL MOV AL,0CH ;unmask channel 0/1 OUT MASKS,AL

MOV AL,4 OUT REQ,AL

;start DMA

X1: IN AL,STATUS;checking TC of channel 0 CMP AL,01H JNZ X1 RET TRANS ENDP

STORAGE DEVICE AND DISK ORGANIZATION

TYPES OF STORAGE DEVICE

Cost
Expensive Limited In Billionth of Second Directly Accessible Less than Primary Nearly Limited In Millionth of Second Routed Through Primary Storage

Capacity

Primary

Secondary

Access Time Processing

Hard Disk Cross Section

Cylinder X, X= Track Number Track N

Side0

Platter 1 Sector7 Sector6 Sector5 Sector4 Platter 3 Sector8 Side1 Sector1 Sector2 Sector3

Track 1 Track 0

Platter 2

PHYSICAL SECTOR/ LOGICAL SECTOR

8 8 7 7 6 7 6 5 5 8 1 5 4 1 2 3 4 4 2 3 2 1 6 7 15 8 0

1 23 16 9 14 17 22 18 21 10 13 20 19 2 11 12 4 3

Physical Sector

Logical Sector

Location 00 02H 03 0AH 0B 0CH 0DH 0E 0FH 10H 11 12H 13 14H 15H 16 17H 18 19H 1A 1BH 1C 1FH 20 23H 24H 25H 26H 27 2AH 2B 35H 36 3DH 3EH

Length (Bytes) 3 8 2 1 2 1 2 2 1 2 2 2 4 4 1 1 1 4 11 8

Description E9 XX XX or EB XX 90 Disk Formatting Program Number of Bytes per Sector Number of Sectors per Cluster Reserved Sector (including boot sector) Number of File Allocation Table (FAT) Number of Root Directory Entries Total Sectors on Disk Media Descriptor Byte Number of Sectors per FAT Sectors per Track Number of Heads Number of Hidden Sectors Total Sector in Logical Volume (Volume Size > 32 MB) Physical Drive Number Reserved Extended Boot Signature Record (29H) Volume Serial Number Volume Label Reserved Bootstrap

LOGICAL INTERPRETATION: BOOT SECTOR OF A FORMATTED FLOPPY

LOGICAL PARTITION: MS-DOS DISK (1.44MB FLOPPY DISK)

Boot sector (sector 0) FAT#1 (sectors 1 to 9) Additional copies of FAT (sectors 10 to 18) Root Directory (sectors 19 to 32) Files Area (sectors 33 to 2879)

ROOT DIRECTORY
DOS keeps track of
Each file and subdirectory as they are added to the disk by user Information about each file/directory is stored

Every time user adds a file, DOS updates directory area

Name of the file Time and date of creation Length of file

Files names are limited to eight characters and a three character extension

ROOT DIRECTORY
Location 00 07H 08 0AH 0BH 0C 15H 16 17H 18 19H 1A 1BH 1C 1FH Length (Bytes) 8 3 1 10 2 2 2 4 Description Filename File Extension File Attribute Reserved Time of Creation or Last Updating Date of Creation or Last Updating Starting Cluster Number Size of File

ROOT DIRECTORY
Attribute Byte
BIT Interpretation
7
Reserved

6
Reserved

5
Archive Bit

4
Directory

3
Vol. Label

2
System File

1
Hidden File

0
Read Only

Time Field
BIT
04 5 10 11 15

Date Field
BIT
04 58 9 15

Interpretation
Binary Number 0 to 29 => 0 to 58 second Binary Number 0 to 59 => 0 to 59 minutes Binary Number 0 to 23 => 0 to 23 hours

Interpretation
Binary Number 0 to 31 => 0 to 31 days Binary Number 0 to 12 => 0 to 12 months Year (base year as 1990)

FILE ALLOCATION TABLE

Purpose create disk space for files Contains entry for each cluster occupied by the file Contains information of the group of clusters that are assigned to the file Fields in FAT gives the cluster number that is allocated to file

FILE ALLOCATION TABLE

12 Bit Content 000H FF0 FF6H FF7H FF8 FFFH Any other Value 16 Bit Content 0000H FFF0 FFF6H FFF7H FFF8 FFFFH Any other Value 32 Bit Content 00000000H FFFFFFF0 FFFFFFF6H FFFFFFF7H FFFFFFF8 FFFFFFFFH Any other Value Interpretation Cluster is available Cluster is reserved Bad Cluster Last Cluster in the File Next Cluster in the File