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VGA Design On VHDL: Submitted By: Pranav Jain (UM 10504) Varun Yadav (UE 105106) Rachit Duggal (UM 10505)

This document describes designing a simple VGA display in VHDL and implementing it on a Spartan 3 FPGA board to observe the output on a monitor. The objectives are to understand VGA operation, design and implement a VGA in VHDL, and enhance VHDL skills. It discusses VGA scanning principles, block diagram, signals, output generation, pixel rates for 640x480 resolution, and the major tools used - Xilinx ISE, ModelSim simulator, and the Spartan 3 FPGA board with a VGA port.

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Pranav Jain
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64 views15 pages

VGA Design On VHDL: Submitted By: Pranav Jain (UM 10504) Varun Yadav (UE 105106) Rachit Duggal (UM 10505)

This document describes designing a simple VGA display in VHDL and implementing it on a Spartan 3 FPGA board to observe the output on a monitor. The objectives are to understand VGA operation, design and implement a VGA in VHDL, and enhance VHDL skills. It discusses VGA scanning principles, block diagram, signals, output generation, pixel rates for 640x480 resolution, and the major tools used - Xilinx ISE, ModelSim simulator, and the Spartan 3 FPGA board with a VGA port.

Uploaded by

Pranav Jain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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VGA design On VHDL

Submitted by: Pranav Jain(UM 10504) Varun Yadav(UE 105106) Rachit Duggal(UM 10505)

Objectives:
To understand the working of VGA To design and implement a simple VGA in VHDL and to observe its output on monitor using Spartan 3 FPGA kit. To enhance design skills in VHDL.

Principle of Working

Scanning of objects

Various parts in horizontal scan

BLOCK DIAGRAM OF VGA

Various signals in VGA

Final Outputs

Text representation scheme

Output generation

Pixel rate of VGA


p: the number of pixels in a horizontal scan line. For 640-by-480 resolution, it is pixels line p = 800 pixels l: the number of lines in a screen (i.e., a vertical scan). For 640-by-480 resolution, it is lines l = 525 -lines s: the number of screens per second. For flickering-free operation, we can set it to 60 screens per second. Therefore pixels processed per second are: p*l*s = 800*525*60 = 25M Therefore 25000 pixels are processed per second.

Final RTL of circuit

Final simulated waveform

Major tools
Xilinx ise software Model Sim, students version as Simulator Spartan-3 FPGA kit Spartan 3 is having a VGA port which is interfaced with monitor.

Problems
Typing errors Errors and warnings Problem in creation of bit file because of improper routing and mapping during synthesis.

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