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Layout Simulation Reults

Post layout simulation results were provided for different impedance, input current, process corners, and ADC output values. The extracted values were calculated by multiplying the count, input current, clock period, and frequency. Small differences between simulation and extraction were seen, possibly due to accuracy issues in the simulation tool. All post layout simulation results are located in the listed directories.

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Areeb Ali
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24 views1 page

Layout Simulation Reults

Post layout simulation results were provided for different impedance, input current, process corners, and ADC output values. The extracted values were calculated by multiplying the count, input current, clock period, and frequency. Small differences between simulation and extraction were seen, possibly due to accuracy issues in the simulation tool. All post layout simulation results are located in the listed directories.

Uploaded by

Areeb Ali
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Post layout simulation results

Impedance Input current Corner ADC output 200k 50nA TT 1001000 200k 50nA FF 1001000 200k 50nA SS 1011010 200k 50nA FS 1110000 200k 50nA SF 0100000 1M 10nA TT 0001100 1M 10nA FF 0100000 1M 10nA SS 0000110 1M 10nA FS 1001010 1M 10nA SF 1111111111100000 Iref=50nA, Tclk=10us, Fin=390Hz, Extracted value=Count*Iref*Tclk* Decimal value 72 72 90 112 32 12 32 6 74 -32 *fin Extracted value 44.1nA 44.1nA 55.14nA 68.6nA 19.6nA 7.35nA 19.6nA 3.7nA 45.3nA 19.6nA

Difference is due to the different currents at the input at different corners. For first case 200kohm, TT corner, I have counter value of 80 from spectre simulation which extracts to 49nA. With UltraSim this value is little less, possibly due to UltraSim accuracy. All post layout results are in: /simulation/ICFWTIS1_test_circuit/UltraSim/chip_layout_50n_tt/psf /simulation/ICFWTIS1_test_circuit/UltraSim/chip_layout_50n_ff/psf /simulation/ICFWTIS1_test_circuit/UltraSim/chip_layout_50n_ss/psf /simulation/ICFWTIS1_test_circuit/UltraSim/chip_layout_50n_fs/psf /simulation/ICFWTIS1_test_circuit/UltraSim/chip_layout_50n_sf/psf /simulation/ICFWTIS1_test_circuit/UltraSim/chip_layout_10n_tt/psf /simulation/ICFWTIS1_test_circuit/UltraSim/chip_layout_10n_ff/psf /simulation/ICFWTIS1_test_circuit/UltraSim/chip_layout_10n_ss/psf /simulation/ICFWTIS1_test_circuit/UltraSim/chip_layout_10n_fs/psf /simulation/ICFWTIS1_test_circuit/UltraSim/chip_layout_10n_sf/psf

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