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Qucs

A Tutorial
Getting Started with Digital Circuit Simulation

Mike Brinson
Copyright c 2006 Mike Brinson <[email protected]> Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.1 or any later version published by the Free Software Foundation. A copy of the license is included in the section entitled GNU Free Documentation License.

Introduction
On 21 January 2006 Qucs 0.0.8 was released by the Qucs development team. This is the rst version of the package to include digital circuit simulation based on VHDL. FreeHDL1 being chosen as the VHDL engine. In the period following the release of Qucs 0.0.8 there has been considerable activity centred around nding and correcting a number of bugs in the Qucs digital simulation code. Many of these xes are now included in the latest CVS code and will eventually form part of the next Qucs release. This tutorial note is an attempt on my part to communicate to other Qucs users a number of background ideas concerning the capabilities and limitations of the current state of Qucs VHDL simulation. Much of the information reported here was assembled by the author while assisting Michael Margraf to test and debug the VHDL code generated by Qucs. In the future, if there is enough interest in these notes, or indeed in Qucs VHDL simulation in general, I will update them as the Qucs digital simulation features are improved. Qucs digital simulation follows a complex set of steps that are mostly transparent to the software user. In step one, a schematic representing a digital circuit under test is drawn. This schematic consists of an interconnected group of Qucs digital components, one or more user dened digital subcircuits (if required), and a copy of the digital simulation icon with the timing or truth table parameters set. In step two, the information recorded on a circuit schematic is converted into a text le containing VHDL statements. These describe the circuit components, their connection, and a testbench for simulating circuit performance. Next, FreeHDL is launched by Qucs to convert the VHDL code le into a C++ source program. This is compiled to form an executable machine code simulation of the original circuit. Finally, Qucs runs this program, collects signal data as digital signal events take place and displays signal waveforms as a function of time or digital data in a truth table format. The VHDL code generated by Qucs 0.0.8 is limited in its scope by the following factors: Digital gates are described by data ow concurrent statements. Flip-ops and the digital signal generator are described by process statements. Component connection wires (signals) can only be of type bit as dened in the standard VHDL library2 .
1 2

The FreeHDL Project, http://www.freehdl.seul.org/. Signal type bit only denes logic signals 0 and 1. Care must be taken to ensure that signal

Digital bus structures are not allowed in this release of the Qucs package. Digital subcircuits can be drawn as schematics and associated with a symbol in a similar fashion to analogue subcircuits. Digital subcircuit pins can have type in, out, inout or analog. Qucs treats pins of type analog the same as VHDL pin type inout. Once dened digital subcircuits may be placed and connected to other components on schematics. Multiple copies of the same digital subcircuit are allowed on a single schematic. Digital subcircuits may also be nested; nesting has been tested to a depth of four.

Simulating simple digital circuits

The most basic form of digital circuit that can be simulated is one consisting entirely of Qucs predened digital components drawn on a schematic having only one level of design hierarchy. The truth table for a simple combinational circuit of this type is shown in Table 1. Output F can be expressed in sum of products Boolean form as

F = A.B.C + A.B.C + A.B.C + A.B.C

contention does not occur during simulation because the resulting logic state cannot be modelled with type bit. Signal contention can happen when two or more digital devices attempt to drive the same wire with logic 0 and logic 1 signals at the same time. Moreover, it is not possible to simulate the performance of tristate devices using VHDL signal type bit.

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

F 0 1 1 0 0 1 1 0

Table 1: Truth table for a logic circuit with inputs A, B, C and output F. 2

On minimisation, using Boolean algebra or a Karnaugh map, output F becomes

F = A.C + B.C
The schematic for example 1 is illustrated in Fig. 1. This diagram was constructed using the same techniques employed for drawing analogue schematics.

Notes on drawing digital schematics

The only predened Qucs components that can be used to draw a digital circuit schematic are (1) the digital components listed in the digital components icon window, (2) the ground symbol, and (3) the digital simulation icon. A useful tip when drawing digital schematics is to adopt the matrix approach shown in Fig. 1. Input signals ow from top to bottom of the schematic and output signals are positioned on the right-hand side of a horizontal line. This makes checking the circuit schematic for errors much easier than the case where diagrams have wires connecting components in an unstructured way. Input and output wires (signals) should be given names consistant with the circuit being simulated, A, B, C and F in Fig. 1. If the signal wires are not named by the user, Qucs will allocate them dierent arbitrary names. This can make identication and selection of signals for display on an output waveform graph, and indeed checking for errors in a large circuit, much more dicult than it need be. Notice in Fig. 1 the international symbols for the logic gates are shown on the schematic.

digital simulation
Y1

B C

Digi1 Type=TimeList time=200ns

&
CB Y2

1 &
Y4

Figure 1: Qucs schematic for minimised logic function F.

VHDL code generated by Qucs

Clicking the Qucs Simulate menu button (or pressing key F2) starts the simulation process. At an early phase in this process Qucs writes a text le to disk that contains the VHDL code for the circuit being simulated. This le can be displayed by clicking on the show last netlist drop down menu or by pressing key F6. The VHDL code produced by Qucs for the circuit shown in Fig. 1 is presented in Table 2. Signals identied by nnnet0 and nnnet1 in Table 2 have been allocated these names by Qucs; nnnet0 and nnnet1 are internal signal nets that are not named on the circuit schematic shown in Fig. 1. Fig. 2 illustrates the starting section of a typical Qucs digital functional waveform plot. This style of plot illustrates signal events without component delays. If required, signal delays can be specied for individual gates and other components (from the component edit properties menu). The VHDL code generated for components with delays will then reect such changes, for example adding a 10 ns delay to signal CB in Table 2 generates VHDL code CB <= not C a f t e r 10 ns ; Readers will probably have observed that the Qucs version number referred to in Table 2 VHDL listing is 0.0.9. This is the current CVS development version number. Qucs 0.0.9 includes a number of important bug xes. The remainder of these notes assume readers have downloaded, and recompiled, the latest CVS code 4

Qucs 0 . 0 . 9 t u t 1 e x 1 . s c h entity TestBench i s end entity ; use work . a l l ; architecture Arch TestBench of TestBench i s s i g n a l CB, A, B, F , C, nnnet0 , nnnet1 : b i t ; begin nnnet0 <= C and A; nnnet1 <= CB and B ; CB <= not C ; A: process begin A <= 0 ; wait f o r 40 ns ; A <= 1 ; wait f o r 40 ns ; end process ;

B : process begin B <= 0 ; wait f o r 20 ns ; B <= 1 ; wait f o r 20 ns ; end process ; F <= nnnet1 or nnnet0 ; C: process begin C <= 0 ; wait f o r 10 ns ; C <= 1 ; wait f o r 10 ns ; end process ; end architecture ;

Table 2: VHDL code for the circuit shown in Fig. 1.

from Sourceforge.net3 .
dtime a.X b.X c.X f.X 0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n 110n 120n 130n 140n 150n 160n 170n 180n 190n 200n

Figure 2: Digital functional waveforms for the circuit shown in Fig. 1.

Truth tables
Truth tables are one of the most fundamental and convenient ways of displaying digital circuit data. Qucs has a built-in facility that allows a truth table to be generated from a schematic drawing. This feature is particularly useful when checking minimised logic designs for errors. Lets consider a simple but instructive example: A logic circuit has four binary inputs A, B, C, and D, and one output P. Output P is logic 1 when inputs ABCD are numbers in the decimal sequence 3, 5, 7, 11 and 13. In Boolean sum of product form

P = A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D

This simplies to

P = D.(A.B + B C )
The schematic for the sum of products equation for P is shown in Fig. 3(a). Similarly Fig. 3(b) presents the schematic for a minimised P equation. Setting the digital simulation type to TruthTable, rather than TimeList, causes Qucs on pressing key F2, to generate a truth table based on the information provided on a circuit schematic. The number of truth table inputs, and indeed outputs, correspond to the number of input generators and the number of named outputs. Truth tables for both schematics are given in Table 3(a) and 3(b). Comparing these two tables clearly indicates that they are not identical and moreover conrms that the minimised solution is not correct. Reworking the minimisation procedure points to the error being a missing signal inversion. The correct Boolean equation for P is

P = D.(A.B + B C )
Please note, Qucs Linux release 0.0.8 will normally simulate single hierarchy digital circuits without error. However, Qucs 0.0.8 does fail at the VHDL to C++ conversion phase if a schematic includes more than one ground symbol.
3

A A Y1 B Y2

B C

C Y3 D

digital simulation
Digi1 Type=TruthTable

3(a): Schematic diagram for sum of products equation P

1 &
Y6

1
P

Y10

Y11

A A Y3

B B

C C

digital simulation
Digi1 Type=TruthTable

3(b): Schematic diagram for minimised equation P

1 &
Y7

1
Y8 Y6

=1
Y4

3(a): Truth table for sum of products equation P

00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 a.X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b.X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 c.X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 d.X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 p.X 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0

3(b): Truth table for minimised equation P

Digital subcircuits
Although it is possible to draw complex schematic diagrams using only the predened digital components supplied with Qucs, this technique can be extremely tedious, and is of course, prone to error. When drawing large schematics we require a design procedure that naturally subdivides groups of digital components into self contained units. These units can then be treated in the same way as basic digital components when placing and connecting them on a schematic drawing. In the world of analogue and digital circuit design such units are often called subcircuits.4 A subcircuit is dened by three major attributes plus a number of other properties. The major attributes are, rstly a digital circuit that denes circuit function, secondly a circuit symbol that depicts a circuit in a higher level of a design hierarchy, and thirdly the subcircuit input/output pins shown on the subcircuit symbol. Other properties include for example, signal path delays. The process for generating digital subcircuits is identical to that used for analogue subcircuits. It is best demonstrated by considering an example. Figure 4 shows the schematic for a four input combinational circuit. After drawing a subcircuit schematic, input and output5 pins are attached to signal ports. Input port pins of type in are shown on circuit diagrams as a green symbol, signals W, X, Y, and Z, in Fig. 4. Ouput port pins of type out are coloured red, signal G in Fig. 4. Signal ow through a port is indicated by the direction of the port symbol arrow head. Input/output signals, and any other signals that need to be easily identied, are also named. Once the subcircuit schematic is complete, pressing key F3 causes Qucs to generate a subcircuit symbol. The drawing tools listed as icons in the Qucs paintings window can be used to edit Qucs generated subcircuit symbols. The input/output port pins on a subcircuit symbol have the same type and name as those on the original subcircuit schematic. Fig. 5 shows the nished symbol for subcircuit COMB1. In these notes, symbol outlines are shown drawn in accordance with the international code for logic symbols6 . To test our new subcircuit we place its symbol on a blank drawing sheet and apply test signals to the input pins and observe the signals at the output pin. Fig. 6 shows a typical test circuit. Subcircuit Gen4bit generates a 4 bit test pattern synchronised
The circuit simulator SPICE is a well known example of a widely used CAD program that makes extensive use of subcircuits in circuit design. 5 Qucs 0.0.8 has a bug which causes a VHDL compile error when subcircuit pins are specied as type out. A work around for this bug is to specify subcircuit output pins as type analog. The Qucs routines that generate the circuit VHDL code convert pin type analog into VHDL type inout. FreeHDL is then able to compile the generated VHDL code without error. This bug has been corrected in Qucs 0.0.9. 6 Ian, Kampel, A practical introduction to the new logic symbols, Butterworths, 1985, ISBN 0-408-01461-X.
4

Z Y3

Y Y2

X Y1

1
XB

IN1

Y4 X WB W

&
Y5

IN2

G G

IN3

In4

Figure 4: Combinational logic circuit with inputs W, X, Y, Z, and output G. to the input of a digital clock. The specication for Gen4bit is given in the next section of these notes7 . The test pattern waveform and output signal G are shown plotted as a function of time in Fig. 7.

Subcircuit Gen4bit includes other nested subcircuits. Qucs 0.0.8 has a bug that causes VHDL compile errors with some congurations of nested subcircuits. This has been xed in version 0.0.9.

COMB1 W X Y Z W X G Y Z G

SUB File=name

Figure 5: Qucs symbol for a logic circuit with inputs W, X, Y, Z, and output G. 10

R R times=5ns; 1sec CLOCK CLOCK times=10ns; 10ns

B0 B1 B2 B3

B0 W B1 X B2 Y B3 Z

COMB1

Gen4bit SUB2 File=gen4bit.sch

digital simulation
COMB1 Type=TimeList time=1000 ns

SUB1 File=dtut1_ex2.sch

Figure 6: Test schematic for a logic circuit with inputs W, X, Y, Z, and output G.

dtime r.X clock.X b0.X b1.X b2.X b3.X g.X

10n

20n

30n

40n

50n

60n

70n

80n

90n

100n

110n

Figure 7: Digital functional waveforms for a logic circuit with inputs W, X, Y, Z, and output G.

Building a digital component library

The Qucs graphical user interface includes good project handling features. Combining these features with the Qucs subcircuit capabilities provides all the tools required for the development of a library of common digital components. Such a library can be stored in a master project and the individual component les imported into other projects when required. Here are a few components that I developed during a recent series of tests aimed at detecting bugs in the VHDL code generated by Qucs.

Logic zero
L0

SUB File=name

Logic one
L1

1
Y1

SUB File=name

G2bit - 2 bit pattern generator

RES CLK
R B0 B1

B0 B1

Gen2bit SUB File=name

B0 JK SUB1 J CLK CLK RES R K

R S

G4bit - 4 bit pattern generator

R R B0 B1 B2 CLK B3 Gen4bit SUB File=name
B0 B1 B1 B2 J K
S

1
SUB1 CLK CLK R J K
S

FF0 JK

1
B0 Q SUB2
R

0
Q Q SUB2 J SQ K Q

B1 B1

B0b

B1b

FF0

FF1

B0 B1 B2 B3

B2 B3 J K
S

0
Q0B

J K

Q Q

Q Q Q3B

Q1B

Q2B

FF1

FF2

FF3

MUX2to1 - 2 input to 1 output multiplexer

EN A Y 1 X L 0 0 D0 0 1 D1

MUX ENB A D0 D1 EN 0}G 0 1 0 1 SUB File=name

A A

1
Y1

& 1
Y2 Y Y

D0 D0 D1 D1

&
Y3

MUX4to1 - 4 input to 1 multiplexer

B X 0 0 1 1 A X 0 1 0 1 EN 1 0 0 0 0 Y 0 D0 D1 D2 D3

MUX ENB A B EN 0 1

0 3 Y

D0 D1 D2 D3

0 1 2 3 SUB File=name

ENB ENB

1
BB

1
AB

1
EN

Y1 D2 D1 D0

& 1
Y2 Y Y

2 bit adder
A1 B1 0 1

A2 B2

0 1

{
0 1 CO

S1 S2

SUB File=name

&
CI B2 A2 B1 A1

1
Y4

& =1
Y5 Y10

S2 S2

=1
Y6 Y8

& 1 &
Y9 Y3 C0 CO

Subcircuit VHDL code generated by Qucs

Qucs generates a separate entity-architecture model for each subcircuit. These component denitions are compiled into the work library by FreeHDL. Here is the VHDL code from two of the previous examples.

Gen2bit

entity S u b g e n 2 b i t i s port (CLK: in b i t ; R: in b i t ; nnout B0 : out b i t ; nnout B1 : out b i t ) ; end entity ; use work . a l l ; architecture A r c h S u b g e n 2 b i t of S u b g e n 2 b i t i s s i g n a l B0b , B1b , JK , nnnet0 , B0 , B1 : b i t ; begin FF0 : process ( nnnet0 , R, CLK) begin i f (R= 1 ) then B0 <= 0 ; e l s i f ( nnnet0 = 1 ) then B0 <= 1 ; e l s i f (CLK= 1 and CLK e v e n t ) then B0 <= (JK and not B0 ) or ( not JK and B0 ) ; end i f ; end process ; B0b <= not B0 ; FF1 : process ( nnnet0 , R, B0b ) begin i f (R= 1 ) then B1 <= 0 ; e l s i f ( nnnet0 = 1 ) then B1 <= 1 ; e l s i f ( B0b= 1 and B0b e v e n t ) then B1 <= (JK and not B1 ) or ( not JK and B1 ) ; end i f ; end process ; B1b <= not B1 ; SUB2 : entity S u b l o g i c z e r o port map ( nnnet0 ) ; nnout B0 <= B0 or 0 ; nnout B1 <= B1 or 0 ; SUB1 : entity S u b L o g i c o n e port map (JK ) ; end architecture ;

2 bit adder
entity S u b f a d d 2 b i t i s

port (A1 : in b i t ; B1 : in b i t ; A2 : in b i t ; B2 : in b i t ; CI : in b i t ; nnout S1 : out b i t ; nnout S2 : out b i t ; nnout CO : out b i t ) ; end entity ; use work . a l l ; architecture A r c h S u b f a d d 2 b i t of S u b f a d d 2 b i t i s s i g n a l nnnet0 , nnnet1 , nnnet2 , nnnet3 , nnnet4 , nnnet5 , nnnet6 , S2 , CO, S1 : b i t ; begin S1 <= CI xor B1 xor A1 ; nnnet0 <= B2 xor A2 ; nnnet1 <= nnnet0 and nnnet2 ; nnnet3 <= B2 and A2 ; nnnet2 <= nnnet4 or nnnet5 ; nnnet4 <= nnnet6 and CI ; nnnet5 <= B1 and A1 ; S2 <= B2 xor A2 xor nnnet2 ; CO <= nnnet3 or nnnet1 ; nnnet6 <= B1 xor A1 ; nnout S2 <= S2 or 0 ; nnout CO <= CO or 0 ; nnout S1 <= S1 or 0 ; end architecture ;

Notes on subcircuit VHDL generation

Qucs predened digital components generate concurrent data ow signal statements or process statements. Previously dened subcircuit symbols generate VHDL port map statements.

Type out entity port signals are prevented from being read as input signals by masking each output signal using the logic function signal-name OR 0.8 A VHDL use work . a l l ; statement is included before each subcircuit architecture denition to ensure that FreeHDL can nd any nested subcircuits 9 . The complete VHDL code le for a digital design is composed from an outer test bench entity-architecture model plus entity-architecture models for each subcircuit specied in the design,

Subcircuit nesting: A more complex design example

In theory there is no limit to the depth of subcircuit nesting allowed by Qucs. In practice most digital circuit schematics can be constructed with a maximum of four or ve levels of design hierarchy. Figure 8 shows an example that was used to test Qucs subcircuit nesting performance. The design is a simple RTL function that uses a multiplexer to transfer data from one of two input registers to a single output register. The next section of these notes outlines in detail the specication of the subcircuits needed to build the RTL design. A set of sample simulation waveforms showing the register transfer operation are illustrated in Fig. 9.

Attempting to read entity port signals of type out results in a VHDL compile error. Strictly speaking it should not be necessary to specically state the use of the work library as this library is normally visible at all times when compiling entity-architecture models. However, at this stage in the development of FreeHDL it does appear that it is necessary when using the default FreeHDL VHDL library mapping.
9

4 bit RTL design

CONTROL1 REG 4bit R1D D0 D1 D2 D3 Q0 Q1 Q2 Q3 R1Q0 R1Q1 R1Q2 R1Q3 CONTROL1 CONTROL2 CONTROL2 Num=2 Y1 AND_LOAD

SUB5

CLOCK CLOCK SUB13 SUB3 File=reg_4bit.sch

SUB14

Reg4bit
REG 4bit D0 D1 D2 D3 D0 D1 D2 D3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3

0} G

0 1 R3D0 R3D1 R3D2 R3D3 D0 D1 D2 D3 Q0 Q1 Q2 Q3 R3Q1 R3Q2 R3Q3 REG 4bit R3Q0

LOAD

0 LOAD 1 0 1 0 1 0 REG 4bit 1 R2Q0 D0 D1 D2 D3 Q0 Q1 Q2 Q3 R2Q1 R2Q2 R2Q3

MUX

LOAD

R2D

SUB1 File=quad_mux2to1.sch

SUB2 File=reg_4bit.sch

LOAD

digital simulation

VHDL Test circuit 2 Multi-hierarchy RTL circuit CONTROL2:R(SUB2)<- R(SUB4) not(CONTROL2) and CONTROL1 : R(SUB2)<-R(SUB3)

SUB4 File=reg_4bit.sch

Digi1 Type=TimeList time=1000 ns

Figure 8: Top level schematic.

LOAD CLOCK

LOAD

SUB File=name

D0 D D0 Num=1 Q0 EN Q0

SUB1 File=d_flip_flop_l.sch D1 D D1 Num=2 Q1 EN Q1

SUB2 File=d_flip_flop_l.sch D2 D D2 Num=3 EN Q2 Q2

SUB3 File=d_flip_flop_l.sch D3 D D3 Num=4 LOAD LOAD Num=5 CLOCK CLOCK Num=6 Q3 EN Q3

SUB4 File=d_flip_flop_l.sch

D ip-op with load enable

D EN CLOCK SUB File=name D EN Q

EN EN D

Mux2to1 0 G 0 1 0 1 D R Y1 Q

D CLOCK CLOCK

SUB1 File=mux2to1.sch

0
SUB2 File=logic_zero.sch

Mux2to1
A D0 D1 Mux2to1 0 G 0 1 0 1 SUB File=name
A

1
A Num=1 Y1

& 1
Y2

Y Y Num=4

&
D0 Num=2 D1 Num=3 D1 Y3

QuadMux
SEL 0} G 0 1

A0 B0 A1 B1 A2 B2 A3 B3

0 1 0 1 0 1 0 1

MUX Y0

SUB File=name

SEL Num=1 A0 Num=2 B0 Num=6

Mux2to1 0 G 0 1 0 1 SUB1 File=mux2to1.sch Mux2to1 0 G 0 1 0

Y0 Num=10

Y1 Num=11

A1 Num=3 B1 Num=7

1 SUB2 File=mux2to1.sch Mux2to1 0 G 0 1 0 Y2 Num=12

A2 Num=4 B2 Num=8

1 SUB3 File=mux2to1.sch Mux2to1 0 G 0 1 0 Y3 Num=13

A3 Num=5 B3 Num=9

1 SUB4 File=mux2to1.sch

dtime clock.X control1.X control2.X load.X r1q0.X r1q1.X r1q2.X r1q3.X r2q0.X r2q1.X r2q2.X r2q3.X r3d0.X r3d1.X r3d2.X r3d3.X r3q0.X r3q1.X r3q2.X r3q3.X

370n

380n

390n

400n

410n

420n

430n

440n

450n

460n

470n

480n

490n

500n

510n

520n

530n

540n

550n

Figure 9: Sample simulation waveforms for RTL design.

Update number one: May 2006

Although it is only a short time since the rst version of these digital tutorial notes was posted on the Qucs Sourceforge Web site, much has happened in the world of Qucs digital simulation. Bugs in the Qucs code have been found, and xed, and a range of new features added to the software. These expand the power of Qucs digital simulation and give users a glimpse of how the package will evolve in the future. The purpose of these notes is rstly to update readers as to the changes to Qucs digital simulation and secondly to explain how to use the new Qucs features. Please note however, they are not intended to teach readers how to program using VHDL.10

Bugs, corrections and small changes to the Qucs digital simulation code
All the bugs reported in the rst version of these notes have been corrected in the latest Qucs CVS code. These corrections are, of course, also included in Qucs release 0.0.9. During testing a number of other annoying, but signicant, bugs have also been found and eliminated, these include
A good introduction to the VHDL language and its application in digital system design can be found in Digital System Design using VHDL by Charles H. Roth, Jr, PWS Publishing Company, 1997, ISBN 0-534-95099-X.
10

Multiple input gates (three or more inputs) of types nand and nor failed at the FreeHDL compile stage due to an error in the VHDL code generated by Qucs. Signals names and, for example, component names constructed from a single letter that was an abbreviation for a physical unit failed to compile. Changing digital component time delays caused component connections on a schematic to be removed. GUI problems caused by errors in the symbol rotation and mirror code. Qucsconv code conversion errors caused the Qucs digital simulation cycle to fail before plotting TimeList waveforms. A number of changes to either the VHDL code generated by Qucs or the schematic capture GUI have been introduced, these include The VHDL code generated by Qucs for the ground symbol has been changed from gnd <= gnd and 0 ; to gnd <= 0 ; The symbol for digital inout ports has been changed from the analogue pin symbol to one that consists of the digital in and out pins drawn back-to-back. This reects the bidirectional status of an inout port. A more complete list of all the bug corrections and other program modications can be found in the Qucs change log les.

New digital simulation features

The ow diagram illustrated in Fig. 10 shows a number of dierent simulation routes for a digital circuit under test. The Qucs digital simulation facilities have been improved to include direct simulation of VHDL testbench code and the simulation of circuit schematics that include digital components specied by VHDL entity-architecture models. The various combinations that users can adopt for Qucs digital circuit entry are as follows:

1. Schematic circuit entry using predened digital component symbols, subcircuits generated using the same symbols and a copy of the digital simulation icon; this is the approach described in the rst version of these tutorial notes. 2. Circuit entry identical to 1 plus symbols for digital components specied by VHDL entity-architecture models. 3. Circuit entry using the Qucs VHDL code editor. The text entered describes both the circuit under test and the test vectors needed to drive the circuit inputs during simulation. Once the circuit under test has been entered into Qucs, clicking the Simulate menu button, or pressing key F2, starts the Qucs digital simulation process.

Limitations
Before describing the new digital simulation features it is important that readers understand the limitations that are inherent in the various digital simulation routes described in the last section and illustrated in the ow diagram shown in Fig. 10. Qucs schematic capture allows users to draw circuits consisting of predened component symbols and subcircuit symbols. At this stage in the development of the GUI digital signals must be of type bit (as dened in the VHDL standard library - library STD in the FreeHDL package) where individual signals ow through a single wire. Qucs schematic drawing bus structures of VHDL type bit-vector, for example, have not been implemented yet. This implies that the device symbol port pins must represent single signals. Similarly the nets connecting pins on more than one device can only be single signal nets and not bus structures. It is anticipated that this will change in a future Qucs release. Although the current release of FreeHDL is 0.0.1 the package implements a substantial subset of the entire VHDL language11 . The major features not supported by release 0.0.1 are: Shared variables. The following attributes; transaction, quiet, stable and delayed. User dened attributes. Groups.
A complete description of the 1987 and 1993 specications of the VHDL language can be found in The Designers Guide to VHDL by Peter J Ashenden, second edition 2002, Morgan Kaufmann Publishers, ISBN 1-55860-674-2.
11

VHDL entity/architecture code model

Generate VHDL symbol

rede!ined Qucs digital component symbols

Qucs GUI VHDL STD library elements Digital subcircuit symbols Generated using Qucs schematic capture

VHDL testbench code Entered using Qucs VHDL editor

Circuit drawing Entered using Qucs schematic capture

Digital circuit under test

SIMULATE
VHDL Testbench code

FreeHDL

Com i!e VHDL code "nd #ener"te m"chine code simu!"tion ro#r"m $or circuit under test

Run

"achine code simulation o! circuit under test

Qucs TimeList plot Simulation #utput data Qucs Truth Table View

Figure 10: Flow diagram of Qucs digital simulation routes.

Guarded signal assignments. Currently drivers cannot be switched o. The Qucs TimeList plotting program uses signal data output by the machine code simulation program generated by the FreeHDL package12 . A current limitation of the TimeList plotting program is that it can only display signals of type bit. Bus signal waveforms cannot be displayed. Given the above limitations it is therefore possible to write VHDL code that can be compiled by FreeHDL but will cause problems at either the schematic drawing or output waveform plotting stages in the Qucs simulation cycle. As Qucs develops it is expected that these limitations will be removed. On the subject of limitations one nal point to note: FreeHDL can simulate circuits described by the data types and other features found in the IEEE.std_logic_1164 library and other predened libraries. However, at this stage in the development of the Qucs software only the VHDL standard library may be used, implying that data type bit must be used to represent logic signals.

Using the Qucs VHDL editor

Qucs release 0.0.9 includes a VHDL text editor13 that has all the usual edit features plus colour coding of the various VHDL language statements. One unusual feature of this editor is a zoom control that allows the text size to be increased or decreased in a similar way to the schematic drawing zoom. The VHDL editor is included in the Qucs package for two primary purposes, rstly for purely text le VHDL simulation14 and secondly for the development of VHDL entity-architecture models that can be linked to schematic capture symbols. The latter increases signicantly the capabilities of the Qucs software in that it allows libraries of hand-crafted device models to be constructed. These new library devices will, given support by the general Qucs user community, greatly expand the potential use of the Qucs package. In this section the use of the VHDL text editor is demonstrated through a series of digital circuit simulation examples. The included VHDL listings indicate typical Qucs use of a number of the basic VHDL data types. The text also outlines any limitations imposed by Qucs.
The machine code simulation program outputs signal data in VCD format. This is then converted to the Qucs TimeList data format by the qucsconv utility program. 13 To launch the new VHDL editor click on the second icon from the left on the Qucs toolbar. It can also be activated using the key sequence Ctrl+Shift+V. 14 This is still the preferred method amongst many experienced users of VHDL. However, the circuit schematic drawing approach does seem to be growing in popularity.
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Example 1: A sum of products (SOP) combinational digital circuit. The Boolean equation15 for a SOP combinational circuit is:

f = W .X.Y .Z + W .X.Y .Z + W.Y .Z + W.X.Y.Z

The VHDL code for a structural model of this combinational circuit and its associated testbench is given in the following listing.
Qucs VHDL e d i t o r example 1 entity t e s t v e c t o r i s Test v e c t o r g e n e r a t o r . port ( z , y , x , w : out b i t ); end entity t e s t v e c t o r ; architecture b e h a v i o u r a l of t e s t v e c t o r i s begin pz : process i s begin z <= 0 ; wait f o r 20 ns ; z <= 1 ; wait f o r 20 ns ; end process pz ; py : process i s begin y <= 0 ; wait f o r 40 ns ; y <= 1 ; wait f o r 40 ns ; end process py ; px : process i s begin x <= 0 ; wait f o r 80 ns ; x <= 1 ; wait f o r 80 ns ; end process px ; pw : process i s begin w <= 0 ; wait f o r 160 ns ; w <= 1 ; wait f o r 160 ns ; end process pw ; end architecture b e h a v i o u r a l ; entity and4 i s 4 i n p u t and g a t e .
The Boolean equation for function f has not been minimised. It is in a form derived directly from a truth table and is introduced purely as an example to demonstrate the use of the Qucs VHDL editor.
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port ( in1 , in2 , in3 , i n 4 : in b i t ; out1 : out b i t ); end entity and4 ; architecture d a t a f l o w of and4 i s begin out1 <= i n 1 and i n 2 and i n 3 and i n 4 ; end architecture d a t a f l o w ; entity and3 i s 3 i n p u t and g a t e . port ( in1 , in2 , i n 3 : in b i t ; out1 : out b i t ); end entity and3 ; architecture d a t a f l o w of and3 i s begin out1 <= i n 1 and i n 2 and i n 3 ; end architecture d a t a f l o w ; entity o r 4 i s 4 i n p u t or g a t e . port ( in1 , in2 , in3 , i n 4 : in b i t ; out1 : out b i t ); end entity o r 4 ; architecture d a t a f l o w of o r 4 i s begin out1 <= i n 1 or i n 2 or i n 3 or i n 4 ; end architecture d a t a f l o w ; entity i n v i s I n v e r t e r . port ( i n 1 : in b i t ; out1 : out b i t ); end entity i n v ; architecture d a t a f l o w of i n v i s begin out1 <= not i n 1 ; end architecture d a t a f l o w ;

entity t e s t b e n c h i s Test bench o u t e r e n t i t y wrapper . end entity t e s t b e n c h ; l i b r a r y work ; use work . a l l ; architecture s t r u c t u r a l of t e s t b e n c h i s T e s t b e n c h a r c h i t e c t u r e . s i g n a l b0 , b1 , b2 , b3 , zb , yb , xb , wb , a , b , c , d , f : b i t ; begin d1 : entity t e s t v e c t o r port map( b0 , b1 , b2 , b3 ) ; d2 : entity i n v port map( b0 , wb ) ; d3 : entity i n v port map( b1 , xb ) ; d4 : entity i n v port map( b2 , yb ) ; d5 : entity i n v port map( b3 , zb ) ; d6 : entity and4 port map( zb , yb , b1 , wb , a ) ; d7 : entity and4 port map( zb , yb , xb , wb , b ) ; d8 : entity and3 port map( zb , yb , b0 , c ) ; d9 : entity and4 port map( b0 , b1 , b2 , b3 , d ) ; d10 : entity o r 4 port map( a , b , c , d , f ) ; end architecture s t r u c t u r a l ;

On entry of this code into the Qucs VHDL text editor the text is colour coded. Unfortunately, the colour coding is lost when printed, or pasted into a word processor, or a layout package like LaTeX. The structure of the VHDL listing follows the normal convention for text based VHDL simulation. All component entity-architecture models must be dened before they are referenced in other component models. The simulation test bench must be the last entity-architecture model in the VHDL listing. During the VHDL compile phase FreeHDL compiles the component entity-architecture models to the work library16 . These compiled models are then made available to the simulation test bench through the use of the VHDL use statement inserted in the listing prior to the testbench architecture statement. Once the VHDL listing for the simulation has been typed into the Qucs VHDL code editor, pressing key F2 starts the simulation process. The simulation duration can be set using the Document Settings in the File dropdown menu (or by pressing the Ctrl+. keys). Any VHDL syntax errors, or indeed typos, are written to le and can be viewed by pressing key F5. Obviously if errors are reported these need to be corrected using the VHDL text editor and the simulation cycle restarted. A typical TimeList output for editor example 1 is shown in
In most VHDL implementations library work is always visible and there is no requirement to make it visible by using the library and use statements. However, FreeHDL appears to need these statements at the linking phase otherwise the VHDL compiler fails.
16

Fig. 11.
dtime b0.X b1.X b2.X b3.X f.X 0 20n 40n 60n 80n 100n 120n 140n 160n 180n 200n 220n 240n 260n 280n 300n 320n

Figure 11: Sample simulation waveforms for VHDL editor example 1 design. Example 2: VHDL editor example 1 modelled using dataow VHDL statements. The VHDL code for the second example is given in the next listing. The VHDL style chosen to model the circuit is based on VHDL dataow concurrent signal assignments. The input text vectors are generated using a simple state machine rather than separate process statements. The test vector generator port specication uses entirely single signal bit types and can be easily interfaced, without problems, to other components connected on a Qucs schematic diagram. The procedure for generating schematic capture component symbols from entity - architecture models is introduced in a later section of these notes. The use of bit vector bus constructions is also illustrated in this example. Qucs allows the use of bit vectors as signals or variables in VHDL models provided all signals in the port statement of entity declaration are of type bit only.17 A typical TimeList output for editor example 2 is shown in Fig. 12.
Qucs VHDL e d i t o r example 2 entity t e s t v e c t o r a i s port ( RESET, CLOCK : in b i t ; B0 , B1 , B2 , B3 : out b i t ); end entity t e s t v e c t o r a ; architecture b e h a v i o u r a l of t e s t v e c t o r a i s s i g n a l p r e s e n t s t a t e , n e x t s t a t e : b i t v e c t o r ( 3 downto 0):= 1111 ; begin
This is a restriction of Qucs 0.0.9 and will be removed in a later release of the package. Also note signals of type bit vector that are declared in architecture denitions are listed in the TimeList plot signal dialogue. However, a text message saying no data results if an attempt is made to display them. Again this limitation will be removed in a later release of Qucs.
17

p1 : process (CLOCK ) i s begin i f (CLOCK e v e n t and CLOCK= 1 ) then p r e s e n t s t a t e <= n e x t s t a t e ; end i f ; end process p1 ; p2 : process (RESET, present state ) is begin i f (RESET = 1 ) then n e x t s t a t e <= 1111 ; end i f ; case p r e s e n t s t a t e i s when 0000 => n e x t s t a t e <= 0001 ; when 0001 => n e x t s t a t e <= 0010 ; when 0010 => n e x t s t a t e <= 0011 ; when 0011 => n e x t s t a t e <= 0100 ; when 0100 => n e x t s t a t e <= 0101 ; when 0101 => n e x t s t a t e <= 0110 ; when 0110 => n e x t s t a t e <= 0111 ; when 0111 => n e x t s t a t e <= 1000 ; when 1000 => n e x t s t a t e <= 1001 ; when 1001 => n e x t s t a t e <= 1010 ; when 1010 => n e x t s t a t e <= 1011 ; when 1011 => n e x t s t a t e <= 1100 ; when 1100 => n e x t s t a t e <= 1101 ; when 1101 => n e x t s t a t e <= 1110 ; when 1110 => n e x t s t a t e <= 1111 ; when 1111 => n e x t s t a t e <= 0000 ; end case ; B3 <= n e x t s t a t e ( 3 ) ; B2 <= n e x t s t a t e ( 2 ) ; B1 <= n e x t s t a t e ( 1 ) ; B0 <= n e x t s t a t e ( 0 ) ; end process p2 ; end architecture b e h a v i o u r a l ; l i b r a r y work ; use work . a l l ; entity t e s t b e n c h i s end entity t e s t b e n c h ; architecture d a t a f l o w of t e s t b e n c h i s s i g n a l r e s e t , c l k , b0 , b1 , b2 , b3 , zb : b i t ;

s i g n a l yb , xb , wb , a , b , c , d , f : b i t ; begin p1 : process i s begin c l k <= 0 ; wait f o r 10 ns ; c l k <= 1 ; wait f o r 10 ns ; end process p1 ; p2 : process i s begin r e s e t <= 1 ; wait f o r 10 ns ; r e s e t <= 0 ; wait f o r 2000 ns ; end process p2 ; d1 : entity t e s t v e c t o r a port map( r e s e t , c l k , b0 , b1 , b2 , b3 ) ; Data f l o w model o f c o m b i n a t i o n a l c i r c u i t wb <= not b0 ; xb <= not b1 ; yb <= not b2 ; zb <= not b3 ; a <= (wb and b1 ) and ( yb and zb ) ; b <= (wb and xb ) and ( yb and zb ) ; c <= b0 and ( yb and zb ) ; d <= ( b0 and b1 ) and ( b2 and b3 ) ; f <= a or b or c or d ; end architecture d a t a f l o w ;
dtime reset.X b0.X b1.X b2.X b3.X f.X 0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n 110n 120n 130n 140n 150n 160n 170n

Figure 12: Sample simulation waveforms for VHDL editor example 2 design. Example 3: VHDL editor example 1 modelled using VHDL process statements and variables. The VHDL code for the third example is given in the listing at the end of this paragraph. In this example the use of VHDL variables is illustrated. The VHDL code for the vector generator is a little unusual in that rather than using the traditional two process design employing signals, a single process statement employing variables undertakes both the calculation of 35

the next state data and the transfer of the next state information to the present state. This approach is necessary because FreeHDL does not allowed shared variables. Once again in this example only single bit data is passed via the entity statement to the device under test. The device under test is represented by a truth table encoded in a process statement. This is not the most elegant code but it does serve the purpose of demonstrating the use of dierent VHDL constructions and data types in Qucs digital simulation. A typical TimeList plot for VHDL editor example 3 is shown in Fig. 13. Comparison of the three output plots for the VHDL editor examples indicates that all the simulation results are very similar with some slight dierences in the start up phase following the RESET pulse changing from logic 1 to logic 0. This is probably an eect due to the dierent initialisation sequences for each of the test vector models.
Qucs VHDL e d i t o r example 3 entity t e s t v e c t o r b i s port ( RESET, CLOCK : in b i t ; B0 , B1 , B2 , B3 : out b i t ); end entity t e s t v e c t o r b ; architecture b e h a v i o u r a l of t e s t v e c t o r b i s begin p1 : process (RESET, CLOCK) i s variable p r e s e n t s t a t e , n e x t s t a t e : b i t v e c t o r ( 3 downto 0):= 0000 ; begin i f (RESET = 1 ) then n e x t s t a t e := 0000 ; e l s i f (CLOCK e v e n t and CLOCK= 1 ) then p r e s e n t s t a t e := n e x t s t a t e ; case p r e s e n t s t a t e i s when 0000 => n e x t s t a t e := 0001 ; when 0001 => n e x t s t a t e := 0010 ; when 0010 => n e x t s t a t e := 0011 ; when 0011 => n e x t s t a t e := 0100 ; when 0100 => n e x t s t a t e := 0101 ; when 0101 => n e x t s t a t e := 0110 ; when 0110 => n e x t s t a t e := 0111 ; when 0111 => n e x t s t a t e := 1000 ; when 1000 => n e x t s t a t e := 1001 ; when 1001 => n e x t s t a t e := 1010 ; when 1010 => n e x t s t a t e := 1011 ;

when 1011 => n e x t s t a t e := 1100 ; when 1100 => n e x t s t a t e := 1101 ; when 1101 => n e x t s t a t e := 1110 ; when 1110 => n e x t s t a t e := 1111 ; when 1111 => n e x t s t a t e := 0000 ; end case ; end i f ; B3 <= n e x t s t a t e ( 3 ) ; B2 <= n e x t s t a t e ( 2 ) ; B1 <= n e x t s t a t e ( 1 ) ; B0 <= n e x t s t a t e ( 0 ) ; end process p1 ; end architecture b e h a v i o u r a l ; l i b r a r y work ; use work . a l l ; entity t e s t b e n c h i s end entity t e s t b e n c h ; architecture d a t a f l o w of t e s t b e n c h i s s i g n a l r e s e t , c l k , b0 , b1 , b2 , b3 , f : bit ; begin p1 : process i s begin c l k <= 0 ; wait f o r 10 ns ; c l k <= 1 ; wait f o r 10 ns ; end process p1 ; p2 : process i s begin r e s e t <= 1 ; wait f o r 10 ns ; r e s e t <= 0 ; wait f o r 2000 ns ; end process p2 ; d1 : entity t e s t v e c t o r b port map( r e s e t , c l k , b0 , b1 , b2 , b3 ) ; B e h a v i o u r a l model o f c o m b i n a t i o n a l c i r c u i t p3 : process ( b3 , b2 , b1 , b0 ) i s variable SEL : b i t v e c t o r ( 3 downto 0 ) ; begin SEL := b3&b2&b1&b0 ; i f (SEL = 0010 ) then f <= 1 ; e l s i f (SEL = 0000 ) then f <= 1 ; e l s i f (SEL = 1111 ) then f <= 1 ;

e l s i f (SEL = 0001 ) then f <= 1 ; e l s i f (SEL = 0011 ) then f <= 1 ; e l s e f <= 0 ; end i f ; end process p3 ; end architecture d a t a f l o w ;
dtime reset.X b0.X b1.X b2.X b3.X f.X 0 10n 20n 30n 40n 50n 60n 70n 80n 90n 100n 110n 120n 130n 140n 150n 160n 170n

Figure 13: Sample simulation waveforms for VHDL editor example 3 design.

Linking VHDL entity-architecture models to Qucs schematic device symbols

VHDL was originally developed as a hardware description language for specifying digital systems. Indeed many engineers still prefer to describe digital systems entirely in VHDL statements rather than use schematic drawings. Once written VHDL code is saved as a text le and becomes the input data for a VHDL compiler/simulation package. Through popular demand a number of digital synthesis/simulator CAD tools18 have started to include a facility that links VHDL model code to a schematic capture symbol. It is then, of course, possible to use a schematic diagram as the main entry media19 when designing and simulating a digital design. Qucs release 0.0.9 has such a facility, allowing VHDL code models to be linked to schematic symbols. When drawing digital design schematics, these user dened symbols may be mixed with the Qucs predened digital symbols and other user dened subcircuit symbols. The process for linking VHDL code to Qucs schematic drawing symbols is straightforward and will be illustrated in these notes through two examples. Example 4: A 4 bit test vector pattern generator.
See for example the XILINX, WebPACK software at http//www.xilinx.com/ise/logic_ design_prod/webpack.htm. 19 Please note that at the start of the VHDL simulation process schematic drawings are converted into a VHDL text le.
18

Shown in Table 4 is the VHDL entity-architecture model listing for a 4 bit binary pattern generator. The VHDL code is identical to the test vector code introduced in the third VHDL editor example. After entering the VHDL entity-architecture model code using the Qucs VHDL editor the nished text is saved in a le with a suitable name and le extension vhdl. Qucs then lists the model under the VHDL project category. Simply clicking on a model name in the VHDL category, with the left hand mouse button, then moving the mouse pointer to a suitable position on a schematic, causes Qucs to move a symbol that represents the model onto the schematic drawing sheet. Placement of the symbol at the position located by the mouse pointer is achieved by clicking the left hand mouse button. The procedure is identical to that used to select and place the Qucs predened symbols on a schematic drawing. Qucs automatically generates a rectangular symbol with a name called VHDL that has the same number of pins as the port statement listed in the VHDL model entity statement. Each of the pins is given a name that corresponds to a name in the entity statement. Qucs xes the order of the pins on the generated symbol. It appears that it is not possible to edit this symbol. However, subcircuit in, out or inout port symbols can be attached to symbol VHDL and a user edited symbol generated. Fig. 14 shows the Qucs generated VHDL symbol with attached ports for the model listed in Table 4. The edited symbol for the 4 bit binary pattern generator is illustrated in Fig. 15. Notice that in Fig. 15 the order of the pins has been changed to reect the natural order for a device with its input pins on the left and output pins on the right. VHDL model symbols can also be generated by placing the VHDL le component, this is located in the digital components viewlist, on a schematic. On editing the VHDL le name property of this device to the name of a VHDL entity-architecture model le, Qucs automatically generates a VHDL symbol. Dening your own symbol then proceeds in a similar fashion to the way described above. Example 5: A 4 bit full adder. VHDL model symbols may be combined with either the Qucs predened digital component symbols or other subcircuit symbols. In this example a VHDL model for a simple one bit full adder is connected four times in a serial fashion to form a 4 bit full adder. The VHDL model code for a simple one bit full adder is given in Table 5. The associated symbol diagrams for the one bit full adder are illustrated in Fig. 16 and Fig. 17.

entity p a t g e n 4 b i t i s port ( RESET, CLOCK : in b i t ; B0 , B1 , B2 , B3 : out b i t ); end entity p a t g e n 4 b i t ; architecture b e h a v i o u r a l of p a t g e n 4 b i t i s begin p1 : process (RESET, CLOCK) i s variable p r e s e n t s t a t e , n e x t s t a t e : b i t v e c t o r ( 3 downto 0):= 0000 ; begin i f (RESET = 1 ) then n e x t s t a t e := 0000 ; e l s i f (CLOCK e v e n t and CLOCK= 1 ) then p r e s e n t s t a t e := n e x t s t a t e ; case p r e s e n t s t a t e i s when 0000 => n e x t s t a t e := 0001 ; when 0001 => n e x t s t a t e := 0010 ; when 0010 => n e x t s t a t e := 0011 ; when 0011 => n e x t s t a t e := 0100 ; when 0100 => n e x t s t a t e := 0101 ; when 0101 => n e x t s t a t e := 0110 ; when 0110 => n e x t s t a t e := 0111 ; when 0111 => n e x t s t a t e := 1000 ; when 1000 => n e x t s t a t e := 1001 ; when 1001 => n e x t s t a t e := 1010 ; when 1010 => n e x t s t a t e := 1011 ; when 1011 => n e x t s t a t e := 1100 ; when 1100 => n e x t s t a t e := 1101 ; when 1101 => n e x t s t a t e := 1110 ; when 1110 => n e x t s t a t e := 1111 ; when 1111 => n e x t s t a t e := 0000 ; end case ; end i f ; B3 <= n e x t s t a t e ( 3 ) ; B2 <= n e x t s t a t e ( 2 ) ; B1 <= n e x t s t a t e ( 1 ) ; B0 <= n e x t s t a t e ( 0 ) ; end process p1 ; end architecture b e h a v i o u r a l ;

Table 4: VHDL code for a 4 bit pattern generator.

RESET

CLOCK

CLOCK Num=2

RESET Num=1
B0 vhdl B1

B1 Num=4

B0 Num=3
B2 B3

B3 Num=6

B2 Num=5

Figure 14: Qucs generated VHDL symbol with subcircuit ports for test pattern generator.
patgen 4bit SUB File=name B0 B1 CLOCK B2 B3 B0 B1 B2 B3

RESET

Figure 15: User dened 4 bit pattern generator symbol.

F u l l adder 1 b i t entity f u l l a d d e r i s port ( a , b , c i n : in b i t ; sum , c o u t : out b i t ); end entity f u l l a d d e r ; architecture d a t a f l o w of f u l l a d d e r i s begin sum <= ( a xor b ) xor c i n ; c o u t <= ( a and b ) or ( a and c i n ) or ( b and c i n ) ; end architecture d a t a f l o w ;

Table 5: VHDL code for a 1 bit full adder. 41

a
cin vhdl sum

sum

cin
cout

cout

Figure 16: Qucs generated VHDL symbol with subcircuit ports for one bit full adder.

a b cin CI CO

SUB File=name sum cout

Figure 17: User dened one bit full symbol. Figure 18 shows the schematic for a simple 4 bit ripple adder. The corresponding user dened symbol for the 4 bit full adder is given in Fig. 19.
SUB1

sum0

a0 b0 cin

SUB2

sum1

a1 b1 CI

SUB3

sum2

a3 b2 CI

SUB4

sum3

a4 b3 CI

cout

Figure 18: 4 bit full adder schematic.

Generating VHDL code from Qucs schematic drawings

Pressing key F2 causes Qucs to simulate the design entered by the Qucs user. The input data for a simulation is either a VHDL text le, saved from the VHDL text editor, or a VHDL code le generated by Qucs using the information encoded on a schematic drawing. In this section of these tutorial notes a larger design is introduced and the resulting VHDL code and simulation results are discussed. 43

a0 a1 a3 a4 b0 b1 b2 b3 cin

sum0 a

}
3 0

sum1 sum2 sum3

}b
3 CI

cout

SUB File=name

Figure 19: User dened 4 bit full adder symbol. b3 a3 a0b3 a1b3 a1b2 a2b3 a2b2 a2b1 a3b3 a3b2 a3b1 a3b0 r7 r6 r5 r4 r3 b2 a2 a0b2 a1b1 a2b0 r2 b1 b0 a1 a0 a0b1 a0b0 a1b0

Table 6: Product table for a 4 bit by 4 bit combinational multiplier. The example chosen for this purpose is a 4 bit by 4 bit combinational digital multiplier. Both the 4 bit pattern generator and the 4 bit full adder outlined in the last section form part of the central core of the 4 bit multiplier design and its associated testbench. Table 6 shows the multiplication product table for a 4 bit by 4 bit combinational binary multiplier. Inputs to the device are binary bits a3 a2 a1 a0 and b3 b2 b1 b0. The 4 by 4 multiplier device requires 16 and gates (to generate the multiplier product terms), three four bit full adders (to sum the output r terms) and two 4 bit pattern generators to test the 256 possible input states. The multiplier output is represented in Table 6 by r7 r6 r5 r4 r3 r2 r1 and r0. The circuit schematic for the 4 bit by 4 bit multiplier and test bench are given in Fig. 20. The VHDL code for this example is presented in the following listing. This listing

was generated by Qucs20 . A small section of the TimeList waveform plot for the digital multiplier is shown in Fig. 21. At 1.74 micro seconds input a is 0101, input b is 0111 and the output r is 00100011 which is 35 in decimal. Taking a few random checks of the simulation results indicates that the 4 bit by 4 bit multiplier design works correctly. Notice that the VHDL code generated by Qucs for the 4 bit multiplier does not contain any propagation delay timing data. This could be added to the and gates, if required. However, at this stage in the development of Qucs digital simulation passing timing data, and other parameters, from device symbols generated from VHDL models has not been implemented yet. The use of VHDL generics is an obvious way this could be done. Generics are allowed, of course, in text based VHDL simulations.

Some readers will have noticed that the naming scheme for internal signal nets is dierent in the multiplier VHDL listing when compared to the VHDL listings in the rst version of these notes. Towards the end of the 0.0.9 development phase the naming convention employed by Qucs was changed to give a more exible structure.

CLOCK

digital simulation
Digi1 Type=TimeList time=5000 ns

SUB5

A3 A2 A1 A0

Figure 20: A 4 bit by 4 bit combinational digital multiplier.

1
SUB3 R patgen 4bit B2 B3 B1 B0 B2 B3 B1 R B3 B2 B1 B0 patgen 4bit B0

R SUB1

CLOCK

&
Y2 &

Y3 & Y4 & Y5 & Y6 & Y7 & Y8 & Y9 &

}
3 0

}b
3 CI

SUB4

}a
3 0

& Y10 & Y11 & Y12 & Y13 & Y14 & Y15 & Y16
Y17

}b
3 CI SUB6

R3 R4

}a
3 0

R5 R6

R7 CO

}b
3 CI

SUB7 File=full_adder_4 bit.sch

Qucs 0 . 0 . 9 /mnt/ hda2 / v h d l c o m p l i b p r j / m u l t i p l i e r 4 b x 4 b i t . s c h entity p a t g e n 4 b i t i s port ( RESET, CLOCK : in b i t ; B0 , B1 , B2 , B3 : out b i t ); end entity p a t g e n 4 b i t ; architecture b e h a v i o u r a l of p a t g e n 4 b i t i s begin p1 : process (RESET, CLOCK) i s variable p r e s e n t s t a t e , n e x t s t a t e : b i t v e c t o r ( 3 downto 0 ) := 0000 ; begin i f (RESET = 1 ) then n e x t s t a t e := 0000 ; e l s i f (CLOCK e v e n t and CLOCK= 1 ) then p r e s e n t s t a t e := n e x t s t a t e ; case p r e s e n t s t a t e i s when 0000 => n e x t s t a t e := 0001 ; when 0001 => n e x t s t a t e := 0010 ; when 0010 => n e x t s t a t e := 0011 ; when 0011 => n e x t s t a t e := 0100 ; when 0100 => n e x t s t a t e := 0101 ; when 0101 => n e x t s t a t e := 0110 ; when 0110 => n e x t s t a t e := 0111 ; when 0111 => n e x t s t a t e := 1000 ; when 1000 => n e x t s t a t e := 1001 ; when 1001 => n e x t s t a t e := 1010 ; when 1010 => n e x t s t a t e := 1011 ; when 1011 => n e x t s t a t e := 1100 ; when 1100 => n e x t s t a t e := 1101 ; when 1101 => n e x t s t a t e := 1110 ; when 1110 => n e x t s t a t e := 1111 ; when 1111 => n e x t s t a t e := 0000 ; end case ; end i f ; B3 <= n e x t s t a t e ( 3 ) ; B2 <= n e x t s t a t e ( 2 ) ; B1 <= n e x t s t a t e ( 1 ) ; B0 <= n e x t s t a t e ( 0 ) ; end process p1 ; end architecture b e h a v i o u r a l ; entity S u b p a t g e n 4 b i t i s

port ( n e t n e t 0 : in b i t ; n e t n e t 5 : in b i t ; n e t o u t n e t n e t 1 : out b i t ; n e t o u t n e t n e t 3 : out b i t ; n e t o u t n e t n e t 2 : out b i t ; n e t o u t n e t n e t 4 : out b i t ) ; end entity ; use work . a l l ; architecture A r c h S u b p a t g e n 4 b i t of S u b p a t g e n 4 b i t i s signal net net1 , net net2 , net net3 , net net4 : bit ; begin n e t o u t n e t n e t 1 <= n e t n e t 1 or 0 ; n e t o u t n e t n e t 2 <= n e t n e t 2 or 0 ; n e t o u t n e t n e t 3 <= n e t n e t 3 or 0 ; n e t o u t n e t n e t 4 <= n e t n e t 4 or 0 ; X1 : entity p a t g e n 4 b i t port map ( n e t n e t 0 , n e t n e t 5 , net net1 , net net3 , net net2 , net net4 ) ; end architecture ;

l o g i c z e r o . v h d l entity l o g i c z e r o i s port ( Y : out b i t ); end entity l o g i c z e r o ; architecture d a t a f l o w of l o g i c z e r o i s begin Y <= 0 ; end architecture d a t a f l o w ;

entity S u b l o g i c z e r o i s port ( n e t o u t n e t Y : out b i t ) ; end entity ; use work . a l l ; architecture A r c h S u b l o g i c z e r o of S u b l o g i c z e r o i s s i g n a l netY : b i t ; begin X1 : entity l o g i c z e r o port map ( netY ) ;

n e t o u t n e t Y <= netY or 0 ; end architecture ;

entity S u b f u l l a d d e r 1 b i t i s port ( n e t n e t 0 : in b i t ; n e t n e t 1 : in b i t ; n e t n e t 2 : in b i t ; n e t o u t n e t n e t 3 : out b i t ; n e t o u t n e t n e t 4 : out b i t ) ; end entity ; use work . a l l ; architecture A r c h S u b f u l l a d d e r 1 b i t of S u b f u l l a d d e r 1 b i t i s signal net net3 , net net4 : bit ; begin X1 : entity f u l l a d d e r port map ( n e t n e t 0 , n e t n e t 1 , net net2 , net net3 , net net4 ) ; n e t o u t n e t n e t 3 <= n e t n e t 3 or 0 ; n e t o u t n e t n e t 4 <= n e t n e t 4 or 0 ; end architecture ;

entity S u b port ( n e t net net net net

full adder 4bit is n e t 0 : in b i t ; n e t 1 : in b i t ; n e t 2 : in b i t ; n e t 3 : in b i t ; n e t 4 : in b i t ;

n e t n e t 5 : in b i t ; n e t n e t 6 : in b i t ; n e t n e t 1 3 : in b i t ; n e t n e t 7 : in b i t ; n e t o u t n e t n e t 8 : out b i t ; n e t o u t n e t n e t 9 : out b i t ; n e t o u t n e t n e t 1 0 : out b i t ; n e t o u t n e t n e t 1 1 : out b i t ; n e t o u t n e t n e t 1 2 : out b i t ) ; end entity ; use work . a l l ; architecture A r c h S u b f u l l a d d e r 4 b i t of S u b f u l l a d d e r 4 b i t i s signal net net14 , net net15 , net net16 , net net8 , net net9 , net net10 , net net11 , net net12 : bit ; begin n e t o u t n e t n e t 8 <= n e t n e t 8 or 0 ; n e t o u t n e t n e t 9 <= n e t n e t 9 or 0 ; n e t o u t n e t n e t 1 0 <= n e t n e t 1 0 or 0 ; n e t o u t n e t n e t 1 1 <= n e t n e t 1 1 or 0 ; n e t o u t n e t n e t 1 2 <= n e t n e t 1 2 or 0 ; SUB4 : entity S u b f u l l a d d e r 1 b i t port map ( n e t n e t 3 , n e t n e t 1 3 , net net14 , net net11 , net net12 ) ; SUB3 : entity S u b f u l l a d d e r 1 b i t port map ( n e t n e t 2 , n e t n e t 6 , net net15 , net net10 , net net14 ) ; SUB2 : entity S u b f u l l a d d e r 1 b i t port map ( n e t n e t 1 , n e t n e t 5 , net net16 , net net9 , net net15 ) ; SUB1 : entity S u b f u l l a d d e r 1 b i t port map ( n e t n e t 0 , n e t n e t 4 , net net7 , net net8 , net net16 ) ; end architecture ; entity TestBench i s end entity ; use work . a l l ; architecture Arch TestBench of TestBench i s s i g n a l netA0 , netA1 , netA2 , netA3 , netR , netB0 , netB1 , netB2 , netB3 , netR0 , netR1 , netR2 ,

netR3 , netR4 , netR5 , netR6 , netR7 , netCLOCK , net net0 , net net1 , net net2 , net net3 , net net4 , net net5 , net net6 , net net7 , net net8 , net net9 , net net10 , net net11 , net net12 , net net13 , net net14 , net net15 , net net16 , net net17 , net net18 , net net19 , net net20 , net net21 , net net22 , net net23 , net net24 : bit ; begin SUB3 : entity S u b p a t g e n 4 b i t port map ( netR , n e t n e t 0 , netA0 , netA1 , netA2 , netA3 ) ; SUB1 : entity S u b p a t g e n 4 b i t port map ( netR , netCLOCK , netB0 , netB1 , netB2 , netB3 ) ; R: process begin netR <= 1 ; netR <= 0 ; end process ;

wait f o r 10 ns ; wait f o r 2000 ns ;

CLOCK: process begin netCLOCK <= 0 ; netCLOCK <= 1 ; end process ;

wait f o r 10 ns ; wait f o r 10 ns ;

n e t n e t 0 <= not netB3 ; netR0 <= netA0 and netB0 ; n e t n e t 1 <= netA0 and netB1 ; n e t n e t 2 <= netA0 and netB2 ; n e t n e t 3 <= netA0 and netB3 ; SUB5 : entity S u b l o g i c z e r o port n e t n e t 5 <= netA1 and netB0 ; n e t n e t 6 <= netA1 and netB1 ; n e t n e t 7 <= netA1 and netB2 ; n e t n e t 8 <= netA1 and netB3 ; n e t n e t 9 <= netA2 and netB0 ; n e t n e t 1 0 <= netA2 and netB1 ; n e t n e t 1 1 <= netA2 and netB2 ; n e t n e t 1 2 <= netA2 and netB3 ; SUB4 : entity S u b f u l l a d d e r 4 b i t net net3 , net net4 , net net8 , net net4 ,

map ( n e t n e t 4 ) ;

port map ( n e t n e t 1 , n e t n e t 2 , net net5 , net net6 , net net7 , netR1 , n e t n e t 1 3 , n e t n e t 1 4 ,

net net15 , net net16 ) ; SUB6 : entity S u b f u l l a d d e r 4 b i t port map ( n e t n e t 1 3 , n e t n e t 1 4 , net net15 , net net16 , net net9 , net net10 , net net11 , n e t n e t 1 2 , n e t n e t 4 , netR2 , n e t n e t 1 7 , n e t n e t 1 8 , net net19 , net net20 ) ; n e t n e t 2 1 <= netA3 and netB0 ; n e t n e t 2 2 <= netA3 and netB1 ; n e t n e t 2 3 <= netA3 and netB2 ; n e t n e t 2 4 <= netA3 and netB3 ; SUB7 : entity S u b f u l l a d d e r 4 b i t port map ( n e t n e t 1 7 , n e t n e t 1 8 , net net19 , net net20 , net net21 , net net22 , n e t n e t 2 3 , n e t n e t 2 4 , n e t n e t 4 , netR3 , netR4 , netR5 , netR6 , netR7 ) ; end architecture ;
dtime clock.X a0.X a1.X a2.X a3.X b0.X b1.X b2.X b3.X r0.X r1.X r2.X r3.X r4.X r5.X r6.X r7.X 1.67u 1.68u 1.69u 1.7u 1.71u 1.72u 1.73u 1.74u 1.75u 1.76u 1.77u 1.78u 1.79u

Figure 21: A section of the 4 bit by 4 bit combinational digital multiplier TimeList output waveforms.

Update number two: September 2006

Update number two in this tutorial series reports on the major changes that have taken place to Qucs digital simulation since the rst update was posted on the Qucs 52

Web site roughly three months ago. During this period a number of signicant, and very critical, extensions have been implemented. Previous releases concentrated on establishing a fundamental base for digital circuit simulation using the VHDL language. The primary vehicle for representing circuit signals being the VHDL bit and bit-vector signal types. The next release of Qucs (version 0.0.10) and FreeHDL (version 0.0.3) extends the allowed signal types to include IEEE std_logic_1164 nine level logic, integers, and reals. Readers will appreciate that these changes are the result of a great deal of work by the Qucs team and must be considered as very much work in progress because not all the features oered by the FreeHDL implementation of the VHDL language are currently available via the Qucs schematic capture and VHDL text le simulation routes. Although a signicant amount of testing has taken place it is likely that software bugs will come to light as more Qucs users try the new features - if you nd a bug please report it by posting a note on the Qucs Web site. Adding new signal types to Qucs digital simulation aects all sections of the simulation route from schematic capture to plotting and tabulating input and output signals. Hence, although it may seem the wrong way round, the place to rst implement the necessary changes to accommodate the new signal types is at the simulation results reporting stages of the Qucs package. In release 0.0.10 no attempt has been made to add the new signal types to the schematic capture part of the Qucs package.21 Recent work on the digital sections of the Qucs package has concentrated on (1) improvements to VHDL language entry using the Qucs colour coded VHDL text editor22 , (2) modications to FreeHDL which allow a cleaner interface between Qucs and FreeHDL, (3) upgrades to the data conversion of simulation results from the FreeHDL value change dump format to the native Qucs format, and (4) major changes to the results reporting routines that are accessed from the Qucs diagrams icon dialogue. A detailed list of the software changes and bug xes can be found in the Qucs and FreeHDL change log les.

Simulating VHDL code using Qucs and FreeHDL.

The ow diagram drawn in Fig. 10 shows the relationship between Qucs and FreeHDL, and the sequence that takes place during digital circuit simulation. This ow diagram does not however, outline the details of the stages that are performed when converting (1) VHDL circuit code into a machine code simulation program, and (2) simulation output results into a format that can be plotted and tabulated by Qucs. These are illustrated in the ow diagram presented in Fig. 22. The shell script qucsdigi controls each of the stages in this sequence. A basic understanding
Adding new signal types to Qucs schematic capture is on the to-do list. A number of editor bugs have been xed and it is now possible for users to dene their own colour scheme for the various classes of VHDL reserved words and data types.
22 21

of the process employed by Qucs and FreeHDL is needed if users of the software are to be able to write meaningful VHDL code and simulate it using the two packages. VHDL code is either generated from a schematic diagram automatically by Qucs or entered using the Qucs VHDL text editor. The use of the schematic entry route was described in update one of these tutorial notes. However, a number of readers will probably have spotted that included in the VHDL code generated by Qucs are references to VHDL libraries. The VHDL language uses libraries to provide features that are not specied in the basic language denition but are commonly used by all language processing systems; two such libraries are STD and IEEE. When simulating digital circuits a basic knowledge of the structure of a simulation task and how these employ VHDL libraries is essential. This implies that users of the Qucs/FreeHDL software must appreciate how the system compiles and simulates a VHDL circuit simulation task. Once the VHDL simulation code has been entered via the VHDL text editor clicking the Qucs simulation button runs shell script qucsdigi performing the sequence shown in Fig. 2223 . Program freeehdl-v2cc converts VHDL code into C++ functions. These are then compiled along with a main C++ function. The next stage in the sequence links the compiled object code with the object code from any references to items in the predened VHDL libraries to produce an executable digital simulation program. This is then run by Qucs outputting a set of simulation results in value change dump (VCD) format24 . Finally a program called qucsconv converts the VCD simulation results into the Qucs native data format ready for post processing as graphical or tabular diagrams by Qucs.

For the FreeHDL package to operate correctly the directory where the software is installed must be included in the shell PATH from which Qucs is launched. 24 The value change dump language was originally designed as a simulation waveform interchange format for Verilog HDL. The specication of the VCD format can be found at http://wwwee.eng.hawaii.edu/ msmith/ASICs/HTML/Verilog/LRM/HTML/15/ch15.2.htm

VHDL source te%t file_name,"$!l file_name,"$! OR

Running C++ con"ersion,,,,

FreeHDL V&CC VHDL - C++ con"ersion file_name,cc

Compiling functions,,,

FreeHDL Compile C++ functions file_name,o

0
log,t%t log,t%t #RROR an! ot$er results !ata QUCS (imeList plot

Compiling main,,,

FreeHDL Compile C++ main function

Lin'ing,,,,
VHDL st! li)rar* stan!ar!,o +### li)rar* st!_logic_--./,o

file_name_main_,o

FreeHDL Lin'ing

file_name log,t%t

Simulating,,,,

RUN file_name simulation program

file_name,"c!

Running VCD con"ersion,,,

QUCSCONV VCD - QUCS !ata con"ersion

QUCS (rut$ ta)le QUCS (a)ulation

Figure 22: Detailed ow diagram showing VHDL code compilation and simulation results processing.

VHDL predened packages and libraries.

All VHDL language processing systems provide a predened VHDL package called standard. This package denes many of the fundamental VHDL data types, for example bit, character, integer and real. The predened types, subtypes and other functions in the package standard are stored in a library called STD. The FreeHDL version of library STD includes an additional VHDL package called textio which is used to input and output signal data from and to les. A second library called IEEE denes (1) multivalued logic signals dened by nine dierent encoding values, making it possible to model digital circuits that are composed from dierent technology components, (2) logic signal subtypes and (3) an extensive range of useful functions, procedures and overloaded operators. The FreeHDL version of the IEEE library consists of the following packages: 1. std_logic_1164 2. numeric_bit 3. math_real 4. numeric_std 5. std_logic_arith 6. std_logic_unsigned 7. vital_timing One other library is always dened by VHDL code processing systems namely the work library. This library holds user compiled VHDL entity/architecture design units.

VHDL simulation code structures.

In its most basic form VHDL circuit simulation code is structured as an entityarchitecture test bench which includes input signal test information.25 An example outline of the basic format is
entity t e s t b e n c h i s e n t i t y body s t a t e m e n t s end entity t e s t b e n c h ; architecture b e h a v i o u r a l of t e s t b e n c h i s a r c h i t e c t u r e body s t a t e m e n t s end architecture b e h a v i o u r a l ;
25

Test signals are often called test vectors.

VHDL data types, functions and operators in package standard are always visible to VHDL test bench code and reference to their use need not be added explicitly. However, if the test bench entity-architecture uses data types or other items dened in other libraries, for example the std_logic type in the IEEE library, then reference to them needs to be added before each entity-architecture pair where they are used. Libraries are referenced using the VHDL library and use statements. An example showing how these statements are employed is outlined in the following VHDL code segment:
library i e e e ; use i e e e . s t d l o g i c 1 1 6 4 . a l l ; entity t e s t b e n c h i s e n t i t y body s t a t e m e n t s end entity t e s t b e n c h ; architecture b e h a v i o u r a l of t e s t b e n c h i s a r c h i t e c t u r e body s t a t e m e n t s end architecture b e h a v i o u r a l ;

Here the VHDL code word all signies that all items in a specic library are to be made available for use in the following entity/architecture pair; testbench in the above example. If more than one library is to be used then a library/use statement is needed for each library reference. Most complete VHDL circuit simulation programs consist of more than one entity/architecture pair. In such cases the circuit test bench, with its signal test vectors, must be the last entry in the program. An example of a more complex VHDL program structure is
library i e e e ; use i e e e . s t d l o g i c 1 1 6 4 . a l l ; entity comp1 i s e n t i t y body s t a t e m e n t s end entity comp1 ; architecture b e h a v i o u r a l of comp1 i s a r c h i t e c t u r e body s t a t e m e n t s end architecture b e h a v i o u r a l ; library i e e e ; use i e e e . s t d l o g i c 1 1 6 4 . a l l ; entity comp2 i s e n t i t y body s t a t e m e n t s

end entity comp2 ; architecture b e h a v i o u r a l of comp2 i s a r c h i t e c t u r e body s t a t e m e n t s end architecture b e h a v i o u r a l ; library i e e e ; use i e e e . s t d l o g i c 1 1 6 4 . a l l ; use work . a l l ; entity t e s t b e n c h i s e n t i t y body s t a t e m e n t s end entity t e s t b e n c h ; architecture b e h a v i o u r a l of t e s t b e n c h i s a r c h i t e c t u r e body s t a t e m e n t s end architecture b e h a v i o u r a l ;

During the conversion of VHDL code to a machine code simulation program each entity/architecture pair, prior to the nal test bench entry, is compiled as a separate design unit and stored in the work library26 . Compiled design units held in the work library can be referenced in other entity/architecture models provided the VHDL statement use work.all; 27 is inserted in the VHDL simulation code prior to each entity/architecture statement where they are referenced.

The testbench entity/architecture pair is also, of course, compiled but this design unit is the one that is run as the executable simulation program. 27 References to individual items are also allowed by inserting, for example, use.work.comb1; use.work.comb2; in the VHDL code.

VHDL data types.

VHDL data types

Scalar

File

Access

Composite

Integer Real Enumerated Physical

Array Record

Figure 23: VHDL data types The chart shown in Fig. 23 indicates the dierent data types that are available in the VHDL language. FreeHDL implements all these data types. In practical circuit simulation the dierent VHDL data types are normally used to specify (1) signals, (2) variables and (3) constants28 . During simulation Qucs/FreeHDL automatically stores the values of integer, real and enumerated bit signals as simulation time progresses. Furthermore, bit_vector and IEEE signal types including std_logic_vector are also stored. Signals of these types are then available for plotting and tabulation using the Timing, Truth table, Tabular and Cartesian output diagrams. Selected elements in user dened composite signals, those that are stored in arrays for example29 , can be assigned to the basic signal types then displayed.30 . An example of how this is done is given in later sections of these update tutorial notes. Note - the values of variables and constants are not recorded during simulation.
Type le is of course dierent in that it is used to store either test vectors, component data such as ROM contents and output simulation results. 29 Please note that signal types based on the composite type record will probably cause the Qucs simulation cycle to fail - work on this data type has been added to the to-do list. 30 Qucs/FreeHDL also automatically collects waveform data for composite signals based on arrays of bit and IEEE signal types. However, in the case of large arrays care is needed when plotting or tabulating these directly because the entire contents of an array is output each time a signal is displayed.
28

An example VHDL simulation employing integer signals.

The following VHDL code demonstrates how the integer data type can be used to represent signals. In this example signals A, B change state on the rising edge of clock clk. The code tests the addition of integer signals and constants using arithmetic operators dened in library STD.31 The results from this simulation are shown in Fig. 24.
A v e r y b a s i c t e s t o f d a t a t y p e i n t e g e r . entity t e s t b e n c h i s end entity t e s t b e n c h ; architecture b e h a v i o u r a l of t e s t b e n c h i s s i g n a l A, B, C : i n t e g e r := 0 ; signal c l k : b i t ; begin p0 : process i s Generate c l o c k s i g n a l . begin c l k <= 0 ; wait f o r 10 ns ; c l k <= 1 ; wait f o r 10 ns ; end process p0 ; p1 : process ( c l k ) i s begin i f ( c l k e v e n t and c l k = 1 ) then A <= A + 1 ; B <= B + 2 ; end i f ; end process p1 ; C <= A + B ; end architecture b e h a v i o u r a l ;
dtime clk.X a.R b.R c.R 0 0 0 0 10n 1 2 3 20n 1 2 3 30n 2 4 6 40n 2 4 6 50n 3 6 9 60n 3 6 9 70n 4 8 12 80n 4 8 12 90n 5 10 15 100n

Figure 24: Output results for a simple test bench example employing integer signals.
The specication for the FreeHDL library STD can be found in text le freehdl0.0.3/std/standard.vhdl.
31

Multivalued logic.
Although signal types bit and bit-vector are widely employed when simulating digital systems one of their great weaknesses is the fact that it is dicult to represent signal bus systems simply using only logic 0 and logic 1 signal encoding. Moreover, circuits where bus signal contention occurs often result in simulation failure. The IEEE std_logic_1164 package overcomes this limitation through the introduction of a multivalued logic system which denes nine dierent logic values to represent signal types and signal strengths. Not only is the bus contention problem solved through logic resolving functions but the multivalued logic system allows devices constructed from dierent manufacturing technologies to be simulated at the same time, ensuring that the simulation process mirrors real circuit design practices. The next two simulation examples introduce the nine value logic system and demonstrate its use in the design of digital bus systems. Signals of type real are also introduced to show their representation by Qucs. Listed below is the VHDL code for a basic simulation which generates a set of IEEE std_logic, integer and real signals. Figure 25 illustrates how the Qucs Timing diagram displays dierent signal types. A section of tabulated results are also given in Fig. 26.
library i e e e ; use i e e e . s t d l o g i c 1 1 6 4 . a l l ; entity t e s t b e n c h i s end entity t e s t b e n c h ; architecture b e h a v i o u r a l of t e s t b e n c h i s signal c l k : b i t ; s i g n a l bv1 : b i t v e c t o r ( 8 downto 0 ) ; s i g n a l s t d l 1 : s t d l o g i c v e c t o r ( 8 downto 0 ) ; s i g n a l INT1 : i n t e g e r := 0 ; s i g n a l INT2 : i n t e g e r := 9 9 ; s i g n a l R1 : r e a l := 0 . 3 3 ; s i g n a l R2 : r e a l := 9 9 . 0 ; s i g n a l R3 : r e a l := 0 . 0 ; s i g n a l R4 : r e a l := 0 . 0 ; begin p0 : process i s begin c l k <= 0 ; wait f o r 10 ns ; c l k <= 1 ; wait f o r 10 ns ; end process p0 ;

p1 : process ( c l k ) i s variable v1 : i n t e g e r := 0 ; begin i f ( c l k e v e n t and c l k = 1 ) then v1 := v1 +1; case v1 i s when 1 => bv1 <= 000000000 ; when 2 => bv1 <= 000000001 ; when 3 => bv1 <= 000000011 ; when 4 => bv1 <= 000000111 ; when 5 => bv1 <= 000001111 ; when 6 => bv1 <= 000011111 ; when 7 => bv1 <= 000111111 ; when 8 => bv1 <= 001111111 ; when 9 => bv1 <= 111111111 ; when others => v1 := 0 ; end case ; end i f ; end process p1 ; p3 : process ( c l k ) i s begin i f ( c l k e v e n t and c l k = 1 ) then INT1 <= INT1 + 1 ; INT2 <= INT2 20; end i f ; i f ( INT1 >= 9 ) then INT1 <= 0 ; INT2 <= 9 9 ; end i f ; end process p3 ; p4 : process ( c l k ) i s Variable V2 : r e a l ; begin i f ( c l k e v e n t and c l k = 1 ) then R1 <= R1 + 1 . 0 ; R2 <= R2 20.0; R3 <= R1 R2 ; R4 <= R2/ (R1 + 0 . 0 0 0 1 ) ; end i f ; i f (R1 >= 2 0 . 0 ) then

stdl1 stdl1 stdl1 stdl1 stdl1 stdl1 stdl1 stdl1 stdl1

<= <= <= <= <= <= <= <= <=

000000000 ; 000000001 ; 00000001X ; 0000001XZ ; 000001XZU ; 00001XZUW ; 0001XZUWL ; 001XZUWLH ; 01XZUWLH ;

R1 <= 0 . 0 ; R2 <= 9 9 . 0 ; end i f ; end process p4 ; end architecture b e h a v i o u r a l ;

dtime clk.X r1.R r2.R r3.R r4.R stdl1.X int1.R int2.R bv1.X 0 0.33 99 0 0 XXXXXXXXX 0 99 000000000 10n 1.33 79 32.67 299.909 000000000 1 79 000000000 20n 1.33 79 32.67 299.909 000000000 1 79 000000000 30n 2.33 59 105.07 59.394 000000001 2 59 000000001 40n 2.33 59 105.07 59.394 000000001 2 59 000000001 50n 3.33 39 137.47 25.3208 00000001X 3 39 000000011 60n 3.33 39 137.47 25.3208 00000001X 3 39 000000011 70n 4.33 19 129.87 11.7114 0000001XZ 4 19 000000111

dtime clk.X r1.R r2.R r3.R r4.R stdl1.X int1.R int2.R bv1.X

70n 4.33 19 129.87 11.7114 0000001XZ 4 19 000000111

80n 4.33 19 129.87 11.7114 0000001XZ 4 19 000000111

90n 5.33 1 82.27 4.38789 000001XZX 5 1 000001111

100n 5.33 1 82.27 4.38789 000001XZX 5 1 000001111

110n 6.33 21 5.33 0.187614 00001XZX0 6 21 000011111

120n 6.33 21 5.33 0.187614 00001XZX0 6 21 000011111

130n 7.33 41 132.93 3.31748 0001XZX00 7 41 000111111

140n 7.33 41 132.93 3.31748 0001XZX00 7 41 000111111

Figure 25: Output results illustrating the TimeList representation of signals. The VCD waveform interchange standard encodes digital signals as four dierent logic levels. These are 0, 1, Z (high impedance) and X (unknown). Table 7 lists how the nine ieee.std_logic signal levels are represented using the VCD format. Until the VCD standard is revised the Qucs/FreeHDL package is restricted to displaying simulation output data using the basic 0, 1, Z and X signal encoding. The next example shows how the IEEE std_logic signal type can be used to simulate bus logic. The demonstration has been kept simple in order to keep the VHDL code short. The code fragment simulates two tri-state buers which 63

VHDL signal levels 0 Forcing logic 0 1 Forcing logic 1 X Forcing unknown Z High impedance U Uninitialised W Weak unknown L Weak logic 0 H Weak logic 1 - Dont care

VCD 0 1 X Z X 0 0 1 X

Table 7: IEEE multivalue logic and VCD representation. pass their outputs to bus drivers whos outputs connect on a common signal bus. The bus drivers ensure that the outputs from the tri-state buers are kept separate before combining onto the common bus line. This allows the output signals from the tri-state buers and the combined signal to be plotted separately. The resulting waveforms clearly show the std_logic resolution function in operation, see Fig. 27 . Note the eect of the 7 ns delay on the plotted waveforms and the use of the VHDL generic statement to set the invert device delay value.
Demonstration o f a s i m p l e bus s t r u c t u r e u s i n g t h e IEEE s t d l o g i c d a t a t y p e . library i e e e ; use i e e e . s t d l o g i c 1 1 6 4 . a l l ; entity buf i s generic ( d e l a y : time := 0 ns ) ; port ( in1 , c o n t r o l : in s t d l o g i c ; out1 : out s t d l o g i c ); end entity buf ; architecture b e h a v i o u r a l of buf i s begin p0 : process ( in1 , c o n t r o l ) i s begin i f ( c o n t r o l = 1 ) then out1 <= i n 1 a f t e r d e l a y ; e l s e out1 <= Z ; end i f ; end process p0 ; end architecture b e h a v i o u r a l ;

library i e e e ; use i e e e . s t d l o g i c 1 1 6 4 . a l l ; entity i n v e r t i s generic ( d e l a y : time := 0 ns ) ; port ( i n 1 : in s t d l o g i c ; out1 : out s t d l o g i c ); end entity i n v e r t ; architecture b e h a v i o u r a l of i n v e r t i s begin out1 <= not i n 1 a f t e r d e l a y ; end architecture b e h a v i o u r a l ; library i e e e ; use i e e e . s t d l o g i c 1 1 6 4 . a l l ; entity buf2 i s port ( i n 1 : in s t d l o g i c ; out1 : out s t d l o g i c ); end entity buf2 ; architecture d a t a f l o w of buf2 i s begin out1 <= i n 1 ; end architecture d a t a f l o w ; library i e e e ; use i e e e . s t d l o g i c 1 1 6 4 . a l l ; use work . a l l ; entity t e s t b e n c h i s end entity t e s t b e n c h ; architecture s t r u c t u r a l of t e s t b e n c h i s signal data in 1 , data in 2 : s t d l o g i c ; signal data out 1 , data out 2 : s t d l o g i c ; signal data control , control buf1 : std logic ;

signal r e s u l t : s t d l o g i c ; begin p0 : process i s begin d a t a i n 1 <= 0 ; wait f o r 5 ns ; d a t a i n 1 <= 1 ; wait f o r 5 ns ; end process p0 ; d a t a i n 2 <= not d a t a i n 1 ; p1 : process i s begin d a t a c o n t r o l <= 1 ; wait f o r 40 ns ; d a t a c o n t r o l <= 0 ; wait f o r 40 ns ; end process p1 ; c1g1 : entity buf port map( i n 1 => d a t a i n 1 , c o n t r o l => d a t a c o n t r o l , out1 => d a t a o u t 1 ) ; c1g2 : entity i n v e r t generic map ( d e l a y => 7 ns ) port map( i n 1 => d a t a c o n t r o l , out1 => c o n t r o l b u f 1 ) ; c1g3 : entity buf port map( i n 1 => d a t a i n 2 , c o n t r o l => c o n t r o l b u f 1 , out1 => d a t a o u t 2 ) ; c1g4 : entity buf2 port map( i n 1 => d a t a o u t 1 , out1 => r e s u l t ) ; c1g5 : entity buf2 port map( i n 1 => d a t a o u t 2 , out1 => r e s u l t ) ; end architecture s t r u c t u r a l ;

dtime 0 1e-8 2e-8 3e-8 4e-8 5e-8 6e-8 7e-8 8e-8 9e-8 1e-7 1.1e-7 1.2e-7 1.3e-7 1.4e-7 1.5e-7 1.6e-7 1.7e-7 1.8e-7 1.9e-7

clk.X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

int1.R 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 0 1

int2.R 99 79 79 59 59 39 39 19 19 -1 -1 -21 -21 -41 -41 -61 -61 -81 99 79

r1.R 0.33 1.33 1.33 2.33 2.33 3.33 3.33 4.33 4.33 5.33 5.33 6.33 6.33 7.33 7.33 8.33 8.33 9.33 9.33 10.3

r2.R 99 79 79 59 59 39 39 19 19 -1 -1 -21 -21 -41 -41 -61 -61 -81 -81 -101

r3.R 0 32.7 32.7 105 105 137 137 130 130 82.3 82.3 -5.33 -5.33 -133 -133 -301 -301 -508 -508 -756

r4.R 0 300 300 59.4 59.4 25.3 25.3 11.7 11.7 4.39 4.39 -0.188 -0.188 -3.32 -3.32 -5.59 -5.59 -7.32 -7.32 -8.68

bv1.X 000000000 000000000 000000000 000000001 000000001 000000011 000000011 000000111 000000111 000001111 000001111 000011111 000011111 000111111 000111111 001111111 001111111 111111111 111111111 111111111

00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100

clk.X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

int1.R 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 0 1 1

int2.R 99 79 79 59 59 39 39 19 19 1 1 21 21 41 41 61 61 81 99 79 79

r1.R 0.33 1.33 1.33 2.33 2.33 3.33 3.33 4.33 4.33 5.33 5.33 6.33 6.33 7.33 7.33 8.33 8.33 9.33 9.33 10.33 10.33

r2.R 99 79 79 59 59 39 39 19 19 1 1 21 21 41 41 61 61 81 81 101 101

r3.R 0 32.67 32.67 105.07 105.07 137.47 137.47 129.87 129.87 82.27 82.27 5.33 5.33 132.93 132.93 300.53 300.53 508.13 508.13 755.73 755.73

r4.R 0 299.909 299.909 59.394 59.394 25.3208 25.3208 11.7114 11.7114 4.38789 4.38789 0.187614 0.187614 3.31748 3.31748 5.59338 5.59338 7.32284 7.32284 8.68158 8.68158

bv1.X 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 001 001 111 111 111 111

0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

stdl1.X XXXXXXXXX 000000000 000000000 000000001 000000001 00000001X 00000001X 0 0 0 0 0 0 1 XZ 0 0 0 0 0 0 1 XZ 0 0 0 0 0 1 XZX 0 0 0 0 0 1 XZX 0 0 0 0 1 XZX0 0 0 0 0 1 XZX0 0 0 0 1 XZ X0 0 0 0 0 1 XZ X0 0 0 0 1 XZX0 0 1 0 0 1 XZX0 0 1 0 1 XZ X0 0 1 X 0 1 XZ X0 0 1 X 0 1 XZ X0 0 1 X 0 1 XZ X0 0 1 X

Figure 26: Output results illustrating tabular representation of signals.

dtime data_in_1.X data_in_2.X data_out_1.X data_out_2.X data_control.X control_buf1.X result.X

10n

15n

20n

25n

30n

35n

40n

45n

47n

50n

55n

60n

65n

70n

75n

80n

Z X

Z Z

dtime data_in_1.X data_in_2.X data_out_1.X data_out_2.X data_control.X control_buf1.X result.X

80n

85n

87n

90n

95n

100n

105n

110n

115n

120n

125n

127n

130n

135n

140n

145n

150n

155n

Z Z

Figure 27: Signal waveforms for the simple bus example.

Run debugging of VHDL simulation code.

The VHDL language has a number of built in features that allow the debugging of VHDL code at simulation time. In this section the VHDL reserved words assert, report and severity are introduced and their use as code debugging aids explained by way of a more detailed design example. In the previous digital tutorial update a structural design of a 4 bit digital multiplier was introduced as an example that employed the Qucs schematic capture digital simulation route. The next example extends the previous multiplier design to 16 bits. However, at a structural level the larger multiplier becomes very detailed and its design can be prone to error. To demonstrate the power of VHDL the 16 bit multiplier has been redesigned at a functional level. A block diagram of the multiplier simulation test bench is given in Fig. 28: rstly a clock strobes a data generator unit which generates a sequence of integer numbers. These are converted to 16 bit_vectors and applied to the 16 bit multiplier unit as inputs x and y; secondly the 16-bit multiplier on sensing a change in inputs x or y converts these signals from 16 bit_vectors to integers, multiples them and nally converts the integer result to 32 bit_vector output Res_bit. Although standard library STD denes arithmetic operations for integers it does not provide functions for the conversion of integers to bit_vectors or the reverse operation. The following VHDL listing gives the complete simulation test bench 68

program for the 16 bit multiplier including the required data conversion functions. VHDL debug or message reporting code using the reserved words assert, report and severity have been added to the data_generator and functional_multiplier architecture code. During simulation these text strings, and the simulation time when they were actioned, are written to the Qucs log.txt le, giving a trace record of the simulation activity. In cases where an error occurs at severity level failure the simulation will terminate. FreeHDL allows VHDL report statements without an accompanying assert statement.32 A typical Timing diagram plot for this design is shown in Fig. 29

X
Data generator 16 16

16 bit functional multiplier

Res_bit
32

CLK
CLOCK X= Y= bit_!ector"1# $o%nto &' bit_!ector"1# $o%nto &' bit_!ector"31 $o%nto &'

Res_bit =

Figure 28: Block diagram of a 16 bit functional multiplier.

16 b i t d i g i t a l m u l t i p l i e r example . S i m u l a t i o n t r a c e u s i n g a s s e r t , r e p o r t and s e v e r i t y s t a t e m e n t s . entity c l o c k i s port ( c l k : out b i t ) ; end entity c l o c k ; architecture b e h a v i o u r a l of c l o c k i s begin p0 : process i s
One of the changes at the 1993 revision of the IEEE VHDL 1076-1987 standard was to allow report statements without the previous mandatory assert clause. FreeHDL attempts to comply with the 1993 revision.
32

begin c l k <= 0 ; wait f o r 10 ns ; c l k <= 1 ; wait f o r 10 ns ; end process p0 ; end architecture b e h a v i o u r a l ; entity d a t a g e n e r a t o r i s port ( c l k : in b i t ; x , y : out b i t v e c t o r ( 1 5 downto 0 ) ); end entity d a t a g e n e r a t o r ; architecture b e h a v i o u r a l of d a t a g e n e r a t o r i s type mem array 16 i s array ( 1 to 8 ) of i n t e g e r ; s i g n a l count : i n t e g e r := 0 ; function i n t e g e r t o v e c t o r 1 6 ( i n t n o : i n t e g e r ) return b i t v e c t o r is variable n i : i n t e g e r ; variable r e t u r n v a l u e : b i t v e c t o r ( 1 5 downto 0 ) ; begin assert ( n i < 0 ) report Function i n t e g e r t o v e c t o r 3 2 : i n t e g e r number must be >= 0 severity f a i l u r e ; n i := i n t n o ; for i in r e t u r n v a l u e Reverse Range loop i f ( ( n i mod 2 ) =1 ) then r e t u r n v a l u e ( i ) := 1 ; e l s e r e t u r n v a l u e ( i ) := 0 ; end i f ; n i := n i / 2 ; end loop ; return r e t u r n v a l u e ; end i n t e g e r t o v e c t o r 1 6 ; begin p1 : process ( c l k ) i s variable x i : mem array 16 := ( 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 ) ; variable y i : mem array 16 := ( 2 , 4 , 6 , 8 , 1 0 , 1 2 , 1 4 , 1 6 ) ; variable xh , yh : i n t e g e r ; variable c o u n t i : i n t e g e r ; begin c o u n t i := count +1;

i f ( c o u n t i > 8 ) then c o u n t i := 1 ; end i f ; xh := x i ( c o u n t i ) ; yh := y i ( c o u n t i ) ; x <= i n t e g e r t o v e c t o r 1 6 ( xh ) ; y <= i n t e g e r t o v e c t o r 1 6 ( yh ) ; count <= c o u n t i ; report In p r o c e s s p1 . d a t a g e n e r a t o r . ; end process p1 ; end architecture b e h a v i o u r a l ; entity f u n c t i o n a l m u l t i p l i e r i s port ( x , y : in b i t v e c t o r ( 1 5 downto 0 ) ; r e s b i t : out b i t v e c t o r ( 3 1 downto 0 ) ); end entity f u n c t i o n a l m u l t i p l i e r ; architecture b e h a v i o u r a l of f u n c t i o n a l m u l t i p l i e r i s function v e c t o r t o i n t e g e r ( v1 : b i t v e c t o r ) return i n t e g e r i s variable r e t u r n v a l u e : i n t e g e r : = 0 ; a l i a s v2 : b i t v e c t o r ( v1 l e n g t h 1 downto 0 ) i s v1 ; begin for i in v2 h i g h downto 1 loop i f ( v2 ( i ) = 1 ) then r e t u r n v a l u e := ( r e t u r n v a l u e +1) 2; else r e t u r n v a l u e := r e t u r n v a l u e 2 ; end i f ; end loop ; i f v2 ( 0 ) = 1 then r e t u r n v a l u e := r e t u r n v a l u e +1; end i f ; return r e t u r n v a l u e ; end v e c t o r t o i n t e g e r ; function i n t e g e r t o v e c t o r 3 2 ( i n t n o : i n t e g e r ) return b i t v e c t o r is variable n i : i n t e g e r ; variable v a l u e : b i t v e c t o r ( 3 1 downto 0 ) ; begin

assert ( n i < 0 ) report Function i n t e g e r t o v e c t o r 3 2 : i n t e g e r number must be >= 0 severity f a i l u r e ; n i := i n t n o ; for i in 0 to 31 loop i f ( ( n i mod 2 ) =1 ) then v a l u e ( i ) := 1 ; e l s e v a l u e ( i ) := 0 ; end i f ; i f n i > 0 then n i := n i / 2 ; e l s e n i := ( ni 1)/2; end i f ; end loop ; return v a l u e ; end i n t e g e r t o v e c t o r 3 2 ; begin p0 : process ( x , y ) i s variable xi , yi , prod mult : i n t e g e r ; begin x i := v e c t o r t o i n t e g e r ( x ) ; y i := v e c t o r t o i n t e g e r ( y ) ; prod mult := x i y i ; r e s b i t <= i n t e g e r t o v e c t o r 3 2 ( prod mult ) ; report In p r o c e s s p1 . f u n c t i o n a l m u l t i p l i e r ; end process p0 ; end architecture b e h a v i o u r a l ; entity t e s t 2 v h d l 1 i s end entity t e s t 2 v h d l 1 ; architecture b e h a v i o u r a l of t e s t 2 v h d l 1 i s signal c l k : b i t ; s i g n a l x , y : b i t v e c t o r ( 1 5 downto 0 ) ; s i g n a l r e s b i t : b i t v e c t o r ( 3 1 downto 0 ) ; begin d1 : entity work . c l o c k port map ( c l k ) ; d2 : entity work . d a t a g e n e r a t o r port map( c l k , x , y ) ; d3 : entity work . f u n c t i o n a l m u l t i p l i e r port map ( x , y , r e s b i t ) ; end architecture b e h a v i o u r a l ;

dtime clk.X res_bit.X x.X y.X

10n 00000000000000000000000000001000 0000000000000010 0000000000000100

20n 00000000000000000000000000010010 0000000000000011 0000000000000110

30n

dtime clk.X res_bit.X x.X y.X

20n 00000000000000000000000000010010 0000000000000011 0000000000000110

30n 00000000000000000000000000100000 0000000000000100 0000000000001000

40n

dtime clk.X res_bit.X x.X y.X

40n 00000000000000000000000000110010 0000000000000101 0000000000001010

50n 00000000000000000000000001001000 0000000000000110 0000000000001100

60n

dtime clk.X res_bit.X x.X y.X

60n 00000000000000000000000001100010 0000000000000111 0000000000001110

70n 00000000000000000000000010000000 0000000000001000 0000000000010000

80n

Figure 29: Typical timing diagram for the 16 bit functional multiplier. More advanced output debug messages, and results tables, can be written to Qucs message le log.txt by using the predened data handling routines in STD library package textio33 . This package contains functions for reading and writing STD data types from and to les34 . The next segment of VHDL code illustrates how a simple table of results can be written to le log.txt. The results table is shown in Table 8.
Test t e x t i o p a c k a g e . l i b r a r y STD ; use STD . t e x t i o . a l l ; entity Q u c s w r i t e t e s t i s
The specication for the FreeHDL package textio can be found in text le freehdl0.0.3/std/textio.vhdl. 34 VHDL allows data to be read from and written to the standard input and output streams as well as user dened les. At this time only writing data to le log.txt and reading data from user dened data les has been tested. Please note that the use of the textio package is very much a cutting edge feature of the Qucs/FreeHDL software and is probably not bug free.
33

end entity Q u c s w r i t e t e s t ; architecture b e h a v i o u r a l of Q u c s w r i t e t e s t i s begin w r i t e t e s t : process i s variable i n p u t l i n e , o u t p u t l i n e : l i n e ; variable i n t 1 : i n t e g e r := 1 0 ; begin write ( output line , string ( ) ) ; w r i t e l i n e ( output , o u t p u t l i n e ) ; w r i t e ( o u t p u t l i n e , s t r i n g ( S t r i n g > l o g . t x t ) ) ; w r i t e l i n e ( output , o u t p u t l i n e ) ; test L1 : f o r i c in 1 to 5 loop i n t 1 := i n t 1 + 1 ; write ( output line , string ( int1 = ) ); write ( output line , int1 ) ; write ( output line , string ( i n t 1 2 = ) ); write ( output line , int1 int1 ) ; w r i t e l i n e ( output , o u t p u t l i n e ) ; end loop t e s t L 1 ; report F i n i s h e d t e s t f o r l o o p . ; end process w r i t e t e s t ; end architecture b e h a v i o u r a l ;

Output: ---------Starting new simulation on Thu 24. Aug 2006 at 13:10:56 running C++ conversion... done. compiling functions... done. compiling main... done. linking... done. simulating... Output to STD output -> log.txt int1 = 11 int1^2 = 121 int1 = 12 int1^2 = 144 int1 = 13 int1^2 = 169 int1 = 14 int1^2 = 196 int1 = 15 int1^2 = 225 0 fs + 0d: NOTE: Finished test for loop. running VCD conversion... done. Simulation ended on Thu 24. Aug 2006 at 13:10:57 Ready. Errors: -------Table 8: Log.txt le showing tabular output results.

Testing digital systems using test vectors stored on disk.

In an attempt on my part to review all the new features introduced in the previous sections of this update the nal example demonstrates how test vectors stored on disk, as a text le, can be read by the simulation program at the start of a simulation, then applied to the inputs of the digital system under test. The code for this example is given in the following listing:
T e s t i n g d i g i t a l c i r c u i t s u s i n g t e s t v e c t o r s s t o r e d as a t e x t f i l e on d i s k . entity comb1 i s port ( a , b , c , d : in b i t ; y : out b i t ); end entity comb1 ; architecture d a t a f l o w of comb1 i s begin y <= ( a nand b ) or ( c and d ) ; end architecture d a t a f l o w ; l i b r a r y STD ; use STD . t e x t i o . a l l ; entity t e s t b e n c h i s end entity t e s t b e n c h ; architecture b e h a v i o u r a l of t e s t b e n c h i s signal clock : b i t ; s i g n a l v1 , v2 , v3 , v4 , y o u t : b i t ; type a r r a y l i s t i s array ( 1 to 2 0 ) of b i t ; s i g n a l v1sd , v2sd , v3sd , v4sd : a r r a y l i s t ; Procedure s t o r e d a t a ( variable number : out i n t e g e r ) i s variable d1 , d2 , d3 , d4 : b i t ; variable i n l i n e , o u t l i n e : l i n e ; variable i : integer ; variable m y s t r i n g : s t r i n g ( 1 to 2 0 ) := c r & C o n s t r a i n e d s t r i n g & c r ; f i l e i n f i l e : t e x t open read mode i s /mnt/ hda2 / qucs 0 . 0 . 1 0 f / t e s t 1 d a t a ; begin report m y s t r i n g ; i := 1 ; while not ( e n d f i l e ( i n f i l e ) ) loop

readline ( infile , in line ); r e a d ( i n l i n e , d4 ) ; r e a d ( i n l i n e , d3 ) ; r e a d ( i n l i n e , d2 ) ; r e a d ( i n l i n e , d1 ) ; v1sd ( i ) <= d1 ; v2sd ( i ) <= d2 ; v3sd ( i ) <= d3 ; v4sd ( i ) <= d4 ; report In f i l e r e a d l o o p . ; i := i +1; i f ( i > 2 0 ) then e x it ; end i f ; number:= i ; end loop ; end procedure s t o r e d a t a ; begin p0 : process i s Generate a c l o c k s i g n a l . begin c l o c k <= 1 ; wait f o r 10 ns ; c l o c k <= 0 ; wait f o r 10 ns ; end process p0 ; g0 : entity work . comb1 port map ( v1 , v2 , v3 , v4 , y o u t ) ; p1 : process i s Read t e s t v e c t o r s from d i s k and apply data to c i r c u i t inputs . variable n o r e a d s : i n t e g e r ; variable i n l i n e , o u t l i n e : l i n e ; begin store data ( no reads ) ; w r i t e ( o u t l i n e , s t r i n g ( count = ) ) ; w r i t e ( o u t l i n e , n o r e a d s 1); w r i t e l i n e ( output , o u t l i n e ) ; f o r k in 1 to n o r e a d s 1 loop Count up . wait u n t i l ( c l o c k e v e n t and c l o c k = 1 ) ; v1 <= v1sd ( k ) ; v2 <= v2sd ( k ) ; v3 <= v3sd ( k ) ; v4 <= v4sd ( k ) ; w r i t e ( o u t l i n e , s t r i n g ( Time = ) , l e f t , 8 ) ;

w r i t e ( o u t l i n e , now , r i g h t , 1 0 ) ; w r i t e ( o u t l i n e , s t r i n g ( Test v e c t o r s > ) , r i g h t , 20 ) ; w r i t e ( o u t l i n e , v4 , l e f t , 2 ) ; w r i t e ( o u t l i n e , v3 , l e f t , 2 ) ; w r i t e ( o u t l i n e , v2 , l e f t , 2 ) ; w r i t e ( o u t l i n e , v1 , l e f t , 2 ) ; w r i t e ( o u t l i n e , s t r i n g ( k = ) , r i g h t , 10 ) ; write ( out line , k ) ; w r i t e l i n e ( output , o u t l i n e ) ; wait u n t i l ( c l o c k e v e n t and c l o c k = 0 ) ; end loop ; f o r k in n o r e a d s 1 downto 1 loop Count down . wait u n t i l ( c l o c k e v e n t and c l o c k = 1 ) ; v1 <= v1sd ( k ) ; v2 <= v2sd ( k ) ; v3 <= v3sd ( k ) ; v4 <= v4sd ( k ) ; w r i t e ( o u t l i n e , s t r i n g ( Time = ) , l e f t , 8 ) ; w r i t e ( o u t l i n e , now , r i g h t , 1 0 ) ; w r i t e ( o u t l i n e , s t r i n g ( Test v e c t o r s > ) , r i g h t , 20 ) ; w r i t e ( o u t l i n e , v4 , l e f t , 2 ) ; w r i t e ( o u t l i n e , v3 , l e f t , 2 ) ; w r i t e ( o u t l i n e , v2 , l e f t , 2 ) ; w r i t e ( o u t l i n e , v1 , l e f t , 2 ) ; w r i t e ( o u t l i n e , s t r i n g ( k = ) , r i g h t , 10 ) ; write ( out line , k ) ; w r i t e l i n e ( output , o u t l i n e ) ; wait u n t i l ( c l o c k e v e n t and c l o c k = 0 ) ; end loop ; wait ; end process p1 ; end architecture b e h a v i o u r a l ;

Although the listing above is relatively short, careful study of its contents should allow readers to identify many of the new Qucs/FreeHDL features introduced earlier. Moreover in some sections, the code illustrates extra features which will be familiar to those Qucs/FreeHDL users who have a more advanced knowledge of the VHDL language. These are listed below with a number of general points: The VHDL code simulates the performance of a simple combinational logic circuit called comb1: this has four inputs (a, b, c, d) of type bit and one output (y) of type bit35 .
35

Type bit was chosen for this example rather than one of the IEEE signal types because

The testbench being simulated consists of two processes: process p0 generates a clock signal with a period of 20 ns; process p1 inputs test data held in le test1_data 36 and stores it in four signal arrays (v1sd, v2sd, v3sd and v4sd), applying this data to the inputs of the circuit under test at the leading edges of the clock pulse. Note process p1 only executes once due to the wait statement at its end. An instantiation of the comb1 component is included in the testbench architecture. Note the use of the VHDL entity work.comb1 construction, this is an alternative for use work.all ; The test vector data held in le test_data is read by procedure store_data which returns the number of lines of data read in variable number. File handling, including reading data from disk, is undertaken with predened routines in package textio. The rst report statement in procedure store_data writes string my_string to le log.txt. My_string is an example of the VHDL constrained string type, consisting of non-printable control characters37 concatenated with printable characters. Two loops are employed in process p1 to apply signal test vectors to the input of comb1: the rst loop counts up from one and the second loop counts down from the number of lines of test vectors read by procedure store_data, eectively generating test vectors in a way similar to using an up-down pattern generator counter. Note that the signal data is applied to the circuit under test on the rising edge of the clock signal and that the applied signal vector sequence is really up to the imagination of the VHDL programmer. The write statements in the process p1 for loops demonstrate the formatted version of the textio write statement. This greatly assists in setting up tables of results. Table 9 gives a typical log.txt content for the comb1 test simulation. In process p1 signals v1, v2, v3 and v4 are assigned an indexed value from (type array_list) v1sd, v2sd, v3sd and v4sd signals. During simulation
package textio does not handle the IEEE multivalue logic types. 36 I use the Knoppix version of the Linux/GNU operating system for all work on the Qucs project. The absolute location of the test data le will depend on where Qucs and FreeHDL have been installed and the location where work les are kept. 37 Type character in package standard lists the two letter codes used by VHDL to represent non-printable control characters.

Qucs/FreeHDL stores signal values as a simulation progresses. Hence, it is theoretically possible to display both the standard and composite signal types. A typical waveform plot for signals v1, v2, v3, v4 and y_out is given in Fig. 30. Fig. 31 illustrates a waveform plot of the composite signals v1sd, v2sd, v3sd and v4sd. In Fig. 31 each group is plotted at a clock edge change yielding identical groups of values; each vertical set of bits represents the bit values for a single line in le test1_data. Compare the displayed values in Fig. 31 with the contents of the test1_data le shown in Fig. 32. As mentioned before some care is needed when plotting, or tabulating, composite signals, particularly when the array sizes are large; array dimensions above roughly 50 become dicult to plot on a normal resolution screen. In such cases it is better to slice part of an array and assign the required values to a signal that can be easily displayed.

dtime v1.X v2.X v3.X v4.X y_out.X

10n

20n

30n

40n

50n

60n

70n

80n

90n

100n

110n

120n

130n

140n

150n

160n

170n

180n

dtime v1.X v2.X v3.X v4.X y_out.X

180n

190n

200n

210n

220n

230n

240n

250n

260n

270n

280n

290n

300n

310n

320n

330n

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360n

dtime v1.X v2.X v3.X v4.X y_out.X

220n

230n

240n

250n

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290n

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320n

330n

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dtime v1.X v2.X v3.X v4.X y_out.X

400n

410n

420n

430n

440n

450n

460n

470n

480n

490n

500n

510n

520n

530n

540n

550n

560n

570n

580n

Figure 30: Typical timing diagram for comb1 simulation.

Output : S t a r t i n g new s i m u l a t i o n on F r i 25 . Aug 2006 a t 14 : 35 : 48 r u n ni n g C++ c o n v e r s i o n . . . done . c o m p i l i n g f u n c t i o n s . . . done . c o m p i l i n g main . . . done . l i n k i n g . . . done . simulating . . . 0 f s + 0d : NOTE : Constrained s t r i n g 0 f s + 0d : NOTE : In f i l e r e a d l o o p . . 0 f s + 0d : NOTE : In f i l e r e a d l o o p . count = 16 Time = 0 ns Test v e c t o r s > 0 0 0 0 k = 1 Time = 20 ns Test v e c t o r s > 0 0 0 0 k = 2 Time = 40 ns Test v e c t o r s > 0 0 0 1 k = 3 Time = 60 ns Test v e c t o r s > 0 0 1 0 k = 4 . Time = 200 ns Test v e c t o r s > 1 0 0 1 k = 11 Time = 220 ns Test v e c t o r s > 1 0 1 0 k = 12 Time = 240 ns Test v e c t o r s > 1 0 1 1 k = 13 Time = 260 ns Test v e c t o r s > 1 1 0 0 k = 14 Time = 280 ns Test v e c t o r s > 1 1 0 1 k = 15 Time = 300 ns Test v e c t o r s > 1 1 1 0 k = 16 Time = 320 ns Test v e c t o r s > 1 1 1 1 k = 16 Time = 340 ns Test v e c t o r s > 1 1 1 1 k = 15 Time = 360 ns Test v e c t o r s > 1 1 1 0 k = 14 Time = 380 ns Test v e c t o r s > 1 1 0 1 k = 13 Time = 400 ns Test v e c t o r s > 1 1 0 0 k = 12 . Time = 560 ns Test v e c t o r s > 0 1 0 0 k = 4 Time = 580 ns Test v e c t o r s > 0 0 1 1 k = 3 r u n ni n g VCD c o n v e r s i o n . . . done . S i m u l a t i o n ended on F r i 25 . Aug 2006 a t 14 : 35 : 50 Ready . Errors :

Table 9: An edited version of the formatted tabular output results written to le log.txt.

dtime v1sd.X v2sd.X v3sd.X v4sd.X

40n 01010101010101010000 00110011001100110000 00001111000011110000 00000000111111110000

50n 01010101010101010000 00110011001100110000 00001111000011110000 00000000111111110000

60n 01010101010101010000 00110011001100110000 00001111000011110000 00000000111111110000

70n 01010101010101010000 00110011001100110000 00001111000011110000 00000000111111110000

80n

Figure 31: Typical timing diagram for composite signals v1sd, v2sd, v3sd and v4sd.

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Figure 32: Comb1 simulation test vectors.

End note
Qucs 0.0.8 added digital simulation to the impressive list of features already available in the Qucs package. The 0.0.8 release represented a signicant step forward in the development of the Qucs project. The fact that there were bugs in the rst version of the digital simulator was not surprising given the complexity of the software. Release 0.0.9 goes a long way to correcting the most annoying of these bugs. It also adds a number of new features, the most notable being the new VHDL editor and the automatic generation of component symbols from hand crafted VHDL 82

model code. Qucs 0.0.10 and FreeHDL 0.0.3 adds a range of new features to the software, particularly important are the use of the IEEE std_logic_1164 package and the le handling routines found in the textio package. My thanks to Michael Margraf and Stefan Jahn for all their encouragement during the period that I have been testing the Qucs VHDL digital simulation and the subsequent writing of these notes.

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