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Lecture35&36 - Delay in Multilevel Logic: Jagannadha Naidu K

This document discusses multistage logic networks and delay. It introduces logical effort, which generalizes effort calculations to multistage networks by accounting for path logical effort, electrical effort, and branching effort. It shows that path delay equals the sum of effort delay and parasitic delay. Optimal delay is achieved when each stage bears equal effort of approximately 4. While minimizing stages does not always minimize delay, best delay occurs around 4 stages. Logical effort provides a method to estimate delays and determine gate sizes without simulation.

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39 views

Lecture35&36 - Delay in Multilevel Logic: Jagannadha Naidu K

This document discusses multistage logic networks and delay. It introduces logical effort, which generalizes effort calculations to multistage networks by accounting for path logical effort, electrical effort, and branching effort. It shows that path delay equals the sum of effort delay and parasitic delay. Optimal delay is achieved when each stage bears equal effort of approximately 4. While minimizing stages does not always minimize delay, best delay occurs around 4 stages. Logical effort provides a method to estimate delays and determine gate sizes without simulation.

Uploaded by

sophieee19
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Lecture35&36 Delay in Multilevel

Logic
Jagannadha Naidu K
Ref: Weste, CMOS VLSI Design,3
rd
edition,2006
Multistage Logic Networks
Logical effort generalizes to multistage
networks
Path Logical Effort
Path Electrical Effort
Path Effort
i
G g =

out-path
in-path
C
H
C
=
i i i
F f g h = =

10
x
y
z
20
g
1
= 1
h
1
= x/10
g
2
= 5/3
h
2
= y/x
g
3
= 4/3
h
3
= z/y
g
4
= 1
h
4
= 20/z
Multistage Logic Networks
Logical effort generalizes to multistage networks
Path Logical Effort
Path Electrical Effort
Path Effort
Can we write F = GH?
i
G g =

out path
in path
C
H
C

=
i i i
F f g h = =

Paths that Branch
No! Consider paths that branch:
G = 1
H = 90 / 5 = 18
GH = 18
h
1
= (15 +15) / 5 = 6
h
2
= 90 / 15 = 6
F = g
1
g
2
h
1
h
2
= 36 = 2GH
5
15
15
90
90
Branching Effort
Introduce branching effort
Accounts for branching between stages in path
Now we compute the path effort
F = GBH
on path off path
on path
C C
b
C
+
=
i
B b =

i
h BH =

Note:
Multistage Delays
Path Effort Delay
Path Parasitic Delay
Path Delay
F i
D f =

i
P p =

i F
D d D P = = +

Designing Fast Circuits


Delay is smallest when each stage bears same effort
Thus minimum delay of N stage path is
This is a key result of logical effort
Find fastest possible delay
Doesnt require calculating gate sizes
i F
D d D P = = +

1
N
i i
f g h F = =
1
N
D NF P = +
Gate Sizes
How wide should the gates be for least delay?
Working backward, apply capacitance
transformation to find input capacitance of each gate
given load it drives.
Check work by verifying input cap spec is met.

out
in
i
i
C
C
i out
in
f gh g
g C
C
f
= =
=
Example: 3-stage path
Select gate sizes x and y for least delay from
A to B
8
x
x
x
y
y
45
45
A
B
Example: 3-stage path
Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27
Electrical Effort H = 45/8
Branching Effort B = 3 * 2 = 6
Path Effort F = GBH = 125
Best Stage Effort
Parasitic Delay P = 2 + 3 + 2 = 7
Delay D = 3*5 + 7 = 22 = 4.4 FO4
8
x
x
x
y
y
45
45
A
B
3

5 f F = =
Example: 3-stage path
Work backward for
sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 =
10
P: 4
N: 4
45
45
A
B
P: 4
N: 6
P: 12
N: 3
Best Number of Stages
How many stages should a path use?
Minimizing number of stages is not always fastest
Example: drive 64-bit datapath with unit inverter
D = NF
1/N
+ P
= N(64)
1/N
+ N
1 1 1 1
8 4
16 8
2.8
23
64 64 64 64
Initial Driver
Datapath Load
N:
f:
D:
1
64
65
2
8
18
3
4
15
4
2.8
15.3
Fastest
Derivation
Consider adding inverters to end of path
How many give least delay?
Define best stage effort
N - n
1
Extra Inverters
Logic Block:
n
1
Stages
Path Eff ort F
( )
1
1
1
1
N
n
i inv
i
D NF p N n p
=
= + +

1 1 1
ln 0
N N N
inv
D
F F F p
N

= + + =

( )
1 ln 0
inv
p + =
1
N
F =
Best Stage Effort
has no closed-form
solution
Neglecting parasitics (p
inv
= 0), we find =
2.718 (e)
For p
inv
= 1, solve numerically for = 3.59
( )
1 ln 0
inv
p + =
Sensitivity Analysis
How sensitive is delay to using exactly the best
number of stages?
2.4 < < 6 gives delay within 15% of optimal
We can be sloppy!
I like = 4
1.0
1.2
1.4
1.6
1.0 2.0 0.5 1.4 0.7
N / N
1.15
1.26
1.51
( =2.4) (=6)
D
(
N
)

/
D
(
N
)
0.0
Review of Definitions
delay
parasitic delay
effort delay
effort
branching effort
electrical effort
logical effort
number of stages
Path Stage Term
i
G g =

out-path
in-path
C
C
H =
N
i
B b =

F GBH =
F i
D f =

i
P p =

i F
D d D P = = +

out
in
C
C
h =
on-path off-path
on-path
C C
C
b
+
=
f gh =
f
p
d f p = +
g
1
Method of Logical Effort
1) Compute path effort
2) Estimate best number of stages
3) Sketch path with N stages
4) Estimate least delay
5) Determine best stage effort
6) Find gate sizes
F GBH =
4
log N F =
1
N
D NF P = +
1
N
f F =

i
i
i out
in
g C
C
f
=
Limits of Logical Effort
Chicken and egg problem
Need path to compute G
But dont know number of stages without G
Simplistic delay model
Neglects input rise time effects
Interconnect
Iteration required in designs with wire
Maximum speed only
Not minimum area/power for constrained delay
Summary
Logical effort is useful for thinking of delay in circuits
Numeric logical effort characterizes gates
NANDs are faster than NORs in CMOS
Paths are fastest when effort delays are ~4
Path delay is weakly sensitive to stages, sizes
But using fewer stages doesnt mean faster paths
Delay of path is about log
4
F FO4 inverter delays
Inverters and NAND2 best for driving large caps
Provides language for discussing fast circuits
But requires practice to master

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