Phase Locked Loop
Phase Locked Loop
A PLL is a negative feedback system where an oscillatorgenerated signal is phase and frequency locked to a reference signal. COMPONENTS OF A PHASE LOCKED LOOP PFD: outputs digital pulse whose width is proportional to phase error CP: converts digital error pulse to analog error current LPF: integrates (and low-pass filters) error current to generate VCO control voltage VCO: low-swing oscillator with frequency proportional to control voltage LS: amplifies VCO levels to full-swing DIV: divides VCO clock to generate FBCLK clock CIRCUIT DIAGRAM OF PHASE LOCKED LOOP
PRINCIPLE OF OPERATION
Before the input signal is applied, the PLL is in the free-running state. Once the input frequency is applied, the VCO frequency starts to change and the PLL is said to be in the capture mode. The VCO frequency continues to change until it equals the input frequency, and the PLL is then in the phase-locked state. When phase-locked, the loop tracks any change in the input frequency through its repetitive action.
APPLICATIONS
Phase-locked loops are widely used for synchronization purposes in space communications for coherent demodulation and threshold extension, bit synchronization, and symbol synchronization. Phase-locked loops can also be used to demodulate frequency-modulated signals. In radio transmitters, a PLL is used to synthesize new frequencies which are a multiple of a reference frequency, with the same stability as the reference frequency.
Clock recovery Deskewing Clock generation Spread spectrum Clock distribution Jitter and noise reduction Frequency Synthesis