Ms. PRIYANKA S. CHIKKALI* et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No.

9, Issue No. 2, 187 - 192

FPGA based Image Edge Detection and Segmentation

Prof. K. PRABHUSHETTY2
Department of Electronics and Communication, KLESCET, Belgaum, INDIA. [email protected]

Abstract The proposed work presents FPGA based architecture for Edge Detection using Sobel operator and uses Histogram method for Segmentation. Currently the image processing algorithms has been limited to software implementation which is slower due to the limited processor speed. So a dedicated processor for edge detection and segmentation is required which was not possible until advancement in VLSI technology. Now more complex system can be integrated on a single chip providing a platform to process real time algorithms on hardware. Sobel operator is chosen due to its property of less deterioration in high levels of noise. The conventional histogram method is modified to adopt for automatically determining the threshold for different regions in the image. Keywords Edge detection, operator, histogram, FPGA. segmentation, sobel

being re-programmable that adds flexibility in the development of image processing algorithms on FPGA. During the recent years FPGAs have become the dominant form of programmable logic. A. Edge detection Edge detection is a method of determining the discontinuities in gray level images. Edges are one of the most important elements in image analysis and processing in computer vision because they play quite a significant role in many applications of image processing particular for machine vision. However no single edge detection algorithm can successfully discover edges for diverse images and no specific quantitative measure of the quality for edge detection is given at present. Conventional edge detection mechanisms examine image pixels for abrupt changes by comparing pixels with their neighbours. This is often done by detecting the maximal value of gradient such as Roberts, Prewitt, Sobel, Canny and so on all of which are classical edge detectors. B. Segmentation Image segmentation is a very important application in the field of image processing. Image segmentation is the process of extracting features or regions of interest from an acquired image for further intelligent computer analysis. The image is sliced into multiple regions based on some property of the pixels. These properties are intensity, texture, position or some local or global statistical parameters. Segmentation using computer vision finds multiple applications especially in the area of biomedicine. Typical computer vision applications usually require an image segmentation preprocessing algorithm as a first procedure. At the output of this stage each object of the image represented by a set of pixels is isolated

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I. INTRODUCTION
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Field Programmable Gate Array (FPGA) technology is become an alternative for the implementation of software algorithms. The unique structure of the FPGA has allowed the technology to be used in many applications from video surveillance to medical imaging applications. FPGA is a large-scale integrated circuit that can be re-programmed. The term field programmable refers to ability of changing the operation of the device. Gate array refers to the basic internal architecture that makes re-programming possible. Implementations of real-time image processing algorithms can be done on general purpose microprocessors. The application of FPGA in image processing has a large impact on image or video processing. This is due to the potential of the FPGA to have parallel and high computational density as compared to a general purpose microprocessor. This step is coupled together with the ability of FPGA of

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from the rest of the scene. The purpose of this step is that the objects and background are separated into non-overlapping sets. Usually this segmentation process is based on the image gray-level histogram. In that case the aim is to find a critical value or threshold. When this threshold is applied to the whole image pixels whose gray levels exceed this critical value are assigned to one set and the rest to the other. For a welldefined image its histogram has a deep valley between two peaks. Around these peaks the object and background gray levels are concentrated. Thus to segment the image using some histogram thresholding technique the optimum threshold value must be located in the valley region.

edge detection is a terminology in image processing particularly in the areas of feature extraction to refer to algorithms which aim at identifying points in a digital image at which the image brightness changes sharply [4,5]. The data of edge detection is very large so the speed of image processing is a difficult problem. FPGA can overcome it [6]. Sobel operator is commonly used in edge detection. Sobel operator has been researched for parallelism [7] but Sobel operator locating complex edges are not accurate. It has been researched for the Sobel enhancement operator in order to locate the edge more accurate and less sensitive to noise but the software can not meet the real-time requirements [8].

II.

SYSTEM DESIGN AND ARCHITECTURE

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Figure 1. Data Flow Process of the Entire System.

The purpose of the design phase is to plan a solution of the problem specified by the requirement document. This phase is the first step in moving from the problem domain to the solution domain. The design of the system is perhaps the most critical factor affecting the quality of the hardware implementation. Here we build the System Block Diagram that is helpful to understand the behavior of the system. In the proposed work entire system is divided into following: 1. Conversion of image to text file using MATLAB. 2. Image Edge detection using Sobel Operator. 3. Image Segmentation using Histogram method. 4. Conversion of text file to image in MATLAB. The entire data flow of the work can be shown in Fig.1.

III.

IMPLEMENTATION OF IMAGE EDGE DETECTION USING FPGA

The edges of image are considered to be most important image attributes that provide valuable information for human image perception [1,3]. The

ISSN: 2230-7818

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The Sobel operator is a classic first order edge detection operator computing an approximation of the gradient of the image intensity function. At each point in the image the result of the Sobel operator is the corresponding norm of this gradient vector. The Sobel operator only considers the two orientations which are 0and 90convolution kernels as shown in Fig. 2.

Figure 2. Convolution Kernels in X and Y direction.

These kernels can then be combined together to find the absolute magnitude of the gradient at each point. The gradient magnitude is given by: Typically an approximate magnitude is computed using: This is much faster to compute. The Sobel operator has the advantage of simplicity in calculation. But the accuracy is relatively low because it only used two convolution kernels to detect the edge of image. B. FPGA Hardware Implementation This design uses 33 convolution kernels processing 256256 Gray Scale Image from the database in personal computer. The architecture is shown in Fig. 3.The system is divided into four modules: 33 pixel generation module, Sobel

A. Sobel Edge Detection Enhancement Algorithm

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enhancement operator module, edges control module and binary segmentation [9,10]. In this system, Clk is the clock signal, Reset is the reset signal and EN is data control signal, Data input is the pixel signal of Gray Scale Image, Result is the result of edge detection operator signal, Generation data and Data are the middle signal[2]. The function and structure of each module are as follows: The structure of 33 pixel generation module is shown in Fig. 4. This module consists of 3 shift register groups and two FIFO. The FIFO is used to cache a line of image data. The image data is input according to the clock signal so P1, P2, , P9 is the 33 image data template. When the data is continuously input, 33 image data template changes. It can contain all pixels of an image. The FIFO is generated by dual-port RAM [11].
Figure 5. Convolution Structure.

Figure 3. Architecture.

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Figure 4. 33 Pixel Generation Module.

In Sobel enhancement operator module the orientation convolution kernel uses parallel processing construction. The orientation convolution result is compared with each other and then the maximum value is the output. The pipeline structure is used to calculate each orientation convolution kernel. It is six corresponding input data because three coefficients of each convolution kernel are zero multiplied by 2. The structure is shown in Fig.5.

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IV.

The structure of edges control module is shown in Fig. 6. Clk is the clock signal and Reset is the reset signal. Turn is enable signal when the Turn is valid the module works. EN is the output data control signal. This module can know where the current pixel location is and whether it is the edges of the image. Sobel edge detection enhancement operator can not deal with the left edge, right edge, the up edge and down edge. In this design the result of the edge pixels is set to zero otherwise call the Sobel enhancement operator module.

The structure of binary segmentation module is shown in Fig. 7. EN is the output data control signal. Data is the result of the Sobel enhancement operator module. Result is 0 or 255. In this module the final result is the binary image of edge detection having only two pixel values according to the given threshold value i.e. 0 and 255.

The Image segmentation is a very important application in the field of image processing. Image segmentation is the process of extracting features or regions of interest from an acquired image for further

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Figure 6. Edges Control Module. Figure 7. Binary Segmentation.

IMPLEMENTATION OF IMAGE SEGMENTATION USING FPGA

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intelligent computer analysis. The image is sliced into multiple regions based on some property of the pixels. These properties are intensity, texture, position or some local or global statistical parameters. There are number of literatures on image segmentation both semiautomatic and automatic. Many segmentation algorithms have proved to be successful. But not much of work is done in the area of realizing hardware for any branch of image processing. In this work cell (i.e. pixel) network is used as the core of the architecture to implement segmentation with some degree of parallelism. An effort is made to integrate all the blocks used in the segmentation using histogram method. A. Automatic Segmentation Algorithm Based On Dynamic Threshold Segmentation based on threshold is one of the primitive segmentation techniques. The proposed work has implemented a simple but efficient thresholding technique for segmentation on FPGA. Threshold values are chosen from the histogram. Histogram is a counter arranged as a vector indexed from 0 to 255 (In a gray image pixels will vary from 0 to 255). Each counter will hold the number of pixels with the intensity value corresponding to the counter index. Conventional histogram fails when the peaks are not clearly defined or overlapping. This problem is overcome by identifying peaks within a defined neighbourhood. Peaks are determined in each region. This ensures that every distinct region within the image is extracted separately[15]. The segmentation algorithm is described in the following steps: Step 1. Determine the histogram of the image. Step 2. Set a width for the neighbourhood within the histogram. Step 3. Set the first counter in the histogram as the initial value. Step 4. Get the maximum value within the specified width ranging from the initial value. Step 5. Retain the maximum count value. Step 6. Increment the initial value and repeat the previous two steps until the last count. This gives almost a smoothened histogram from the original histogram as shown in Fig. 8. Step 7. Determine the largest Peak value and set this as the threshold. Step 8. Segment the image based on this threshold. One region gets extracted. Set certain offset to the threshold value as there is always variations among the pixels representing the same information or region. This limitation is due to the scanning hardware.

Step 9. Look for the next largest value from the remaining peaks. Carry out the segmentation as mentioned in the previous step. Step 10. Repeat step 9 till all the peaks are set for thresholding and segmenting.

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Figure 8. Histogram showing three Distinct Regions and the second figure shows three Peaks Extracted.

In the proposed algorithm threshold values are accurately and automatically determined for every region. Depending on the image the width of the region can be set. Fig. 8 shows the original histogram and the smoothened histogram to identify the different threshold values for the different regions present in the image. The threshold values are dynamically assigned from the histogram. This also enables the algorithm to segment image with any number of distinct regions. This makes the entire process of segmentation totally automatic. B. Architecture of FPGA Implementation for Segmentation The proposed segmentation processor has the architecture shown in Fig. 9. It consists of five functional blocks: 1.Interface, 2. Interlacer, 3. Memory, 4. Operator and 5. Control unit. The interface unit literally acts as the interface between the processor and the external data/instructions source. Interlacer unit is a register which converts the data from serial to parallel, parallel to serial and also provides serial in serial out, parallel in parallel out. Interlacer unit implements the parallelism in transferring the data too and fro between the memory and the external interface. The memory stores the pixels of the image. Operator performs the histogram calculation and thresholding part of the segmentation algorithm. And the control unit masters the interaction and timing of the different functional units.

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Fig. 10(b) shows gradient in X-direction for edge detection in MATLAB. Fig. 10(c) shows gradient in Y-direction for edge detection in MATLAB. Fig. 10(d) shows edge detection result in MATLAB. Fig. 10(e) shows edge detection result using VHDL.

Figure 9. Segmentation Processor Architecture.

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V. EXPERIMENTAL RESULTS
ISSN: 2230-7818

Memory is arranged in the form of an array of sequential rows. Row has cells to store each pixel value. This cell network stores the entire image. Memory is split into two sections of read/write memory. Write memory stores the image pixels for processing and the processed image is stored in the read memory section. The input data is connected to the write memory and the output data path is through the read memory. Operator unit performs the histogram computation and thresholding required for segmentation of the image. The algorithm is discussed earlier. The data from the memory unit is passed to the operator. The threshold value is offset with certain minimum value so as to take care of deviations within the pixels of the same region. The entire row of pixels is compared against the threshold value in one clock cycle. The thresholded pixels are stored in the read memory unit. Control unit monitors all the activities of the processor. It distinguishes the instruction from the data based on the data/instruction signal. This unit decodes the instruction and issues control signal to the interlacer to channel the data and activates the appropriate function in the operator unit. This unit subdivides the external instruction and generate control signals to execute it. Control signals are issued to the memory unit and the interface.

The experimental results for image edge detection in MATLAB and its comparison in VHDL are shown below: Fig. 10(a) is the original image for Edge Detection.

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Figure 10 (c) Figure 10 (e)

The hardware was realized on a Xilinx FPGA kit. The processor was coded using VHDL and simulated using Modelsim 6.3c. VHDL can not handle the standard image formats so the images were converted to ASCII text files using MATLAB. The ASCII text file was applied as vector to the hardware interface. The output files were similarly converted and viewed in MATLAB. The execution time for the entire program of edge detection for an image of size 256256 is few seconds. To improve the speed and efficiency pipelining can be further done in edge detection. Similarly segmentation can be implemented on hardware using the histogram method mentioned above.

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Figure 10 (d)

Figure 10 (a)

Figure 10 (b)

VI.

CONCLUSION

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[1] Jain, Anil K. (1989). Fundamentals of Digital Image Processing, Prentice-Hall, Inc. [2] Zhengyang Guo, Wenbo Xu Zhilei Chai Image Edge detection based on FPGA 2010 Ninth International Symposium on Distributed Computing and Applications to Business, Engineering [3]Gonzalez, Rafael C. and Woods, Richard E. (2002). Digital Image Processing, Pearson Education, Inc. [4] Pratt, W. K. (2004). Digital Image Processing, John Wiley & Sons, Inc. [5]Rafael C. Gonzalez, Richard E. Woods. Digital Image Processing (2nd Edition) Prentice Hall, 2nd edition (January 15, 2002) [6] D. T.Saegusa, T.Maruyama, Y.Yamaguchi, How fast is an FPGA in image processing?, IEICE Technical Report, Vol.108. No.48, 2008, pp.8388 [7] Yangli ,Yangbing. Study of FPGA based Parallel Processing of Sobel Operator AI Modern Electronics Technique 2005.J. [8] SHEN fengting WEI hong An Improved Thread Edge Detection Method Based On Sobel Algorithm. Control&Automation 2008. [9] Steve Kilts, Advanced FPGA Design: Arichitecture , Implementation , and Optimization , John Tiley & Sons. [10] Arrigo Benedetti, Andrea Prati, Nello Scarabottolo. Image convolution on FPGAs: the implementation of a multi-FPGA FIFO structure. Euromicro Conference, 1998. [11] Spartan FPGA Complete Data Sheet Xilinx Inc. [12] P. Athanas and A. Abbott. Real-time image processing on acustom computing platform. In IEEE Computer, Feb. 1995 [13] Bellon, O.R.P. Silva, L. New improvements to range image segmentation by edge detection Signal Processing Letters, IEEE Volume 9, Issue 2, Feb. 2002 Page(s):43 -45 [14] Gevers, T. Robust segmentation and tracking of color objects in video, Circuits and Systems for Video Technology IEEE Transactions on, Volume 14, Issue 6, Jun 2004. pp:776 - 781. [15] Shanthi K J, Ashok L R, Anandu A S and Gokul Das BFPGA Implementation of Image Segmentation Processor. Second International Conference on Emerging Trends in Engineering and Technology, ICETET-09 [16] T.Morimoto,Y. Harada, T. Koide and H J Mattauschs, A Pixel Parallel digital CMOS implementation of image segmentation by region growing, IEEE Proceedings Circuits Devices and Systems, Vol 152,No.6 Dec 2005. [17] K Yamohaka, T. Morimoto, H Adachi, T. Koide, and H.J. Mattausch Image Segmentation and Pattern Matching Based FPGA/ASIC Implementation Architecture of Real Time Object Tracking Design Automation, 2006. Asia and South Pacific Conference on 2006, IEEE Pages :6pp

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