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Experiment 17: Implement and Verify Asynchronous Counter Using Verilog HDL

The document describes an experiment to implement and verify an asynchronous counter using Verilog HDL. It discusses the theory of ripple counters and synchronous counters. The experiment involves designing ripple up, down, and up/down counters in Verilog code. RTL schematics and simulation waveforms are shown to verify the correct functionality of each counter design.

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Shalini Sharma
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69 views6 pages

Experiment 17: Implement and Verify Asynchronous Counter Using Verilog HDL

The document describes an experiment to implement and verify an asynchronous counter using Verilog HDL. It discusses the theory of ripple counters and synchronous counters. The experiment involves designing ripple up, down, and up/down counters in Verilog code. RTL schematics and simulation waveforms are shown to verify the correct functionality of each counter design.

Uploaded by

Shalini Sharma
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Experiment 17

Object: Implement and verify Asynchronous Counter using Verilog HDL. Software Used: Theory:
A register that goes through a prescribed sequence of states upon the application of input pulses is called a counter. The input pulses may be clock pulses, or they may originate from some external source and may occur at a fixed interval of time or at random. Counters are available in two categories: ripple counters and synchronous counters. In a ripple counter, a flipflop output transition serves as a source for triggering other flipflops. In other words, the C input of some or all flipflops are triggered, not by the common clock pulses, but rather by the transition that occurs in other flip flop outputs.
XILINX ISE 8.2i

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Verilog Code for Ripple up counter:module tff(t,clk,reset,q); input t,clk,reset; output reg q=1'b0; always@(negedge clk,posedge reset) begin if(reset) q=1'b0; else if(t) q=~q; end endmodule module up_counter(count,reset,a0,a1,a2,a3); input count,reset; output a0,a1,a2,a3; tff t0(1'b1,count,reset,a0); tff t1(1'b1,a0,reset,a1); tff t2(1'b1,a1,reset,a2); tff t3(1'b1,a2,reset,a3); endmodule

RTL Schematic of Ripple up counter -

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Simulation Waveforms of Ripple up counter:-

Verilog Code Ripple down counter:module tff(t,clk,reset,q,qb); input t,clk,reset; output reg q=1'b0,qb=1'b1; always@(negedge clk,posedge reset) begin if(reset) begin q=1'b0; qb=1'b1; end else if(t) begin q=~q; qb=~qb; end end endmodule module up_counter(count,reset,a0,a1,a2,a3); input count,reset; output a0,a1,a2,a3; wire w0,w1,w2,w3; tff t0(1'b1,count,reset,a0,w0); tff t1(1'b1,w0,reset,a1,w1); tff t2(1'b1,w1,reset,a2,w2); tff t3(1'b1,w2,reset,a3,w3); endmodule

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RTL Schematic of Serial Ripple down counter

Simulation Waveforms of Ripple down counter:-

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Verilog Code Ripple up/down counter:module tff(t,clk,reset,q); input t,clk,reset; output reg q=1'b0; always@(negedge clk,posedge reset) begin if(reset) q=1'b0; else if(t) q=~q; end endmodule module up_counter(count,reset,a0,a1,a2,a3,down); input count,reset,down; output a0,a1,a2,a3; wire w0,w1,w2; tff t0(1'b1,count,reset,a0); xor(w0,a0,down); tff t1(1'b1,w0,reset,a1); xor(w1,a1,down); tff t2(1'b1,w1,reset,a2); xor(w2,a2,down); tff t3(1'b1,w2,reset,a3); endmodule

RTL Schematic of Ripple up/down counter

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Simulation Waveforms of Ripple up/down counter:-

Conclusion: Asynchronous Counter were designed using Verilog HDL and its working is verified using ISE Simulator.

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