Scribd
Upload
18 views

Chip Multicore Processors - Tutorial 7: Task 7.1: Memory Overhead of Cache Coherency

This document discusses cache coherency protocols for multicore processors. It provides tasks to calculate the memory overhead of snooping-based and directory-based coherency and analyze the states of caches using MSI and MESI protocols.

Uploaded by

Bobby Beaman
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
18 views

Chip Multicore Processors - Tutorial 7: Task 7.1: Memory Overhead of Cache Coherency

This document discusses cache coherency protocols for multicore processors. It provides tasks to calculate the memory overhead of snooping-based and directory-based coherency and analyze the states of caches using MSI and MESI protocols.

Uploaded by

Bobby Beaman
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

MUNCHEN TECHNISCHE UNIVERSITAT Lehrstuhl f ur Integrierte Systeme

Chip Multicore Processors Tutorial 7


June 12, 2013

Task 7.1: Memory Overhead of Cache Coherency


Given is the sketched system, which integrates p processor cores and their caches. Each of the caches has size c1 . The cores share a last level cache of size c2 . All cache blocks are of size l. A memory of size m is connected to the system. Cache coherency can either be snooping-based or directory-based. Snooping adds 2 extra bits to the caches and the directory implementation requires 3 bits plus a bitvector. a) Calculate the required memory bits for snooping- and directorybased coherency. b) Calculate the extra memory of an embedded system with 32 MB memory, 32 kB L1 cache and 256 kB L2 cache. The cache blocks are of 4 words. c) Calculate the extra memory of a desktop system with 4096 MB memory, 512 kB L1 cache and 4 MB L2 cache. The cache blocks are of 8 words.

L1 Dir

L1 L2 Mem

L1

Task 7.2: Basics of Cache Coherency


a) Three caches use snooping-based cache coherency with a shared bus. Complete the states of the cache entries according to the MSI protocol for the given operations (nomenclature: (core) operation).
t 0 1 2 3 4 5 6 7 Operation (1) Read (1) Write (0) Read (2) Write (2) Read (0) Read (0) Write C0 I C1 I C2 I Beschreibung

2 b) Do the same according to the MESI protocol.


t 0 1 2 3 4 5 6 7 Operation (1) Read (1) Write (0) Read (2) Write (2) Read (0) Read (0) Write C0 I C1 I C2 I Beschreibung

c) According to you, what extensions does a bus need to support snooping-based cache coherency? d) For MSI and MESI sketch the valid state combinations for one entry in two caches.

You might also like