Data Sheet

FEATURES

1 kV RMS Six-Channel Digital Isolators ADuM7640/ADuM7641/ADuM7642/ADuM7643

FUNCTIONAL BLOCK DIAGRAMS
VDD1A 1 GND1 2 VIA 3 VIB 4 VIC 5 VID 6 VDD1B 7 VIE 8 VIF 9 GND1 10
ENCODE ENCODE DECODE DECODE ENCODE ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE

Small 20-lead QSOP 1000 V rms isolation rating Safety and regulatory approvals (pending): UL recognition (pending) 1000 V rms for 1 minute per UL 1577 Low power operation 3.3 V operation 1.6 mA per channel maximum at 0 Mbps to 1 Mbps 7.8 mA per channel maximum at 25 Mbps 5 V operation 2.2 mA per channel maximum at 0 Mbps to 1 Mbps 11.2 mA per channel maximum at 25 Mbps Bidirectional communication Up to 25 Mbps data rate (NRZ) 3 V/5 V level translation High temperature operation: 105C High common-mode transient immunity: >15 kV/s

ADuM7640

20 VDD2A 19 GND2 18 VOA 17 VOB 16 VOC 15 VOD 14 VDD2B 13 VOE

10448-001

12 VOF 11 GND2

Figure 1. ADuM7640
VDD1A 1 GND1 2 VIA 3 VIB 4 VIC 5 VID 6 VDD1B 7 VOE 8 VIF 9 GND1 10
DECODE ENCODE ENCODE DECODE ENCODE ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE

ADuM7641

20 19 18 17 16 15 14 13 12 11

VDD2A GND2 VOA VOB VOC VOD VDD2B VIE

10448-002

APPLICATIONS
General-purpose, multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation

VOF GND2

Figure 2. ADuM7641
VDD1A 1 GND1 2 VIA 3 VIB 4 VIC 5 VOD 6 VDD1B 7 VOE 8 VIF 9 GND1 10
DECODE ENCODE ENCODE DECODE ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE ENCODE

GENERAL DESCRIPTION
The ADuM7640/ADuM7641/ADuM7642/ADuM76431 are 6-channel digital isolators based on the Analog Devices, Inc., iCoupler technology. These 1 kV digital isolation devices are packaged in a small 20-lead QSOP. They offer space savings and a lower price than 2.5 kV or 5 kV isolation solutions when only functional isolation is needed. This family, like many Analog Devices isolators, offers very low power consumption, using one-tenth to one-sixth the power of other digital isolators, with the supply voltage on either side ranging from 3.0 V to 5.5 V. Despite their low power consumption, the ADuM7640/ADuM7641/ADuM7642/ADuM7643 provide low pulse width distortion (< 6 ns for C grade) and a channelby-channel glitch filter to protect the device against extraneous noise disturbances. Four channel direction combinations are available with a maximum data rate of 1 Mbps or 25 Mbps. All products have a default output high logic state in the absence of input power.

ADuM7642

20 VDD2A 19 GND2 18 VOA 17 VOB 16 VOC 15 VID 14 VDD2B 13 VIE

10448-003

12 VOF 11 GND2

Figure 3. ADuM7642
VDD1A 1 GND1 2 VIA 3 VIB 4 VOC 5 VOD 6 VDD1B 7 VOE 8 VIF 9 GND1 10
DECODE ENCODE ENCODE DECODE ENCODE ENCODE DECODE DECODE DECODE DECODE ENCODE ENCODE

ADuM7643

20 19 18 17 16 15 14 13 12 11

VDD2A GND2 VOA VOB VIC VID VDD2B VIE

10448-004

VOF GND2

Figure 4. ADuM7643
1

Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending.

Rev. 0

Document Feedback
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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www.analog.com

ADuM7640/ADuM7641/ADuM7642/ADuM7643 TABLE OF CONTENTS

Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams ............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics5 V Operation................................ 3 Electrical Characteristics3.3 V Operation ............................ 5 Electrical CharacteristicsMixed 5 V/3.3 V Operation ........ 7 Electrical CharacteristicsMixed 3.3 V/5 V Operation ........ 8 Package Characteristics ............................................................... 9 Regulatory Information ............................................................... 9 Insulation and Safety Related Specifications ............................ 9 Recommended Operating Conditions ...................................... 9

Data Sheet
Absolute Maximum Ratings ......................................................... 10 ESD Caution................................................................................ 10 Pin Configurations and Function Descriptions ......................... 11 Typical Performance Characteristics ........................................... 15 Applications Information .............................................................. 17 Printed Circuit Board Layout ................................................... 17 Propagation Delay-Related Parameters ................................... 17 DC Correctness ............................................................................ 17 Magnetic Field Immunity............................................................. 18 Power Consumption .................................................................. 19 Insulation Lifetime ..................................................................... 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20

REVISION HISTORY
9/12Revision 0: Initial Version

Rev. 0 | Page 2 of 20

Data Sheet SPECIFICATIONS

ELECTRICAL CHARACTERISTICS5 V OPERATION

ADuM7640/ADuM7641/ADuM7642/ADuM7643

All typical specifications are at TA = 25C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended operation range of 4.5 V VDD1 5.5 V, 4.5 V VDD2 5.5 V, and 40C TA +105C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 1.
Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew 1 Channel Matching Codirectional 2 Opposing Directional 3 Jitter
1

Symbol PW tPHL, tPLH PWD

Min 250

A Grade Typ Max

Min 40

C Grade Typ Max

Unit ns Mbps ns ns ps/C ns ns ns ns

Test Conditions/Comments Within PWD limit Within PWD limit 50% input to 50% output |tPLH tPHL|

1 75 25 5 20 25 30 2

28

40 2 3

25 50 6 14

tPSK tPSKCD tPSKOD

6 7 2

12 12

tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 2 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 3 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the isolation barrier.

Table 2.
Parameter SUPPLY CURRENT ADuM7640 ADuM7641 ADuM7642 ADuM7643 Symbol IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 1 MbpsA and C Grades Min Typ Max 5.7 4.4 5.5 4.6 5.2 4.8 4.8 5.0 7.0 5.9 6.8 5.7 6.3 6.0 6.0 6.3 25 MbpsC Grade Min Typ Max 44 11 38 15 31 19 24 22 54 13 46 19 38 24 30 29 Unit mA mA mA mA mA mA mA mA Test Conditions/Comments No load

Rev. 0 | Page 3 of 20

ADuM7640/ADuM7641/ADuM7642/ADuM7643
Table 3.
Parameter DC SPECIFICATIONS Input Voltage Threshold Logic High Logic Low Output Voltages Logic High Logic Low Input Current per Channel Supply Current per Channel Quiescent Supply Current Input Output Dynamic Supply Current Input Output AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 1 Refresh Rate
1

Data Sheet
Max Unit Test Conditions/Comments

Symbol

Min

Typ

VIH VIL VOH VOL II

0.7 VDDx 0.3 VDDx VDDx 0.1 VDDx 0.4 5.0 4.8 0.0 0.2 +0.01

V V V V V V A IOx = 20 A, VIx = VIxH IOx = 4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL 0 V VIx VDDx

10

0.1 0.4 +10

IDDI (Q) IDDO (Q) IDDI (D) IDDO (D) tR/tF |CM| fr

0.95 0.73 0.26 0.04 2.0 25 600

1.16 0.98

mA mA mA/Mbps mA/Mbps ns kV/s kHz 10% to 90% VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V DC data inputs

15

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 VDDLx or VOH > 0.7 VDDIx. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

Rev. 0 | Page 4 of 20

Data Sheet
ELECTRICAL CHARACTERISTICS3.3 V OPERATION

ADuM7640/ADuM7641/ADuM7642/ADuM7643

All typical specifications are at TA = 25C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended operation range of 3.0 V VDD1 3.6 V, 3.0 V VDD2 3.6 V, and 40C TA +105C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 4.
Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew 1 Channel Matching Codirectional 2 Opposing Directional 3 Jitter
1

Symbol PW tPHL, tPLH PWD

Min 250

A Grade Typ Max

Min 40

C Grade Typ Max

Unit ns Mbps ns ns ps/C ns ns ns ns

Test Conditions/Comments Within PWD limit Within PWD limit 50% input to 50% output |tPLH tPHL|

1 85 25 5 20 25 30 2

33

49 2 3

25 66 6 14

tPSK tPSKCD tPSKOD

6 6 2

12 15

tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 2 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 3 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the isolation barrier.

Table 5.
Parameter SUPPLY CURRENT ADuM7640 ADuM7641 ADuM7642 ADuM7643 Symbol IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 1 MbpsA and C Grades Min Typ Max 4.1 3.3 3.9 3.4 3.7 3.5 3.5 3.6 5.2 4.3 4.9 4.2 4.7 4.4 4.4 4.5 25 MbpsC Grade Min Typ Max 32 7.2 27 11 23 14 18 16 38 8.7 33 13 27 16 21 20 Unit mA mA mA mA mA mA mA mA Test Conditions/Comments No load

Rev. 0 | Page 5 of 20

ADuM7640/ADuM7641/ADuM7642/ADuM7643
Table 6.
Parameter DC SPECIFICATIONS Input Voltage Threshold Logic High Logic Low Output Voltages Logic High Logic Low Input Current per Channel Supply Current per Channel Quiescent Supply Current Input Output Dynamic Supply Current Input Output AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 1 Refresh Rate
1

Data Sheet
Max Unit Test Conditions/Comments

Symbol

Min

Typ

VIH VIL VOH VOL II

0.7 VDDx 0.3 VDDx VDDx 0.2 VDDx 0.5 3.3 3.1 0.0 0.2 +0.01

V V V V V V A IOx = 20 A, VIx = VIxH IOx = 4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL 0 V VIx VDDx

10

0.1 0.4 +10

IDDI (Q) IDDO (Q) IDDI (D) IDDO (D) tR/tF |CM| fr

0.68 0.55 0.19 0.03 2.8 20 550

0.87 0.72

mA mA mA/Mbps mA/Mbps ns kV/s kHz 10% to 90% VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V DC data inputs

15

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 VDDLx or VOH > 0.7 VDDIx. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

Rev. 0 | Page 6 of 20

Data Sheet

ADuM7640/ADuM7641/ADuM7642/ADuM7643

ELECTRICAL CHARACTERISTICSMIXED 5 V/3.3 V OPERATION

All typical specifications are at TA = 25C, VDD1 = 5 V, VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended operation range of 4.5 V VDD1 5.5 V, 3.0 V VDD2 3.6 V, and 40C TA +105C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 7.
Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew 1 Channel Matching Codirectional 2 Opposing Directional 3 Jitter
1

Symbol PW tPHL, tPLH PWD

Min 250

A Grade Typ Max

Min 40

C Grade Typ Max

Unit ns Mbps ns ns ps/C ns ns ns ns

Test Conditions/Comments Within PWD limit Within PWD limit 50% input to 50% output |tPLH tPHL|

1 80 25 5 20 25 30 2

30

42 2 3

25 58 6 14

tPSK tPSKCD tPSKOD

5 8 2

15 15

tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 3 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the isolation barrier.
2

Table 8.
Parameter SUPPLY CURRENT ADuM7640 ADuM7641 ADuM7642 ADuM7643 Symbol IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 Symbol 1 MbpsA, C Grades Min Typ Max 5.7 3.3 5.4 3.4 5.1 3.5 4.8 3.6 Min 7.0 4.1 6.8 4.0 6.3 4.3 6.0 4.3 Typ 25 MbpsC Grade Min Typ Max 44 7.5 38 11 31 14 24 16 Max 54 8.7 46 13 38 16 30 20 Unit mA mA mA mA mA mA mA mA Unit Test Conditions/Comments Test Conditions/Comments No load

Table 9.
Parameter DC SPECIFICATIONS Input Voltage Threshold Logic High Logic Low Output Voltages Logic High Logic Low Input Current per Channel AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 1 Refresh Rate
1

VIH VIL VOH VOL II tR/tF |CM| fr

0.7 VDDx 0.3 VDDx VDDx 0.1 VDDx 0.5 VDDx VDDx 0.2 0.0 0.2 +0.01 2.5 20 600

V V V V V V A ns kV/s kHz IOx = 20 A, VIx = VIxH IOx = 4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL 0 V VIx VDDx 10% to 90% VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V DC data inputs

10

0.1 0.4 +10

15

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 VDDLx or VOH > 0.7 VDDIx. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. 0 | Page 7 of 20

ADuM7640/ADuM7641/ADuM7642/ADuM7643
ELECTRICAL CHARACTERISTICSMIXED 3.3 V/5 V OPERATION

Data Sheet

All typical specifications are at TA = 25C, VDD1 = 3.3 V, VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended operation range of 3.0 V VDD1 3.6 V, 4.5 V VDD2 5.5 V, and 40C TA +105C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 10.
Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew 1 Channel Matching Codirectional 2 Opposing Directional 3 Jitter
1

Symbol PW tPHL, tPLH PWD

Min 250

A Grade Typ Max

Min 40

C Grade Typ

Max

Unit ns Mbps ns ns ps/C ns ns ns ns

Test Conditions/Comments Within PWD limit Within PWD limit 50% input to 50% output |tPLH tPHL|

1 80 25 5 20 25 30 2

29

46 2 3

25 60 6 14

tPSK tPSKCD tPSKOD

6 9 2

13 18

tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 3 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the isolation barrier.
2

Table 11.
Parameter SUPPLY CURRENT ADuM7640 ADuM7641 ADuM7642 ADuM7643 Symbol IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 Symbol 1 MbpsA, C Grades Min Typ Max 4.1 4.5 3.9 4.6 3.7 4.8 3.5 5.0 Min 4.9 5.9 4.7 5.7 4.4 6.0 4.2 6.2 Typ 25 MbpsC Grade Min Typ Max 32 11 27 15 23 19 18 22 Max 38 13 33 19 27 24 21 29 Unit mA mA mA mA mA mA mA mA Unit Test Conditions/Comments Test Conditions/Comments No load

Table 12.
Parameter DC SPECIFICATIONS Input Voltage Threshold Logic High Logic Low Output Voltages Logic High Logic Low Input Current per Channel AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 1 Refresh Rate
1

VIH VIL VOH VOL II tR/tF |CM| fr

0.7 VDDx 0.3 VDDx VDDx 0.1 VDDx 0.5 VDDx VDDx 0.2 0.0 0.2 +0.01 2.5 20 550

V V V V V V A ns kV/s kHz IOx = 20 A, VIx = VIxH IOx = 4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL 0 V VIx VDDx 10% to 90% VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V DC data inputs

10

0.1 0.4 +10

15

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 VDDLx or VOH > 0.7 VDDIx. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. 0 | Page 8 of 20

Data Sheet
PACKAGE CHARACTERISTICS
Table 13.
Parameter Resistance (Input to Output) 1 Capacitance (Input to Output)1 Input Capacitance 2 IC Junction-to-Ambient Thermal Resistance
1 2

ADuM7640/ADuM7641/ADuM7642/ADuM7643

Symbol RI-O CI-O CI JA

Min

Typ 1013 2 4.0 76

Max

Unit pF pF C/W

Test Conditions/Comments f = 1 MHz Thermocouple located at center of package underside

The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together. Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION
The ADuM7640/ADuM7641/ADuM7642/ADuM7643 are approved by the organizations listed in Table 14. See Table 18 and the Insulation Lifetime section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 14.
UL (Pending) Recognized Under UL 1577 Component Recognition Program 1 Single Protection,1000 V rms Isolation Voltage File E274400
1

In accordance with UL 1577, each ADuM7640/ADuM7641/ADuM7642/ADuM7643 is proof tested by applying an insulation test voltage 1200 V rms for 1 sec (current leakage detection limit = 5 A).

INSULATION AND SAFETY RELATED SPECIFICATIONS

Table 15.
Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group
350

Symbol L(I01) L(I02)

Value 1000 3.8 2.8 2.6 >400 II

Unit V rms mm min mm min m min V

CTI

Test Conditions/Comments 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1)

RECOMMENDED OPERATING CONDITIONS

Table 16.
Parameter Operating Temperature Supply Voltages 1 Input Signal Rise and Fall Times
1

300

SAFETY-LIMITING CURRENT (mA)

250 200

Symbol TA VDD1, VDD2

Min 40 3.0

Max +105 5.5 1.0

Unit C V ms

150 100 50 0 0 50 100 150 CASE TEMPERATURE (C) 200

All voltages are relative to their respective grounds. See the DC Correctness section for information about immunity to external magnetic fields.

Figure 5. Thermal Derating Curve, Dependence of Safety-Limiting Values on Case Temperature per DIN V VDE V 0884-10

10448-005

Rev. 0 | Page 9 of 20

ADuM7640/ADuM7641/ADuM7642/ADuM7643 ABSOLUTE MAXIMUM RATINGS

TA = 25C, unless otherwise noted. Table 17.
Parameter Storage Temperature (TST) Range Ambient Operating Temperature (TA) Supply Voltages (VDD1, VDD2) Input Voltages (VIA, VIB, VIC, VID, VIE, VIF)1, 2 Output Voltages (VOA, VOB, VOC, VOD, VIE, VIF)1, 2 Average Output Current per Pin3 Side 1 (IO1) Side 2 (IO2) Common-Mode Transients3
1

Data Sheet
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rating 65C to +150C 40C to +105C 0.5 V to +7.0 V 0.5 V to VDDI + 0.5 V 0.5 V to VDDO + 0.5 V

ESD CAUTION

10 mA to +10 mA 10 mA to +10 mA 100 kV/s to +100 kV/s

VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the Printed Circuit Board Layout section. 2 See Figure 5 for maximum rated current values for various temperatures. 3 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage.

Table 18. Maximum Continuous Working Voltage 1

Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Basic Insulation DC Voltage Basic Insulation
1

Max 420 420 420

Unit V peak V peak V peak

Constraint 50-year minimum lifetime 50-year minimum lifetime 50-year minimum lifetime

Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.

Table 19. Truth Table (Positive Logic)

VIx Input 1 H L X X VDDI State 2 Powered Powered Unpowered Powered VDDO State 3 Powered Powered Powered Unpowered VOxOutput1 H L H Z Description Normal operation; data is high. Normal operation; data is low. Input unpowered. Output pins are in the default high state. Outputs return to input state within 1.6 s of VDDI power restoration. See the pin function descriptions (Table 20 through Table 23) for more information. Output unpowered. Output pins are in high impedance state. Outputs return to input state within 1.6 s of VDDO power restoration. See the pin function descriptions (Table 20 through Table 23Table 22) for more information.

VIx and VOx refer to the input and output signals of a given channel (A, B, C, D, E or F). VDDI refers to the supply voltage on the input side of a given channel (A, B, C, D, E or F). 3 VDDO refers to the supply voltage on the output side of a given channel (A, B, C, D, E or F).
1 2

Rev. 0 | Page 10 of 20

Data Sheet

ADuM7640/ADuM7641/ADuM7642/ADuM7643

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VDD1A 1 GND1* 2 VIA 3 VIB 4 VIC 5 VID 6 VDD1B 7 VIE 8 VIF 9 GND1* 10
20 19 18

VDD2A GND2* VOA VOB VOC VOD VDD2B VOE VOF GND2*

ADuM7640
TOP VIEW (Not to Scale)

17 16 15 14 13 12 11

*PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED. CONNECTING BOTH PINS TO PCB SIDE 1 GROUND IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED. CONNECTING BOTH PINS TO PCB SIDE 2 GROUND IS RECOMMENDED.

Figure 6. ADuM7640 Pin Configuration

Table 20. ADuM7640 Pin Function Descriptions

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic VDD1A GND1 VIA VIB VIC VID VDD1B VIE VIF GND1 GND2 VOF VOE VDD2B VOD VOC VOB VOA GND2 VDD2A Description Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a 0.01 F to 0.1 F between VDD1A (Pin 1) and GND1 (Pin 2). Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB ground plane is recommended. Logic Input A. Logic Input B. Logic Input C. Logic Input D. Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a 0.01 F to 0.1 F between VDD1B (Pin 7) and GND1 (Pin 10). Logic Input E. Logic Input F. Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB ground plane is recommended. Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB ground plane is recommended. Logic Output F. Logic Output E. Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 14 must be connected externally to Pin 20. Connect a 0.01 F to 0.1 F between VDD2B (Pin 14) and GND2 (Pin 11). Logic Output D. Logic Output C. Logic Output B. Logic Output A. Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB ground plane is recommended. Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 20 must be connected externally to Pin 14. Connect a 0.01 F to 0.1 F between VDD2A (Pin 20) and GND2 (Pin 19).

Reference the AN-1109 Application Note for specific layout guidelines.

Rev. 0 | Page 11 of 20

10448-006

ADuM7640/ADuM7641/ADuM7642/ADuM7643
VDD1A 1 GND1* 2 VIA 3 VIB 4 VIC 5 VID 6 VDD1B 7 VOE 8 VIF 9 GND1* 10
20 VDD2A 19 GND2* 18 VOA

Data Sheet

ADuM7641
TOP VIEW (Not to Scale)

17 VOB 16 VOC 15 VOD 14 VDD2B 13 VIE 12 VOF 11 GND2*

*PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED. CONNECTING BOTH PINS TO PCB SIDE 1 GROUND IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED. CONNECTING BOTH PINS TO PCB SIDE 2 GROUND IS RECOMMENDED.

Figure 7. ADuM7641 Pin Configuration

Table 21. ADuM7641 Pin Function Descriptions

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic VDD1A GND1 VIA VIB VIC VID VDD1B VOE VIF GND1 GND2 VOF VIE VDD2B VOD VOC VOB VOA GND2 VDD2A Description Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a 0.01 F to 0.1 F between VDD1A (Pin 1) and GND1 (Pin 2). Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB ground plane is recommended. Logic Input A. Logic Input B. Logic Input C. Logic Input D. Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a 0.01 F to 0.1 F between VDD1B (Pin 7) and GND1 (Pin 10). Logic Output E. Logic Input F. Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB ground plane is recommended. Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB ground plane is recommended. Logic Output F. Logic Input E. Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 14 must be connected externally to Pin 20. Connect a 0.01 F to 0.1 F between VDD2B (Pin 14) and GND2 (Pin 11). Logic Output D. Logic Output C. Logic Output B. Logic Output A. Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB ground plane is recommended. Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 20 must be connected externally to Pin 14. Connect a 0.01 F to 0.1 F between VDD2A (Pin 20) and GND2 (Pin 19).

Reference the AN-1109 Application Note for specific layout guidelines.

Rev. 0 | Page 12 of 20

10448-007

Data Sheet
VDD1A 1 GND1* 2 VIA 3 VIB 4 VIC 5 VOD 6 VDD1B 7 VOE 8 VIF 9 GND1* 10

ADuM7640/ADuM7641/ADuM7642/ADuM7643
20 VDD2A 19 GND2* 18 VOA

ADuM7642
TOP VIEW (Not to Scale)

17 VOB 16 VOC 15 VID 14 VDD2B 13 VIE 12 VOF 11 GND2*

*PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED. CONNECTING BOTH PINS TO PCB SIDE 1 GROUND IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED. CONNECTING BOTH PINS TO PCB SIDE 2 GROUND IS RECOMMENDED.

Figure 8. ADuM7642 Pin Configuration

Table 22. ADuM7642 Pin Function Descriptions

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic VDD1A GND1 VIA VIB VIC VOD VDD1B VOE VIF GND1 GND2 VOF VIE VDD2B VID VOC VOB VOA GND2 VDD2A Description Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a 0.01 F to 0.1 F between VDD1A (Pin 1) and GND1 (Pin 2). Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB ground plane is recommended. Logic Input A. Logic Input B. Logic Input C. Logic Output D. Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a 0.01 F to 0.1 F between VDD1B (Pin 7) and GND1 (Pin 10). Logic Output E. Logic Input F. Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB ground plane is recommended. Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB ground plane is recommended. Logic Output F. Logic Input E. Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 14 must be connected externally to Pin 20. Connect a 0.01 F to 0.1 F between VDD2B (Pin 14) and GND2 (Pin 11). Logic Input D. Logic Output C. Logic Output B. Logic Output A. Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB ground plane is recommended. Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 20 must be connected externally to Pin 14. Connect a 0.01 F to 0.1 F between VDD2A (Pin 20) and GND2 (Pin 19).

Reference the AN-1109 Application Note for specific layout guidelines.

Rev. 0 | Page 13 of 20

10448-008

ADuM7640/ADuM7641/ADuM7642/ADuM7643
VDD1A 1 GND1* 2 VIA 3 VIB 4 VOC 5 VOD 6 VDD1B 7 VOE 8 VIF 9 GND1* 10
20 VDD2A 19 GND2* 18 VOA

Data Sheet

ADuM7643
TOP VIEW (Not to Scale)

17 VOB 16 VIC 15 VID 14 VDD2B 13 VIE 12 VOF 11 GND2*

*PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED. CONNECTING BOTH PINS TO PCB SIDE 1 GROUND IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED. CONNECTING BOTH PINS TO PCB SIDE 2 GROUND IS RECOMMENDED.

Figure 9. ADuM7643 Pin Configuration

Table 23. ADuM7643 Pin Function Descriptions

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic VDD1A GND1 VIA VIB VOC VOD VDD1B VOE VIF GND1 GND2 VOF VIE VDD2B VID VIC VOB VOA GND2 VDD2A Description Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a 0.01 F to 0.1 F between VDD1A (Pin 1) and GND1 (Pin 2). Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB ground plane is recommended. Logic Input A. Logic Input B. Logic Output C. Logic Output D. Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a 0.01 F to 0.1 F between VDD1B (Pin 7) and GND1 (Pin 10). Logic Output E. Logic Input F. Ground Reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both pins to the PCB ground plane is recommended. Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB ground plane is recommended. Logic Output F. Logic Input E. Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 14 must be connected externally to Pin 20. Connect a 0.01 F to 0.1 F between VDD2B (Pin 14) and GND2 (Pin 11). Logic Input D. Logic Input C. Logic Output B. Logic Output A. Ground Reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both pins to the PCB ground plane is recommended. Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 20 must be connected externally to Pin 14. Connect a 0.01 F to 0.1 F between VDD2A (Pin 20) and GND2 (Pin 19).

Reference the AN-1109 Application Note for specific layout guidelines.

Rev. 0 | Page 14 of 20

10448-009

Data Sheet
10

ADuM7640/ADuM7641/ADuM7642/ADuM7643
45 40

TYPICAL PERFORMANCE CHARACTERISTICS

8
35

IDD1 CURRENT (mA)

CURRENT (mA)

30 25 20 15 10 5
3.3V

6
5V

5V

4
3.3V

10448-010

10

15

20

25

30

10

15

20

25

DATA RATE (Mbps)

DATA RATE (Mbps)

Figure 10. Typical Supply Current per Input Channel vs. Data Rate for 5 V and 3.3 V Operation
4

Figure 13. Typical ADuM7640 VDD1 Supply Current vs. Data Rate for 5 V and 3.3 V Operation
12

10

IDD2 CURRENT (mA)

CURRENT (mA)

8
5V

2
5V

6
3.3V

1
3.3V

10448-011

10

15

20

25

30

10

15

20

25

DATA RATE (Mbps)

DATA RATE (Mbps)

Figure 11. Typical Supply Current per Output Channel vs. Data Rate for 5 V and 3.3 V Operation (No Output Load)
4

Figure 14. Typical ADuM7640 VDD2 Supply Current vs. Data Rate for 5 V and 3.3 V Operation
40 35

30

IDD1 CURRENT (mA)

CURRENT (mA)

25
5V

5V

20 15
3.3V

3.3V

10 5

10448-012

10

15

20

25

30

10

15

20

25

DATA RATE (Mbps)

DATA RATE (Mbps)

Figure 12. Typical Supply Current per Output Channel vs. Data Rate for 5 V and 3.3 V Operation (15 pF Output Load)

Figure 15. Typical ADuM7641 VDD1 Supply Current vs. Data Rate for 5 V and 3.3 V Operation

Rev. 0 | Page 15 of 20

10448-015

10448-014

10448-013

ADuM7640/ADuM7641/ADuM7642/ADuM7643
18 16 14 20 25

Data Sheet

IDD2 CURRENT (mA)

12
5V

IDD2 CURRENT (mA)

15
5V

10 8 6 4 2
10448-016

3.3V

10
3.3V

10

15

20

25

10

15

20

25

DATA RATE (Mbps)

DATA RATE (Mbps)

Figure 16. Typical ADuM7641 VDD2 Supply Current vs. Data Rate for 5 V and 3.3 V Operation
35 30

Figure 18. Typical ADuM7642 VDD2 Supply Current vs. Data Rate for 5 V and 3.3 V Operation

30

25

IDD1 CURRENT (mA)

IDD1 CURRENT (mA)

25

20
5V

20
5V

15
3.3V

15
3.3V

10

10

10

15

20

25

10448-017

10

15

20

25

DATA RATE (Mbps)

DATA RATE (Mbps)

Figure 17. Typical ADuM7642 VDD1 Supply Current vs. Data Rate for 5 V and 3.3 V Operation

Figure 19. Typical ADuM7643 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3.3 V Operation

Rev. 0 | Page 16 of 20

10448-019

10448-018

Data Sheet APPLICATIONS INFORMATION

PRINTED CIRCUIT BOARD LAYOUT
The ADuM7640/ADuM7641/ADuM7642/ADuM7643 digital isolators require no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 20). Connect four bypass capacitors between Pin 1 and Pin 2 for VDD1A, between Pin 7 and Pin 10 for VDD1B, between Pin 11 and Pin 14 for VDD2B, and between Pin 19 and Pin 20 for VDD2A. Connect the VDD1A supply pin and the VDD1B supply pin together, and connect the VDD2B supply pin and VDD2A supply pin together. The capacitor values should be from 0.01 F to 0.1 F. The total lead length between both ends of the capacitor and the power supply pin should not exceed 20 mm.
VDD1A GND1 VIA VIB VIC/VOC VID/VOD VDD1B VIE/VOE VIF GND1 VDD2A GND2 VOA VOB VOC/VIC VOD/VID VDD2B VOE/VIE VOF GND2

ADuM7640/ADuM7641/ADuM7642/ADuM7643
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The input-tooutput propagation delay time for a high-to-low transition may differ from the propagation delay time for a low-to-high transition.
INPUT (VIx) 50%

tPLH
OUTPUT (VOx)

tPHL
50%
10448-021

Figure 21. Propagation Delay Parameters

Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved. Channel-to-channel matching refers to the maximum amount of time that the propagation delay differs between channels within a single ADuM7640/ADuM7641/ADuM7642/ADuM7643 component. Propagation delay skew refers to the maximum amount of time that the propagation delay differs between multiple ADuM7640/ ADuM7641/ADuM7642/ADuM7643 components operating under the same conditions.

Figure 20. Recommended Printed Circuit Board Layout

In applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. Furthermore, users should design the board layout so that any coupling that occurs affects all pins equally on a given component side. Failure to follow this design guideline can cause voltage differentials between pins that exceed the absolute maximum ratings of the device, which can lead to latch-up or permanent damage. With proper PCB design choices, the ADuM7640/ADuM7641/ ADuM7642/ADuM7643 can readily meet CISPR 22 Class A (and FCC Class A) emissions standards, as well as the more stringent CISPR 22 Class B (and FCC Class B) standards in an unshielded environment. For PCB-related EMI mitigation techniques, including board layout and stack-up issues, see the AN-1109 Application Note.

10448-020

DC CORRECTNESS
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder using the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 s, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default high state by the watchdog timer circuit.

Rev. 0 | Page 17 of 20

ADuM7640/ADuM7641/ADuM7642/ADuM7643
MAGNETIC FIELD IMMUNITY
The magnetic field immunity of the ADuM7640/ADuM7641/ ADuM7642/ADuM7643 is determined by the changing magnetic field, which induces a voltage in the transformer receiving coil large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM7640/ADuM7641/ ADuM7642/ADuM7643 is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at approximately 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (d/dt) rn2; n = 1, 2, , N where: is magnetic flux density (gauss). rn is the radius of the nth turn in the receiving coil (cm). N is the total number of turns in the receiving coil. Given the geometry of the receiving coil in the ADuM7640/ ADuM7641/ADuM7642/ADuM7643 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field at a given frequency can be calculated. The result is shown in Figure 22.
MAXIMUM ALLOWABLE MAGNETIC FLUX (kgauss)
1000

Data Sheet
The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM7640/ ADuM7641/ADuM7642/ADuM7643 transformers. Figure 23 shows these allowable current magnitudes as a function of frequency for selected distances. As shown in Figure 23, the ADuM7640/ ADuM7641/ADuM7642/ADuM7643 are extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted previously, a 1.2 kA current would have to be placed 5 mm away from the ADuM7640/ADuM7641/ ADuM7642/ADuM7643 to affect the operation of the component.
1000

MAXIMUM ALLOWABLE CURRENT (kA)

100

10

0.1 DISTANCE = 5mm DISTANCE = 100mm DISTANCE = 1m 0.01 1k 10M 10k 100k 1M MAGNETIC FIELD FREQUENCY (Hz) 100M
10448-023

Figure 23. Maximum Allowable Current for Various Current-to-ADuM7640/ADuM7641/ADuM7642/ADuM7643 Spacings

100

10

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces can induce error voltages sufficiently large to trigger the thresholds of succeeding circuitry. Take care in the layout of such traces to avoid this possibility.

0.1

0.01

10k

100k

1M

10M

100M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 22. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.5 kgauss induces a voltage of 0.25 V at the receiving coil. This voltage is approximately 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse and is of the worst-case polarity, it reduces the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder.

Rev. 0 | Page 18 of 20

10448-022

0.001 1k

Data Sheet
POWER CONSUMPTION
The supply current at a given channel of the ADuM7640/ ADuM7641/ADuM7642/ADuM7643 isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel. For each input channel, the supply current is given by IDDI = IDDI (Q) IDDI = IDDI (D) (2f fr) + IDDI (Q) IDDO = IDDO (Q)
3

ADuM7640/ADuM7641/ADuM7642/ADuM7643
The insulation lifetime of the ADuM7640/ADuM7641/ ADuM7642/ADuM7643 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 24, Figure 25, and Figure 26 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the bipolar ac condition determines the Analog Devices recommended maximum working voltage. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 18 can be applied while maintaining the 50-year minimum lifetime, provided that the voltage conforms to either the unipolar ac or dc voltage case. Any cross-insulation voltage waveform that does not conform to Figure 25 or Figure 26 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 18. The voltage presented in Figure 25 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.
RATED PEAK VOLTAGE 0V
10448-024

f 0.5 fr f > 0.5 fr f 0.5 fr

For each output channel, the supply current is given by IDDO = (IDDO (D) + (0.5 10 ) CL VDDO) (2f fr) + IDDO (Q) f > 0.5 fr where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA). f is the input logic signal frequency (MHz); it is half the input data rate, expressed in units of Mbps. fr is the input stage refresh rate (Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). To calculate the total VDD1 and VDD2 supply current, the supply currents for each input and output channel corresponding to VDD1 and VDD2 are calculated and totaled. Figure 10 and Figure 11 show per-channel supply currents as a function of data rate for an unloaded output condition. Figure 12 shows the per-channel supply current as a function of data rate for a 15 pF output condition. Figure 13 through Figure 17 show the total VDD1 and VDD2 supply current as a function of data rate for ADuM7640/ ADuM7641/ADuM7642/ADuM7643 channel configurations.

Figure 24. Bipolar AC Waveform

RATED PEAK VOLTAGE

10448-025

INSULATION LIFETIME
All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation depends on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM7640/ADuM7641/ADuM7642/ ADuM7643 components. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 18 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.
Rev. 0 | Page 19 of 20

0V

Figure 25. Unipolar AC Waveform

RATED PEAK VOLTAGE

10448-026

0V

Figure 26. DC Waveform

ADuM7640/ADuM7641/ADuM7642/ADuM7643 OUTLINE DIMENSIONS

0.345 (8.76) 0.341 (8.66) 0.337 (8.55)

Data Sheet

20

11

10

0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79)

0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10)

0.069 (1.75) 0.053 (1.35) SEATING PLANE 0.012 (0.30) 0.008 (0.20)

0.010 (0.25) 0.006 (0.15)

0.020 (0.51) 0.010 (0.25)

0.025 (0.64) BSC

8 0

0.050 (1.27) 0.016 (0.41)

0.041 (1.04) REF

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 27. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20) Dimensions shown in inches and (millimeters)

ORDERING GUIDE
Model 1 ADuM7640ARQZ ADuM7640ARQZ-RL7 ADuM7640CRQZ ADuM7640CRQZ-RL7 ADuM7641ARQZ ADuM7641ARQZ-RL7 ADuM7641CRQZ ADuM7641CRQZ-RL7 ADuM7642ARQZ ADuM7642ARQZ-RL7 ADuM7642CRQZ ADuM7642CRQZ-RL7 ADuM7643ARQZ ADuM7643ARQZ-RL7 ADuM7643CRQZ ADuM7643CRQZ-RL7
1

Number of Inputs, VDD1 Side 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3

Number of Inputs, VDD2 Side 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3

Maximum Data Rate 1 Mbps 1 Mbps 25 Mbps 25 Mbps 1 Mbps 1 Mbps 25 Mbps 25 Mbps 1 Mbps 1 Mbps 25 Mbps 25 Mbps 1 Mbps 1 Mbps 25 Mbps 25 Mbps

Maximum Propagation Delay, 5 V 20 ns 20 ns 14 ns 14 ns 20 ns 20 ns 14 ns 14 ns 20 ns 20 ns 14 ns 14 ns 20 ns 20 ns 14 ns 14 ns

Maximum Pulse Width Distortion 75 ns 75 ns 50 ns 50 ns 75 ns 75 ns 50 ns 50 ns 75 ns 75 ns 50 ns 50 ns 75 ns 75 ns 50 ns 50 ns

Temperature Range 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C

Package Description 20-Lead QSOP 20-Lead QSOP, 7 Tape and Reel 20-Lead QSOP 20-Lead QSOP, 7 Tape and Reel 20-Lead QSOP 20-Lead QSOP, 7 Tape and Reel 20-Lead QSOP 20-Lead QSOP, 7 Tape and Reel 20-Lead QSOP 20-Lead QSOP, 7 Tape and Reel 20-Lead QSOP 20-Lead QSOP, 7 Tape and Reel 20-Lead QSOP 20-Lead QSOP, 7 Tape and Reel 20-Lead QSOP 20-Lead QSOP, 7 Tape and Reel

08-19-2008-A

COMPLIANT TO JEDEC STANDARDS MO-137-AD

Package Option RQ-20 RQ-20 RQ-20 RQ-20 RQ-20 RQ-20 RQ-20 RQ-20 RQ-20 RQ-20 RQ-20 RQ-20 RQ-20 RQ-20 RQ-20 RQ-20

Z = RoHS Compliant Part.

2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10448-0-9/12(0)

Rev. 0 | Page 20 of 20