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Quartus II Functional vs. Timing Simulations

The document discusses the differences between functional and timing simulations in Quartus II. It notes that some logic devices in the Quartus library have timing issues. It recommends doing a functional simulation rather than a timing simulation to avoid these issues. A functional simulation will produce output waveforms without propagation delays, so it will not show glitches that may occur in real hardware. The document provides instructions for running a functional simulation and notes that functional simulations do not accurately model real-world timing behavior.

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Gurpreet Dhillon
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89 views1 page

Quartus II Functional vs. Timing Simulations

The document discusses the differences between functional and timing simulations in Quartus II. It notes that some logic devices in the Quartus library have timing issues. It recommends doing a functional simulation rather than a timing simulation to avoid these issues. A functional simulation will produce output waveforms without propagation delays, so it will not show glitches that may occur in real hardware. The document provides instructions for running a functional simulation and notes that functional simulations do not accurately model real-world timing behavior.

Uploaded by

Gurpreet Dhillon
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Quartus II Functional vs. Timing Simulations.

The 74390, 74393, 74192 and 74193 devices in the Quartus others\maxplus2 library have timing problems. In fact they are not equivalent to the actual HC-devices that youve been using in the lab! If youve tried to simulate the circuits from the last couple of labs youve found that out. Anyway, heres a simulation solution to the timing problems associated with those devices...

Dont do a Timing mode simulation, do a Functional mode simulation instead!


Heres how: 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) Draw the circuit as you normally would. Save the file. Compile the file (make sure you set it to top-level before you compile it). Open a New .VWF file and insert the nodes as you normally would. Save the file with a descriptive name (NOT waveform1!) Click on Processing Simulator Tool Select a Functional Simulation Mode not Timing mode. Click on the Generate Functional Simulation Netlist button. Press the Start button. The simulator will produce output waveforms for an ideal circuit, no propagation delays!

A few things to note: Functional sims have no propagation delays and therefore will NOT show glitches in the simulation waveforms. So if you simulate your MOD-6 asynchronous counter from lab-7 you wont see the temporary state reset glitch on the Qb output. Please have a look at my load9 counter circuit and Functional vs. Timing simulations for more information. Theyre in the shareout\elex2115\lab\simulations\ folder.

Have fun, but remember simulations arent always real world.

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