C:/Users/ASIC/Desktop/Project/MIPI LLI/ip/FifoSync64x24.

// // // // // // // // // // // // // // // // //

megafunction wizard: %FIFO% GENERATION: STANDARD VERSION: WM1.0 MODULE: scfifo ============================================================ File Name: FifoSync64x24.v Megafunction Name(s): scfifo Simulation Library Files(s): altera_mf ============================================================ ************************************************************ THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 10.1 Build 197 01/19/2011 SP 1 SJ Full Version ************************************************************

//Copyright (C) 1991-2011 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module FifoSync64x24 ( clock, data, rdreq, sclr, wrreq, almost_full, empty, full, q, usedw); input input input input input output output output output output clock; [23:0] data; rdreq; sclr; wrreq; almost_full; empty; full; [23:0] q; [5:0] usedw;

wire [5:0] sub_wire0; wire sub_wire1; wire sub_wire2; wire [23:0] sub_wire3; wire sub_wire4;
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wire [5:0] usedw = sub_wire0[5:0]; wire empty = sub_wire1; wire full = sub_wire2; wire [23:0] q = sub_wire3[23:0]; wire almost_full = sub_wire4; scfifo scfifo_component ( .clock (clock), .sclr (sclr), .wrreq (wrreq), .data (data), .rdreq (rdreq), .usedw (sub_wire0), .empty (sub_wire1), .full (sub_wire2), .q (sub_wire3), .almost_full (sub_wire4), .aclr (), .almost_empty ()); scfifo_component.add_ram_output_register = "ON", scfifo_component.almost_full_value = 62, scfifo_component.intended_device_family = "Cyclone IV GX", scfifo_component.lpm_numwords = 64, scfifo_component.lpm_showahead = "ON", scfifo_component.lpm_type = "scfifo", scfifo_component.lpm_width = 24, scfifo_component.lpm_widthu = 6, scfifo_component.overflow_checking = "ON", scfifo_component.underflow_checking = "ON", scfifo_component.use_eab = "ON"; endmodule // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // ============================================================ CNX file retrieval info ============================================================ Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" Retrieval info: PRIVATE: AlmostFull NUMERIC "1" Retrieval info: PRIVATE: AlmostFullThr NUMERIC "62" Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" Retrieval info: PRIVATE: Clock NUMERIC "0" Retrieval info: PRIVATE: Depth NUMERIC "64" Retrieval info: PRIVATE: Empty NUMERIC "1" Retrieval info: PRIVATE: Full NUMERIC "1" Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" Retrieval info: PRIVATE: Optimize NUMERIC "1" Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" Retrieval info: PRIVATE: UsedW NUMERIC "1" Retrieval info: PRIVATE: Width NUMERIC "24" Retrieval info: PRIVATE: dc_aclr NUMERIC "0" Retrieval info: PRIVATE: diff_widths NUMERIC "0" Retrieval info: PRIVATE: msb_usedw NUMERIC "0" Retrieval info: PRIVATE: output_width NUMERIC "24" Retrieval info: PRIVATE: rsEmpty NUMERIC "1" Retrieval info: PRIVATE: rsFull NUMERIC "0" Retrieval info: PRIVATE: rsUsedW NUMERIC "0" Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
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defparam

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// Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: "almost_full" // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info: // Retrieval info:

PRIVATE: sc_sclr NUMERIC "1" PRIVATE: wsEmpty NUMERIC "0" PRIVATE: wsFull NUMERIC "1" PRIVATE: wsUsedW NUMERIC "0" LIBRARY: altera_mf altera_mf.altera_mf_components.all CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON" CONSTANT: ALMOST_FULL_VALUE NUMERIC "62" CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" CONSTANT: LPM_NUMWORDS NUMERIC "64" CONSTANT: LPM_SHOWAHEAD STRING "ON" CONSTANT: LPM_TYPE STRING "scfifo" CONSTANT: LPM_WIDTH NUMERIC "24" CONSTANT: LPM_WIDTHU NUMERIC "6" CONSTANT: OVERFLOW_CHECKING STRING "ON" CONSTANT: UNDERFLOW_CHECKING STRING "ON" CONSTANT: USE_EAB STRING "ON" USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]" USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty" USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full" USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]" USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr" USED_PORT: usedw 0 0 6 0 OUTPUT NODEFVAL "usedw[5..0]" USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" CONNECT: @clock 0 0 0 0 clock 0 0 0 0 CONNECT: @data 0 0 24 0 data 0 0 24 0 CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0 CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0 CONNECT: empty 0 0 0 0 @empty 0 0 0 0 CONNECT: full 0 0 0 0 @full 0 0 0 0 CONNECT: q 0 0 24 0 @q 0 0 24 0 CONNECT: usedw 0 0 6 0 @usedw 0 0 6 0 GEN_FILE: TYPE_NORMAL FifoSync64x24.v TRUE GEN_FILE: TYPE_NORMAL FifoSync64x24.inc FALSE GEN_FILE: TYPE_NORMAL FifoSync64x24.cmp FALSE GEN_FILE: TYPE_NORMAL FifoSync64x24.bsf FALSE GEN_FILE: TYPE_NORMAL FifoSync64x24_inst.v FALSE GEN_FILE: TYPE_NORMAL FifoSync64x24_bb.v TRUE LIB_FILE: altera_mf

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