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Iterative Logarithmic Multiplier: by Abhishek Reddy G Jagadeeshwara Prasad Y Uday Kiran N

This document describes an iterative logarithmic multiplier circuit based on Mitchell's algorithm. It uses encoders, shifters, MSB detectors and decoders to approximate the logarithms of two input numbers, add the results, and take the antilogarithm to obtain the product. The key components designed for this circuit are two 8-bit MSB detectors, two 4-to-2 encoders, a 3-to-8 decoder, two 8-bit dynamic shifters and two 8-bit and one 2-bit adders. This iterative logarithmic multiplier offers advantages of significantly less logic, easy computation, small area, high speed and efficiency for large operands making it suitable for image and signal processing applications.

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27 views9 pages

Iterative Logarithmic Multiplier: by Abhishek Reddy G Jagadeeshwara Prasad Y Uday Kiran N

This document describes an iterative logarithmic multiplier circuit based on Mitchell's algorithm. It uses encoders, shifters, MSB detectors and decoders to approximate the logarithms of two input numbers, add the results, and take the antilogarithm to obtain the product. The key components designed for this circuit are two 8-bit MSB detectors, two 4-to-2 encoders, a 3-to-8 decoder, two 8-bit dynamic shifters and two 8-bit and one 2-bit adders. This iterative logarithmic multiplier offers advantages of significantly less logic, easy computation, small area, high speed and efficiency for large operands making it suitable for image and signal processing applications.

Uploaded by

uday11x
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Iterative Logarithmic Multiplier

By Abhishek Reddy G Jagadeeshwara Prasad Y Uday Kiran N

Contents:

Introduction Mitchells Algorithm Block Diagram Components designed Design and Layout Advantages

Introduction:
Significant

process in Digital Signal Processing and arithmetic units. Challenge: Involves lot of computation and time. In DSP applications accuracy is not a constraint. Our design is based on Mitchells Algorithm-uses encoders, shifters, MSB 1 detectors and decoders.

Mitchells Algorithm:
N1

* N2 = Logarithm(N1,N2) >> Add logs >> Antilog(result). Each binary number k 1 can be represented as, N 2k (1 2i k Z i ) 2k (1 X ) i j Using approximation of 3 4 Ex : 10010 2 (1 2i 4 Z i ) 2 4 (1 0.125) logarithms, we get i 0
log 2 N k log 2 (1 X ) N1* N 2 log 2 N1 log 2 N 2 k1 k 2 log 2 (1 X 1) log 2 (1 X 2)

log 2 ( N1.N 2) k1 k 2 X 1 X 2

Block Diagram:

Iterative multiplier:

Components designed:
Two

8 bit MSB 1 detectors Two 4 to 2 bit Encoders One 3 to 8 bit decoder Two 8 bit dynamic shifters Two 8 bit & one 2 bit adder

Schematic and Layout:

Advantages:
Significantly

less logic Easy computation Small area Less components High speed Mostly suitable in Image and Signal Processing applications Very efficient for large sized operands

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