C8813 Service Manual

V1.0

Directory

Chapter 1 : Introduction 1.1 Appearance 1.2 Product Features Chapter 2 : Repair information described in Guidelines 2.1 Documentation Instructions 2.2 aintenance Considerations 2.! aintenance "uidelines for access to information

Chapter ! hosts e#ploded dia"ram

Chapter $ motherboard components location map Chapter % &oft'are (p"rade %.1 before up"radin" to prepare %.2 (p"radin" the hard'are connection %.! (&) dri*er installation %.!.1 up"rade process %.!.2 Forced (p"rade %.$ &D up"rade %.$.1 &D card normal up"rade %.$.2 &D card is mandatory up"rade %.% +#ception ,andlin" Chapter -: Repair .ools Chapter /: Fi"ure disassemble step Chapter 0: Installation steps Fi"ure Chapter 1: obile principle and failure analysis 1.1 )loc2 dia"ram and introduce mobile phone 1.2 baseband unit 1.2. A po'er mana"ement circuit s'itched 1.2.2 char"e mana"ement circuit 1.2.! cloc2 circuit 1.2.$ Flash circuit 1.! G& radio unit 1.!.1 CD A RF transcei*er circuit 1.!.2 G& RF transcei*er circuit 1.$ peripheral circuits 1.$.1 Display 1.$.2 3ibration 1.$.! Recei*er and &P4 1.$.$ microphone 1.$.% headphones 1.$.- &I card

1.$./ I5 Interface 1.$.0 &D Card Interface 1.$.1 F 6 ). Chapter 17 :of the PC) and )GA chip solder indication map Chapter 11: Functional .est 11.1 4eyboard and Features 11.2 I test 11.! 3oice .est

Chapter 1

obile principle and failure analysis

1.1 )loc2 dia"ram and introduce mobile phone

C001! is a 8ualcomm & 0-2%9based independent research and de*elopment of CD A candy bar phone: the use of 8(A;C5 Incorporated & 0-2% P 0721 ch )oard includes & 0-2%: P 0721: RF de*ices: connected by FPC ;CD: Recei*er: &pea2er by shrapnel and otherboard connector: IC connected to the board by solderin": 'eldin" motor &I card < &D card soft board: throu"h the connector to the motherboard 'ith +*en. RF antenna connected by shrapnel: 'ith shell structure: batteries: constitutes a 'hole. In addition to pro*idin" basic *oice: &hort messa"e function: also supports phone boo2 and & & sa*ed in the (I card and mobile phone t'o stora"e modes: support icro&D card stora"e. ,ard'are .he support F radio and recordin" function. C001! supports color .F. ;CD: dot number is 0%$ = $07> pro*ide e#ternal icro (&) type char"er interface: (I cards Interface: support for polyphonic rin"tones and *ibration function: F function. RF antenna built9in: optional 1/77mAh lithium battery: CD A standby .ime of $77hrs around ?'ith the actual net'or2 related@: continuous tal2 time of about 11 hrs ?'ith the actual net'or2 related@.

1.2 baseband unit 1.2.1 )oot po'er mana"ement circuits Circuit dia"ram: 4PD PAR 5B

C001!

aintenance

anual 31.7

Circuit theory analysis: C001! uses separate po'er mana"ement chip P 0721: the principle of all by the po'er of 8ualcomm code control: po'er on the map by the principle 4PDCPARC5B detection *olta"e is acti*e lo'. .he po'er mains *olta"e in the 3,PCPAR process by P 0721 po'er mana"ement chip transfer Chan"e the table belo' to "et a *ariety of *olta"e:

Failure analysis process: Can not boot into boot no fault current: lo' current: hi"h current and other cate"ories: many machines are due to po'er anomalies caused: Ahen faced 'ith a similar po'er failure: please troubleshoot problems caused by po'er supply circuit in accordance 'ith troubleshootin" methods. 1 boot no current: DC po'er boot: press the po'er button: display the current DC po'er from 7 to %mA> 2 )oot ;ittle Current: DC po'er boot: press the po'er button: the DC po'er display current %mA to 177mA> ! lar"e boot current: DC po'er boot: press the po'er button: the display current !77mA DC po'er o*er> Ahen the situation C001! phone can not boot: can fail to Dud"e by obser*in" DC po'er supply current. 1. Bo current

Does not boot +#ternal fa2e batteries and electrical repairs &ource: press the po'er button: obser*e the po'er Flo' Bo current Ahether the 2eys copper o#ideE B easure 3P,CPAR 3olta"e is normal !.$ to $.2 G aintenance of po'er supply *olta"e F Clean button

Inspection (271

F
Chec2 'hether the cloc2 is normalE B Chec2 the cloc2 H!71 (!171

F
Depot Repair

2.A small current Does not boot +#ternal fa2e batteries and electrical repairs &ource: press the po'er button: obser*e the po'er Flo' A small current Detect P .he output *olta"e is Bo normalE F easure H!71 .he output freIuency is G !2./-04,J 5r (!171 +#port 11.2 ,J B Inspection (271

Re9'eldin" or replacement H!71 (!171

F Depot Repair

!.A lar"e current Does not boot +#ternal fa2e batteries and electrical repairs &ource: press the po'er button: obser*e the po'er Flo' A ;ar"e current Detection K1-11 ! Pin GroundedE B (271 detection *olta"e is normalE B Re9'eldin" or replace (271 F Detection (271 and K1-11

F
Depot Repair

1.2.2 char"e mana"ement circuit Circuit dia"ram:

circuit theory analysis: C001! uses P 0721 po'er mana"ement chip: the internal inte"ration of the char"in" scheme: there are three char"in" status: red tric2le po'er: constant Current char"in" and constant *olta"e char"in". ,a*e adopted the same char"e path: (&)C3C,G L 3C,G L 3P,CPAR L 8271: pin! L 3)A. (sin" FAB%$72(CH dedicated po'er chip 1A char"in": usin" I2C communication and control: t'o interfaces GPI51! ?I2CC&C;CDCDC@: GPI510 ?I2CC&DACDCDC@. .his char"e mana"ement chip strai"ht from 3C,AG (&) interface..hen ta2e po'er from the I2C control. 5utput 3P,CPAR is po'ered P : 'hile char"in" the battery. .he functional bloc2 dia"ram as follo's:

$91- char"in" chip functional bloc2 dia"ram

Char"in" flo' dia"ram as follo's:

Char"in" flo' dia"ram in Fi"ure $91/ .his chip has three modes: char"e mode: boost mode and hi"h9impedance mode. Bormal start char"in" mode char"in" process: boost ode is (&)95.G mode: hi"h9impedance mode is not char"in" po'er sa*in" mode ?standby@. Ahen the e#ternal po'er supply ?char"er or (&)@ connection to the phone: to determine the e#ternal *olta"e is "reater than 3u*loP : then loo2 3A(HPAR M3;5A3 ?specific meanin" to the battery *olta"e is less than the ma#imum battery *olta"e@. If the battery *olta"e is ma#imum: no char"e +lectricity> Instead: start the char"in" process.

&e*eral *olta"e and current e#planation: 3 ?&,5R.@ tric2le char"in": constant current char"e startin" *olta"e 3 ?5R+G@: constant current char"in": constant *olta"e char"in" start *olta"e I5 ?C,ARG+@ constant char"in" current I ?IBC;I I.@ constant char"in" current limit: and I5 ?C,ARG+@ 29to91 I ?&,5R.@ tric2le char"e current 3 ?RC,@ As the rechar"eable battery *olta"e )y monitorin" the cell phone chip C&5(. pin mains *olta"e: 'hen the battery *olta"e is less than 3 ?&,5R.@: start the tric2le char"e> Ahen electricity )attery *olta"e is "reater than 3 ?&,5R.@ is less than 3 ?5R+G@ constant current char"in" starts> Ahen the battery *olta"e is appro#imately eIual to 3 ?5R+G@: constant *olta"e char"in" start +lectricity> Ahen the char"e current is less than a certain *alue 'hile the *olta"e e#ceeds a certain ran"e 3 ?RC,@: stop char"in". Chip built9in 1% minutes and !2 seconds timer: sa*in" CP( resources: automatically starts 1% minutes timer that no i2c control: parameter use to load their o'n char"e. If the CP( *ia I2C control: then starts a !2 second timer. Process is as follo's:

)82$1%2 timer flo'chart in Fi"ure $910 under char"in" mode Actual circuit hard'are 5.G man recei*ed a le*el "reater than 1.$3: the initial char"in" char"in" port is limited to the ma#imum current the 'hole %77mA: the char"in" process to be detected after a specific soft'are to disable this limit. FAB%$72(CH has its o'n temperature detection function Able: 'hen the temperature reaches the upper limit .K .CF: reducin" the char"e current: stop char"in" 'hen 'hen .K is less than the upper temperature limit .CF17 de"rees: hea*y Be' start char"in". Ahen the char"in" *olta"e 3)(& char"e *olta"e is less than the sleep ?3A(HPAR 6 3slp@ 'hen: FAB%$72(CH into sleep mode to sa*e po'er. FAB%$72(CH can continue char"in" *olta"e detection 3)(&: 3IB ?min@ 'hen 3)(& is less than the set threshold: Re9determine the phone stops char"in" and 'ait for a .IB.. FAB%$72(CH 'ith char"in" o*er*olta"e protection: battery o*er9 *olta"e protection Function: battery rei"n detection: no battery start.

Failure analysis process: &ymptom: .he phone is not char"in" failure is usually the case: there are t'o: First: after the char"er is connected to the phone: the phone did not respond> Another phone 'hile char"in" is displayed: but can not char"e the battery. For no char"e fault plane: first detected I < 5 interfaces: ;oo2 for any ob*ious dama"e. After the char"er is connected to the phone: the phone 'ithout char"in" indicator After the char"er is connected to the phone: the phone has a char"in" indicator: but you can not char"e the battery Into the char"er is not char"in"

Char"er is 'or2in" properlyE

Replacement char"er

5bser*ation (&) connector K171 'hether AeldE

K171 'eldin"

Are there *olta"e measurement B C2!1E

Chec2 fuses F171 and beads ;)171

F
Chec2 'hether the char"in" chip (171 5utput *olta"e 3P,CPAR B Replacin" (171

F
Chec2 'hether the output pin ! 8271E F )attery connector K172 is dama"edE B If the battery is dama"edE B +nd F Chan"e )attery F Replace the battery connector K172 B Replacin" 8271

.his section schematics si"nal summary: &i"nal Bame Function Details

USB_VCHG

.est Reference *alue or 'a*eform chart

Charger power input. External USB powered charging chip input. Charge control signal chip. Charge control signal chip. The main power supply to the power supply module here
0N 5 V

VCHG

I2C_SCL_DCDC

No No Supply voltage variation range 0-4.2V

I2C_SDA_DCDC

VPH_PWR

BAT_FET_N

MOS transistor battery (Q201) of the control output. Battery voltage Battery voltage variation range 0-4.2V No No

VBAT

USB_HS_DP

USB differential data positive input USB differential data positive input.

USB_HS_DN

1.2.! cloc2 circuit Circuit dia"ram: 11.2 ,J

Circuit theory analysis:

As Fi"ure: 11.2 ,J cloc2 output access P 0721 and R.R-20%A: .P4C;5CADK control precision cloc2 output. .P4C;5CADK has t'o filter circuit: R27$: C2!2 and R!171: C!171. After P output to the host system as the main chip Cloc2. !2./-02,J crystal oscillator input to the P 0721: the P output to the system Failure analysis process: &ymptom: .he phone does not boot: or easy to crash: chec2 !2./-02,J crystal oscillator H!71 detection and (!171 ha*e not A si"nal: or the freIuency is stable. &olution: Replace the H!71 or (!171: to see 'hether it is normal: other'ise replace the P 0721.

.his section schematics si"nal summary: &i"nal Bame

XTAL32K _OUT

Function Details

.est Reference *alue or 'a*eform chart

32.768kHz master clock signal output terminal

XTAL32K_IN

32.768kHz master clock signal input terminal

VREG_TCXO

19.2MHz crystal power 19.2MHz frequency control signal output 19.2MHz clock output

2.85V NO

TRK_LO_ADJ

RTR6285_TCXO

TCXO

19.2MHz clock output

9.2.4 Flash circuit Circuit diagram:

Circuit theory analysis: & 0-2% can be accessed throu"h the hi"h9speed bus +)I1 connected thereto by ;PDDR PoP ?Pac2a"e9on9pac2a"e@: At the same time: but also the lo'9speed access to e#ternal memory bus +)I2 e C by one: as sho'n belo':

Fi"ure $92 C001! +

obile

emory Interface Analysis C de*ices.

C uses ei"ht data lines for transmission: C001! products usin" the $G +

Failure analysis process: &ymptom: .he phone does not boot or boot currents can rise to tens of mA: Processin" methods: (p"rade or loadin" soft'are: testin" 3R+GCDCDCC2P0% *olta"e is normal: if normal peripheral de*ices: 'hether Replace the (1077.

.his section schematics si"nal summary: &i"nal Bame Function Details .est Reference *alue or 'a*eform ap

&DC!CDA.A! SDC3_DATA2 SDC3_DATA1 SDC3_DATA0 SDC3_DATA7 SDC3_DATA6 SDC3_DATA5 SDC3_DATA4 SDC3_CLK SDC3_CMD VREG_DCDC_2P85 VREG_S3 MSM_RESOUT_N VPH_PWR

Data line Data line Data line Data line Data line Data line Data line Data line Cloc2 Command

Flash Power Power supply

Reset &ystem po'er: 2.0%3 DCDC chip po'er supply

2.85V 1.8V

1.! G& radio unit .he band CD A G&

s'itch "atin" circuit schematics

&'itch &elect .ruth .able )ehind the main antenna RF s'itch model is $/1$77!2: 'hich control lo"ic list is as follo's:

Select the ANT_SEL0 (GPIO75) band

CDMA CELL GSM 900 GSM 900 GSM 1800 GSM 1800 GSM 1900 GSM 1900 TX/RX TX RX TX RX TX RX

ANT_SEL1 (GPIO74)

ANT_SEL2 (GPIO73)

ANT_SEL3 (GPIO72)

0 0 1 0 1 0 1

0 0 x 0 x 0 x

1 0 1 1 1 1 1

0 1 1 1 0 1 0

Description: on the table O;O *olta"e ran"e is 7 P 7.23: O,O *olta"e ran"e 1.0 P !.73. OHO indicates not in*ol*ed. .hese control si"nals "i*en by the & 0-2%. 1.!.1 CD A RF transcei*er circuit .H C+;; D(P;+H+R Q PA

CD A RF .ranscei*er

1.!.2 G& RF transcei*er circuit G& PA inheritance RF selector s'itch inside. After R.R-20%A usin" G& RF transcei*er chip.

1.$ peripheral circuits 1.$.1 Display circuit dia"ram:

Circuit theory analysis: C001! is optional ;CD .F. $.% inches: dot number 0%$ = $07: usin" the IPI interface. C001! ;CD interface products usin" IPI: Dust usin" t'o pairs of differential si"nal lines: a pair of po'er lines: support -7,J refresh rate. Aith frame synchroniJation: use GPI5C71/ of DPC3&FBC synchroniJation si"nals as data transmission: to a*oid split9screen phenomenon. Failure analysis process: &ymptom: Fou can boot but no display ;CD &olution: Chec2 the ;CD

Bo ;CD display Reload soft'are Bo normalE B Ahether the bac2li"htE B Chec2 the ;1!7!: (1!7!

+nd

F (1-71 'hether Aeldin" "oodE B Re9'elded

F Chec2 the connectors K1!72 'hether 'eldin" Good contactE B Rest K1!72

Depot Repair ?Bo ;CD display repair process@ .his section schematics si"nal summary: &i"nal Bame 3R+GC;12C2P0% 3R+GC&! IPICD&IC;AB+2CP IPICD&IC;AB+2CB IPICD&IC;AB+1CP IPICD&IC;AB+1CP ;CDCR&. 1.0 DPC3&FBCCP ;CDCID7 ;CDCID1 IPICD&ICC;4CP IPICD&ICC;4CB Function Details test reference *alue or 'a*eform chart ;CD analo" *olta"e: 2.0% I < 5 port di"ital *olta"e 1.0 differential si"nal 6 1.0 differential si"nal 9 1.0 differential si"nal 6 1.0 differential si"nal 9 1.0 ;CD po'er9on reset si"nal is 1.0 lon"itudinal frame synchroniJation si"nal *endor ID information 1.0 *endor ID information 1.0 cloc2 differential si"nal 6 1.0 differential cloc2 si"nals 9 1.0

1.$.2 3ibration circuit dia"ram:

Circuit theory analysis: P 0721 pin 3I)CDR3CB as a dri*e pin *ibrator motor is placed on the motherboard. Ahen the motor of appetite: 3P,CPAR and 3I)CDR3CB are hi"h. failure analysis process: &ymptom: otor appetite .reatment:

No vibration motor Reload software After normal? Y End

N Check whether the motor Weld? Y N Measure whether motor-powered Normal? N Whether extremely low? Y Check the power Replace the motor if Normal? N Depot Repair
?Bo *ibration repair process@

After verification welding ends

Vibration test negative

End

.his section schematics si"nal summary: &i"nal Bame Function Details 3P,CPAR main po'er supply to the motor 'here foot motor dri*e si"nal: then no motor

test reference *alue or 'a*eform chart

no

3I)CDR3CB

ne"ati*e

1.$.! Recei*er and &P4 &P4 circuit dia"ram:

C001! offers three audio outputs: 1. Recei*er output. .he output si"nal from the CP(. 2. &pea2er output. After the P 0721 amplifier output to &pea2er. ! headphone output: C001! dual channel headphone desi"n. &i"nal Bame +AR1CA PC1C5P +AR1CA PC1C5B &P4C5(.C;CP &P4C5(.C;C Function Details test reference *alue or 'a*eform chart output to the recei*er 'ithout output to the recei*er 'ithout after P 0721 amplifier output to the &P+A4+R Bone after P 0721 amplifier output to the &P+A4+R Bone

Failure analysis process: &ymptom: After creatin" a call by sayin" no. .reatment: After the call is established: then no subDect Reload soft'are After normalE B Chec2 the earpiece *olume settin"s &et normalE

+nd

AdDust the *olume to see if normal

F 3ie' recei*er e*en ;ine is normalE F Are misDud"ment headphones InsertE B Replace the recei*er is Bo normalE B Chec2 the (271 peripheral le*el Are Aeld Road de*iationE B Depot Repair B Re9'elded connections

5*erhaul headphone connector

+BD

+BD

1.$.$ microphone circuit dia"ram: aster i2e:

Circuit theory analysis: C001! board has only one microphone: usin" ,&+DC IC)IA& ?,eadphone IC P 0721 ,&+DC)IA&1@:: & C IC)IA& ? IC /22/A ICC)IA&@ po'er supply. Failure analysis process: &ymptom: Bo transmitter failure .reatment: After the call is established: no microphone Reload soft'are After normalE F +BD B Re9'eldin" IC .o see 'hether it is normalE B Chec2 the electrical IC)IA& Ahether the pressure is normalE F Replace the IC 'hether BormalE B Depot Repair B Chec2 the C%7/

+BD

+BD

.his section schematics si"nal summary: &i"nal Bame Function Details IC1CP main mic input IC1CB main mic input & C IC)IA& aster i2e bias *olta"e 1.$.% headphones circuit dia"ram:

test reference *alue or 'a*eform chart 'ithout 'ithout 'ithout

Circuit theory analysis: ,eadphones into the detection by ,&CD+.+C.CB ?GPI5C70-@ pin Dud"ment: Ahen headphones are plu""ed in before: ,&CD+.+C.CB is pulled into a hi"h le*el 3R+GC&!> Ahen the headphones are plu""ed in: ,&CD+.+C.CB is pulled lo': a lo' le*el. ,eadphone IC po'er supply uses ICC)IA&1 ?P 0721 < ,&+DC)IA&1@ po'er: and used the headset to ans'er detection. Failure analysis process: &ymptom: Bo sound headphones .reatment: Replace the headset: replace the headphone Dac2.

After the establishment of the call: the headset ,ear the sound of the call Chec2 the earpiece *olume settin"s &et normalE B F Replacin" normal headphones BormalE B Plu" in your headphones ,&CD+.+C. 'hether 3olta"e chan"eE F Depot Repair .his section schematics si"nal summary: &i"nal Bame F CAB. ,P,C5(.C; ,P,C5(.CR ,&+DC IC)IA& IC2CP IC2CB ,&+DCADCCD+. ,&CD+.+C. GBDC IC! 1.$.- &I card circuit dia"ram: Function Details F antenna stereo headphone output stereo headphone output headset IC bias headphones headphones headset IC detect headphones into the detection headset IC to test reference *alue or 'a*eform chart 'ithout 'ithout 'ithout *olta"e si"nal 'ithout IC input 'ithout IC input *olta"e chan"es *olta"e chan"e no

Re9set the *olume

+nd

Replace the headset seat

Circuit theory analysis: C001! &I card on the soft board: connected throu"h the motherboard connector interface pro*ides si"nal input and output is controlled by the P 0721. failure analysis process: &ymptom: (I card is not reco"niJed &olution: First chec2 the (I dec2 is normal:

Do not read the (I

card F end

Replace the (I card After normalE N Chec2 the (I card (I card F Chec2 3DDC&I E BormalE F Deboot repare B B

Aeldin" or replacement )loc2 is normalE

Chec2 3DDC&I

.his section schematics si"nal summary: After le*el con*ersion by P 0721 for the PP pins to communicate 'ith the &I card. 3R+GC;1-C(I 1 *olta"e can be set to 1.% P !.7%3. (&I interface "eneral operatin" le*el of 1.03 or !.73. .he follo'in" table (&I & le*el for the P 0721Rs con*ersion interface: and the interface si"nals ;e*el
VREG_S3

UIM1_MSM_CLK UIM1_MSM_DATA

(&I card and interface si"nals le*el UIM1_RESET VREG_L16_UIM1 UIM1_CLK configured by s.ware UIM1_DATA card number: so the increase .3& tube: pro*idin" static

Bote: Due to the number of user actions &I and sur"e protection. 1.$./ I5 Interface circuit dia"ram:

Circuit theory analysis: I5 interface to connect the char"er 'hen the char"er pro*ided 3C,G char"in" *olta"e for battery char"in"> Ahen connectin" cable: (&)C,&CDB and (&)C,&CDP phone for communications and computer ?for soft'are up"rades: read the phone information: etc.@. Failure analysis process: &ymptom: not char"in": I < 5 interfaces no'here .reatment: Clean: plus 'eldin" or replacement interfaces .his section schematics si"nal summary: &i"nal Bame 3C,G (&)CD (&)CDP 1.$.0 &D Card Interface Circuit dia"ram: Function Details char"in" hi"h po'er di"ital si"nal di"ital si"nal test reference *alue or 'a*eform chart input: %3 'ithout 'ithout

Circuit theory analysis: Plus (1$72 for +&D and + I filterin".

Failure analysis process: &ymptom: does not 2no' the card: no card reader .reatment: Do not read icro9&D card F Do not read icro9 &D card

After replacin" the card is BormalE B (1$72 both sides of the si"nal Are conductionE F (pdate soft'are *erification is Bo normalE B Deboot repare 1.$.1 F 6 ). circuit dia"ram:

Re9'eldin" (1$72

+BD

). F Principle Analysis: C001!Rs desi"n: usin" ).: F achie*ed.

combo modules to achie*e its function: usin" 8ualcommRs ACB22$!

In this desi"n as a separate ). antenna: F antenna to the headphone left and ri"ht channels. & 0-2% pro*ides PC and (AR. interfaces directly connected 'ith the PC : (AR. si"nal ). module interface si"nals "i*en Defined as follo's: & 0-2%A GPI5C$$ GPI5C$! GPI5C$GPI5C$% GPI5C-1 GPI5C-0 GPI5C/7 GPI5C/1 GPI5C17/ GPI5C0! si"nal line (AR.1CC.&CB (AR.1CRFRCB (AR.1C.H (AR.1CRH A(HCPC CDIB A(HCPC CD5(. A(HCPC C&FBC A(HCPC CC;4 & CAA4+&C). ).CAA4+&C & definitions sent to the sla*e masterRs ready to recei*e from the machine to the host issued clear to send send si"nals recei*ed si"nal PC input PC output PC synchroniJation PC cloc2 'a2e up the host a2e ).

P 0721 pro*ides audio input interface: directly connected 'ith the left and ri"ht channel si"nals F module interface si"nals are defined as follo's:

WCN2243 FM_RXP FM_RXN FM_VDD2P5 FM_AOUT1 FM_AOUT2

network FM_ANT -----SR_AVDD2P5 FM_OUT_L FM_OUT_R PM8029

MSM8625

Description FM antenna (headset)

PM8029 LINE_IN_LP

FM OUTPUT

LINE_IN_RM

FM OUTPUT

Failure analysis process: Symptom: FM does not work Treatment: If you can find a signal, but no sound, check the headset pathway.

No Signal FM FM silent FM station search result is not satisfactory After replacing the normal headphones Normal? Y N Check the seat re-welding headphones After normal? N After updating the software is Normal? N Deboot repare Chapter 17 of the PC) and )GA chip solder indication map Red (R: 255, G: 0, B: 0): Empty Point

end

end

end

Green (R: 0, G: 255, B: 0):

ground

Blue (R: 0, G: 0, B: 255):

solder

TOP

BOTTOM

U201

U401

U1800

U3901

U901

U1402

U6301

U6100

U6000:

U1205

U1002