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Design of 8: 1 Multiplexer Using When-Else Concurrent Statement (Data Flow Modeling Style)

The document describes a VHDL code for an 8:1 multiplexer that uses a when-else statement. The code defines an entity with 8 input bits, 3 select bits, and 1 output bit. The architecture uses a when-else statement to assign the output to one of the 8 input bits based on the value of the 3-bit select signal.

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dineshvhaval
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131 views2 pages

Design of 8: 1 Multiplexer Using When-Else Concurrent Statement (Data Flow Modeling Style)

The document describes a VHDL code for an 8:1 multiplexer that uses a when-else statement. The code defines an entity with 8 input bits, 3 select bits, and 1 output bit. The architecture uses a when-else statement to assign the output to one of the 8 input bits based on the value of the 3-bit select signal.

Uploaded by

dineshvhaval
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Design of 8 : 1 Multiplexer Using When-Else Statement (VHDL Code).

11:30
naresh.dobal
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Design of 8 : 1 Multiplexer Using When-Else


Concurrent Statement (Data Flow Modeling Style)-

Output Waveform : 8 : 1 Multiplexer

VHDL Code--------------------------------------------------------------------------------- Title


: multiplexer8_1
-- Design
: vhdl_test
-- Author
: Naresh Singh Dobal
-- Company : nsd
---------------------------------------------------------------------------------- File
: 8 : 1 multiplexer using when else.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity multiplexer8_1 is
port(
din : in STD_LOGIC_VECTOR(7 downto 0);
sel : in STD_LOGIC_VECTOR(2 downto 0);
dout : out STD_LOGIC
);
end multiplexer8_1;
architecture multiplexer8_1_arc of multiplexer8_1 is
begin
dout <= din(7) when (sel="000") else
din(6) when (sel="001") else
din(5) when (sel="010") else
din(4) when (sel="011") else
din(3) when (sel="100") else
din(2) when (sel="101") else
din(1) when (sel="110") else
din(0);
end multiplexer8_1_arc;
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