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IES Electrical Engineering Topic wise Questions Microprocessor

YEAR 2008 MCQ 1

Three devices P, Q and R have to be connected to an 8085 microprocessor. Device P has the highest priority and device R has the lowest priority. L 1 this context, which of the following is the correct assignment of interrupt inputs ? (A) P uses TRAP, Q uses RST 5.5 and R uses RST 6.5 (B) P uses RST 5.5, Q uses RST 6.5 and R uses RST 7.5 (C) P uses RST 7.5, Q uses RST 6.5 and R uses RST 5.5 (D) P uses RST 5.5, Q uses RST 6.5 and R uses TRAP
MCQ 2

The content of the Program Counter of an intel 8085 A microprocessor specifies which one of the following ? (A) The address of the instruction being executed (B) The address of the instruction executed earlier (C) The address of the next instruction to be executed (D) The number of instructions executed so far
MCQ 3

Both the ALU and control section of CPU employ which special purpose storage locations ? (A) Buffers

IES EE Topic wise 2001-2008 Microprocessor

www.gatehelp.com (B) Decoders (C) Accumulators (D) Registers

In an Intel 8085 A, what is the content of the Instruction Register (IR) ? (A) Op-code for the instruction being executed (B) Operand for the instruction being executed (C) Op-code for the instruction to be executed next (D) Operand for the instruction to be executed next
MCQ 5

In an Intel 8085 A microprocessor, why is READY signal used ? (A) To indicate to user that the microprocessor is working and is ready for use (B) To provide proper WAIT states when the microprocessor is communicating with a slow peripheral device (C) To slow down a fast peripheral device so as to communicate at the microprocessors device (D) None of the above
MCQ 6

In an Intel 8085 A, which is always the first machine cycle of an instruction ? (A) An op-code fetch cycle (B) A memory read cycle (C) A memory write cycle (D) An I/O read cycle
MCQ 7

The addressing mode used in the instruction JMP F 347 H in case of an Intel 8085 A microprocessor is which one of the following ? (A) Direct (B) Register-indirect
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www.gatehelp.com (C) Implicit (D) Immediate

IES EE Topic wise 2001-2008 Microprocessor

What is the number of machine cycles in the instruction LDA 2000 H that consists of thirteen states ? (A) 2 (B) 3 (C) 4 (D) 5
MCQ 9

Match List I (Feature of instruction) with List II (Instruction) and select the correct answer using the code given below the lists : List I A. Maskable interrupt B. Signal C. Instruction D. Memory location 002C H Codes : A (A) (B) (C) (D) 4 2 4 2 B 1 3 3 1 C 2 4 2 4 D 3 1 1 3 List II 1. RST 5.5 2. XTHL 3. SID 4. RST 6.5

MCQ 10

An intel 8085 A microprocessor is operated at a frequency of 2 MHz. If the instruction LXI H, E000 H that takes ten T states, is executed, then what is the instruction cycle time ? (A) 10 s (B) 5 s (C) 4 s
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IES EE Topic wise 2001-2008 Microprocessor

www.gatehelp.com (D) 2.5 s

When TRAP interrupt is triggered in an intel 8085 A, the program control is transferred to which one of the following ? (A) 0020 H (B) 0024 H (C) 0028 H (D) 002C H
MCQ 12

The stack pointer of an 8085 A microprocessor contains ABCD H. PUSH XTHL PUSH JMP D EC 75 H PSW

At the end of the execution of the above instructions, what would be the content of the stack pointer ? (A) ABCD H (B) ABCA H (C) ABC9 H (D) ABC8 H
MCQ 13

If the HLT instruction of an Intel 8085 A microprocessor is executed (A) the microprocessor is disconnected from the system bus till the RESET is pressed (B) the microprocessor halts the execution of the program and returns to the monitor (C) the microprocessor enters into a HALT state and the buses are tri-stated (D) the microprocessor reloads the program counter from the locations 0024 H and 0025 H
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MCQ 14

IES EE Topic wise 2001-2008 Microprocessor

The contents of Program Counter (PC), when the microprocessor is reading from 2FFF H memory location, will be (A) 2FFE H (B) 2FFF H (C) 3000 H (D) 3001 H
MCQ 15

Carry flag is not affected after the execution of (A) ADD B (B) SBB B (C) INR B (D) ORA B
MCQ 16

Which one is the indirect addressing mode in the following instructions ? (A) LXIH 2050 H (B) MOV A, B (C) LDAX B (D) LDA 2050 H
MCQ 17

An 8254 programmable interval timer consists of independent 16-bit programmable counters. This number is (A) 2 (B) 3 (C) 4 (D) 5
MCQ 18

Assertion (A) : Each memory cell of a DRAM requires refreshing every 2, 4 or 8 ms or its data will be lost.
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www.gatehelp.com Reason (R) : DRAM stores 1s and 0s as charges on a small MOS capacitor which has tendency to leak off charges after a period of time. (A) Both A and R are true and R is the correct explanation of A (B) Both A and R are true but R is not the correct explanation of A (C) A is true but R is false (D) A is false but R is true

YEAR 2007 MCQ 19

If 8255 A chip is selected when A 2 to A 7 bits are all 1, what is the address of port A ? (A) 80 (B) F A (C) F B (D) F C
MCQ 20

If 8255 A chip is selected when A 2 to A 7 pins are 1, what is the address of Port C ? (A) F C (B) F D (C) F B (D) F E
MCQ 21

The power failure alarm must be connected to which one of the following interrupt of 8085 ? (A) RST 7.5 (B) TRAP (C) INTR (D) HOLD
MCQ 22
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www.gatehelp.com The cycle required to fetch and execute an instruction in a 8085 microprocessor is which one of the following ? (A) Clock cycle (B) Memory cycle (C) Machine cycle (D) Instruction cycle
MCQ 23

IES EE Topic wise 2001-2008 Microprocessor

Which one of the following statements corresponding to execution of SIM instructions is not correct ? (A) It will selectively mark all the interrupts of 8085 (B) Contents of bit (b 7) are copies on SOD pin only if bit b 6 in acc is 1 (C) RST 7.5 can reset without executing ISR for RST 7.5 (D) It can handle interrupts and serial I/O
MCQ 24

What are the sets of commands in a program which are not translated into machine instructions during assembly process, called ? (A) Mnemonics (B) Directives (C) Identifiers (D) Operands
MCQ 25

On execution of the following segment of instructions in sequence MVI A, 91H XRI 91H Which one of the following is correct ? (A) Content of accumulator is 00H. Carry, Auxiliary Carry and Zero flag set to 0, 1 and 0, respectively (B) Content of accumulator is 91H. Carry Auxiliary Carry and Zero flag set to 0, 0 and 1, respectively (C) Content of accumulator is 00H. Carry, Auxiliary Carry and Zero flag set to 0, 0 and 1 respectively
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IES EE Topic wise 2001-2008 Microprocessor

www.gatehelp.com (D) Content of accumulator is 91H. Carry Auxiliary Carry and Zero flat set to 0, 1 and 0 respectively
MCQ 26

Read the following Assembly Language Program Segment of 8085 Microprocessor : LXI MOV ORI MOV MOV ANI MOV HLT What are the contents of A, H and L registers after executing the above set of instructions in sequence ? (A) Contents of A, H and L registers are 25, 20 and F1, respectively (B) Contents of A, H and L registers are 05, 25 and 01, respectively (C) Contents of A, H and L registers are 10, 10 and F1, respectively (D) Contents of A, H and L registers are 25, 05 and 01, respectively
MCQ 27

H, 2501 H A, L FOH L, A A, H FOH H, A

Read the following Assembly Language Program Segment of 8085 : EI RIM ANI 80 H SIM What kind of task is performed by above set of instructions ? (A) Sends bit out on SOD pin (B) Accepts bit in from SID pin (C) Accepts RST 7.5 interrupt (D) Resets RST 7.5 interrupt
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MCQ 28

IES EE Topic wise 2001-2008 Microprocessor

Which one of the following statements does not describe property/ characteristic of a stack pointer-register in 8085 microprocessor ? (A) It points to top of the stack (B) It is UP/DOWN counter (C) It is automatically initialized to 0000H on power-on (D) It is a 16-bit register
MCQ 29

Eight memory chips of 32 # 4 bit size have their address buses connected together. What is the size of this memory system ? (A) 512 # 2 bits (B) 256 # 4 bits (C) 64 # 16 bits (D) 32 # 32 bits
MCQ 30

Assertion (A) : A subroutine is a program written separately from the main program to perform a function that occurs repeatedly in the main program. Reason (R) : A subroutine can be called by a CALL instruction. (A) Both A and R are true and R is the correct explanation of A (B) Both A and R are true but R is not the correct explanation of A (C) A is true but R is false (D) A is false but R is true
MCQ 31

Assertion (A) : Analog to digital converters are used to interface microprocessor to analog signals. Reason (R) : Many applications in real word produce signal analog in nature. (A) Both A and R are true and R is the correct explanation of A (B) Both A and R are true but R is not the correct explanation of A (C) A is true but R is false (D) A is false but R is true
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MCQ 32

Consider the following statements : 1. The process of entering data is called burning in ROM. 2. 3. ROMs are volatile memories. ROMs are used in C security systems.

What of the statements given above are correct ? (A) 1, 2 and 3 (B) 1 and 2 (C) 2 and 3 (D) 1 and 3
MCQ 33

Which interrupt has the highest priority ? (A) RST 7.5 (B) RST 7 (C) RST 6.5 (D) INTR
MCQ 34

The contents of memory location 4 FFFH are 11011011. The memory word could not be interpreted as which one of the following ? (A) 2s complement number (B) 1s complement number (C) Octal number (D) BCD number
MCQ 35

Which interrupt has the highest priority ? (A) RST 7.5 (B) RST 7 (C) RST 6.5 (D) INTR

YEAR 2006
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MCQ 36

IES EE Topic wise 2001-2008 Microprocessor

Consider the following statements : 1. 2. 3. 4. Indirect addressing is not possible for I/O mapped I/O port addresses Pointers cannot be used to access memory mapped I/O addresses Fewer machine instructions can be used with I/O mapped I/O addressing as compared to memory mapped I/O addressing. With an 8085 microprocessor, one can access at the most 512 devices with unique addresses using I/O mapped I/O addressing

Which of the statements given above are correct ? (A) 1, 2 and 3 (B) 2 and 4 (C) 3 and 4 (D) 1 and 3
MCQ 37

Which one of the following instructions is a 3-byte instruction ? (A) M V I A (B) L D A X B (C) J M P 2050 (D) MOV A, M
MCQ 38

Match List I (Interrupt) with List II (Property) and select the correct answer using the code given below the lists : List I A. RST 7.5 B. RST 5.5 C. INTR D. TRAP Codes : A (A) 1 B 3 C 4 D 2
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List II 1. Non-maskable 2. Edge sensitive 3. Level sensitive 4. Non-vectored

IES EE Topic wise 2001-2008 Microprocessor

www.gatehelp.com (B) (C) (D) 2 1 2 4 4 3 3 3 4 1 2 1

MCQ 39

The contents of memory locations 2000 H, 2001 H and 2002 H are AAH, BBH are CCH respectively. What are the contents of H and L registers after executing the following instructions in sequence ? LXI LHLD H, 2001 H 2001 H

Select the correct answer using the codes given below : (A) Contents of H and L registers are 20 H and 01 H, respectively (B) Contents of H and L registers are AAH and BBH, respectively (C) Contents of H and L registers are BBH and CCH, respectively (D) Contents of H and L registers are CCH and BBH, respectively
MCQ 40

How many times will the following loop be executed ? LXIB LOOP DCX MOV ORA JNZ (A) 10 (B) 100 (C) 16 (D) 15
MCQ 41

0010 H B A, B C LOOP

Select the correct answer using the code given below :

In 8085, the DDA instruction is used for (A) Direct Address Accumulator (B) Double Add Accumulator
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www.gatehelp.com (C) Decimal Adjust Accumulator (D) Direct Access Accumulator

IES EE Topic wise 2001-2008 Microprocessor

Programme status ward of 8085 microprocessor has five flags. Which are these five flags ? (A) S, Z, AC, P, CY (B) S, OV, AC, P, CY (C) S, Z, OV, P, CY (D) S, Z, AC, P, OV
MCQ 43

Suppose 64 kB, ROM ICs are available in abundance. 1 MB ROM can be obtained from (A) 16 ICs in a row (B) 16 ICs in a column (C) 8 ICs in a column and 2 ICs in a row (D) None of the above
MCQ 44

Which one of the following is the software intercept of 8085 microprocessor ? (A) RST 7.5 (B) RST 7 (C) TRAP (D) INTR Direction : The following item consist of two statements, one labelled as Assertion A and the other labelled as Reason R. You are to examine these two statements carefully and decide if the Assertion A and the Reason R are individually true and if so, whether the Reason is a correct explanation of the Assertion. Select your answers to these items using the codes given below. Codes : (A) Both A and R are true R is the correct explanation of A (B) Both A and R are true but R is NOT the correct explanation of
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IES EE Topic wise 2001-2008 Microprocessor

www.gatehelp.com A (C) A is true but R is false (D) A is false but R is true

Assertion (A) : Stack is a group of memory locations in RAM used for temporary storage of data Reason (R) : PUSH and POP instructions are used to send and retrieve data from stack.
YEAR 2005 MCQ 46

Match List I with List II and select the correct answer using the correct codes given below the lists : List I A. Modified during fetch phase B. Holds subscripts of array C. Needed by the DEBUG program D. Calculates addresses of data in data-segment Codes : A (A) (B) (C) (D) 2 3 2 3 B 4 1 1 4 C 1 4 4 1 D 3 2 3 2 List II 1. DI 2. DS 3. IP 4. TF

MCQ 47

Consider the following statements about register indirect addressing : 1. 2. 3. 4.

It helps in writing code that executes faster It helps in writing compact code It allows reuse of memory CPU data transfer instruction It is essential for stack operations

www.gatehelp.com Which of the statements given above are correct ? (A) 1, 3 and 4 (B) 1, 2 and 4 (C) 2, 3 and 4 (D) 1, 2 and 3
MCQ 48

IES EE Topic wise 2001-2008 Microprocessor

Which of the following does not take place when 8085 processor is reset ? (A) 8085 gives reset out signal to reset external hardware (B) 8085 resets program counter to FFFFH (C) The interrupt system is disabled (D) The busses are tristated
MCQ 49

Memory chips of four different sizes as below are available : 1. 32 k # 4 2. 3. 4. 32 k # 16 8k#8 16 k # 4

All the memory chips as mentioned in the above list are Read/Write memory. What minimal combination of chips or chip alone can map full address space of 8085 microprocessor ? (A) 1 and 2 (B) 1 only (C) 2 only (D) 4 only
MCQ 50

A good assembly language programmer should use general purpose registers rather than memory in maximum possible ways for data processing. This is because : (A) Data processing with registers is easier than with memory (B) Data processing with memory requires more instructions in the program than that with registers
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IES EE Topic wise 2001-2008 Microprocessor

www.gatehelp.com (C) Of limited set of instructions for data processing with memory (D) Data processing with registers takes fewer cycles than that with memory
MCQ 51

Consider the following 8085 instructions : ANA A, ORA A, XRA A, SUB A, CMP A. Now, consider the following statements : 1. 2. 3. 4. All are arithmetic and logic instructions All cause the accumulator to be cleared irrespective of its original contents All reset the carry flag All of them are 1-byte instructions

Which of the statements given above is/are correct ? (A) 1, 2, 3 and 4 (B) 2 only (C) 1, 2 and 4 (D) 1, 3 and 4
MCQ 52

INR instruction of 8085 does not affect carry flag. Which of the following is correct about INR instruction ? (A) Overflow cannot be detected (B) Overflow can be detected (C) If a programme requires overflow to be detected, ADD instruction should be used instead of INR (D) It can be used to increase the contents of the BC register pair.
MCQ 53

Which of the following is not correct ? (A) Bus is a group of wires (B) Bootstrap is a technique or device for loading first instruction (C) An instruction is a set of bits that defines a computer operation (D) An interrupt signal is required at the start of every program
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MCQ 54

IES EE Topic wise 2001-2008 Microprocessor

The interrupt vector table IVT of 8086 contains (A) The contents of CS and IP of the main program address to which the interrupt has occured (B) The contents of CS and IP of the main program address to which the control has to come back after the service routine (C) The starting CS and IP values of the interrupt service routine (D) The staring address of the IVT
MCQ 55

Consider the following statements : 1. 2. 3. 4. A total of about one million bytes can be directly addressed by the 8086 microprocessor 8086 has thirteen 16-bit registers 8086 has eight flags Compared to 8086, the 80286 provides a higher degree of memory protection.

Which one of the statements given above are correct ? (A) 2, 3 and 4 (B) 1, 3 and 4 (C) 1, 2 and 4 (D) 1, 2 and 3
MCQ 56

The following sequences of instructions are executed by an 8085 microprocessor : 1000 LXI SP, 27FF 1003 CALL 1006 1006 POPH What are the contents of the stack pointer (SP) and the HL register pair on completion of execution of these instruction ? (A) SP = 27 FF, HL = 1003 (B) SP = 27 FD, HL = 1003 (C) SP = 27 FF, HL = 1006
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www.gatehelp.com (D) SP = 27 FD, HL = 1006

Consider the program given below, which transfer a block of data from one place in memory to another : MVI LXI LXI L1 : MOV STAX INR INR DCR JNZ C, 0B H H, 2400 H D, 3400 H A, M D L E C L1

What is the total number of memory accesses (including instruction fetches) carried out (A) 118 (B) 140 (C) 98 (D) 108
MCQ 58

When an 8086 executes an INT type instruction, it : (A) Resets both IF and TF flags (B) Resets all flags (C) Sets both IF and TF (D) Resets the CF and TF
MCQ 59

Consider the following statements : In memories, 1. ROMs are used for temporary program and data storage 2. 3.
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Dynamic RAM is less expensive than static RAM MASK ROM is used in high volume microprocessor based system

www.gatehelp.com Which of the statements given above is/are correct (A) 1 only (B) 1 and 2 (C) 2 and 3 (D) 1, 2 and 3

IES EE Topic wise 2001-2008 Microprocessor

YEAR 2004 MCQ 60

Which one of the following statements is correct ? In Intel 8085, the interrupt enable flip-flop is reset by (A) DI instructions only (B) System RESET only (C) Interrupt acknowledgement only (D) Either DI or system RESET or interrupt acknowledgement
MCQ 61

Match List I (Instruction) with List II (Operation) for Intel 8085 and select the correct answer using the codes given below : List I A. PCHL B. SPHL C. XTHL D. XCHG Codes : A (A) (B) (C) (D) 3 3 4 4 B 4 4 3 3 C 1 2 2 1 D 2 1 1 2
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List II 1. Exchange the top of the stack with the contents of HL pair 2. Exchange the contents of HL with those of DE pair 3. Transfer the contents of HL to the stack pointer 4. Transfer the contents of HL to the programme counter

IES EE Topic wise 2001-2008 Microprocessor

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MCQ 62

Match List I (Instruction) with the List II (Application) and select the correct answer using the codes given below : List I A. SIM B. DAD C. DAA D. SPHL List II 1. 16-bit addition 2. Initializing the stack pointer 3. Serial output data 4. Checking the current interrupt mask setting 5. BCD addition Codes : A (A) (B) (C) (D) 5 3 5 3 B 4 1 1 4 C 2 5 2 5 D 1 2 4 1

MCQ 63

Which one of the following statements is correct ? (A) ROM is a Read/Write Memory (B) PC points to the last instruction that was executed (C) Stack works on the principle of LIFO (D) All instructions affect the flags
MCQ 64

What must be the contents of the control word of Intel 8255 for Mode 0 (operation) and for the following ports configuration : Port A-output, Port B-output, Port C lower -Output, Port C upper -input ? (A) 85 H (B) 86 H (C) 87 H (D) 88 H
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MCQ 65

IES EE Topic wise 2001-2008 Microprocessor

Which one of the following 8085 assembly language instructions does not affect the contents of the accumulator ? (A) CMA (B) CMPB (C) DAA (D) ADDB
MCQ 66

MC 1488 and MC 1489 are needed when using RS 232 for which one of the following ? (A) To convert the logical levels at the receiving and sending ends of RS 232 into TTL compatible levels (B) To convert the TTL level voltage at the sending and receiving ends of RS 232 to ! 12 V level (C) They are not required while using RS 232 (D) To improve the current drive of the RS 232 output signals
MCQ 67

Which one of the following statements for Intel 8085 is correct ? (A) Program counter (PC) specifies the address of the instruction last executed (B) PC specifies the address of the instruction being executed (C) PC specifies the address of the instruction to be executed (D) PC specifies the number of instructions executed so far
MCQ 68

Match List I (Interrupts) with List II (Corresponding Characteristics) and select the correct answer using the codes given below : List I A. TRAP B. INTR C. RST 7.5 D. RST 6.5 List II 1. Level triggered 2. Non maskable 3. For increasing the number of interrupts 4. Positive edge triggered
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IES EE Topic wise 2001-2008 Microprocessor

www.gatehelp.com Codes : A (A) (B) (C) (D) 2 1 1 2 B 4 4 3 3 C 3 3 4 4 D 1 2 2 1

MCQ 69

What is the total number of memory locations and input-output devices that can be addressed with a processor having 16-bits address bus, using memory maped I/O ? (A) 64 K memory locations and 256 I/O devices (B) 256 I/O devices and 65279 memory locations (C) 64 K memory locations and no I/O devices (D) 64 K memory locations or input-output devices
MCQ 70

For Intel 8085, match List I (Addressing Mode) with List II (Instruction) and select the correct answer using the codes given below : List I A. Implicit addressing B. Register-Indirect C. Immediate D. Direct addressing Codes : A (A) (B) (C) (D) 4 4 3 3 B 1 2 2 1 C 2 1 1 2 D 3 3 4 4 List II 1. JMP 3 FAO H 2. MOV A, M 3. LDA 03 FC H 4. RAL

MCQ 71
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www.gatehelp.com A memory system of 64 kbytes needs to be designed with RAM chips of 1 kbyte each, and a decoder tree constructed with 2:4 decoder chips with Enable input. What is the total number of decoder chips ? (A) 21 (B) 64 (C) 32 (D) 25
MCQ 72

IES EE Topic wise 2001-2008 Microprocessor

Match List I with List II and select the correct answer using the codes given below the lists : List I A. Monitor program B. Assembler C. Mnemonic D. Program counter Codes : A (A) (B) (C) (D) 4 4 3 3 B 3 3 4 4 C 2 1 1 2 D 1 2 2 1 List II 1. Used to indicate memory location 2. A combination of letters, symbols and numerals 3. A program that translates symbolic instructions into binary equivalent 4. An operating system

YEAR 2003 MCQ 73

A Direct Memory Access (DMA) transfer implies (A) Direct transfer of data between memory and accumulator (B) Direct transfer of data between memory and I/O devices without the use of microprocessor (C) Transfer of data exclusively within microprocessor registers (D) A fast transfer of data between microprocessor and I/O devices
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MCQ 74

After an arithmetic operation, the flag register of a 8085 microprocessor has the following look : D7 1 D6 0 D5 X D4 1 D3 X D2 0 D1 X D0 1

The arithmetic operation has resulted in (A) A carry and an odd parity number having 1 as the MSB (B) Zero and the auxiliary carry flag being set (C) A number with even parity and 1 as the MSB (D) A number with odd parity and 9 as the MSB
MCQ 75

The program counter in a 8085 microprocessor is a 16-bit register, because (A) It counts 16 bits at time (B) There are 16 address lines (C) It facilitates the user storing 16-bit data temporarily (D) It has to fetch two 8-bit data at a time
MCQ 76

A microprocessor is ALU (A) and control unit on a single chip (B) and memory on a single chip (C) register unit and I/O device on a single chip (D) register unit and control unit on a single chip
MCQ 77

In Intel 8085 a microprocessor ALE signal is made high to (A) Enable the data bus to be used as low order address bus (B) To latch data D 0 D7 from data bus (C) To disable data bus (D) To achieve all the functions listed above
MCQ 78
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www.gatehelp.com Examine the following instruction to be executed by a 8085 microprocessor. The input port has an address of 01H and has a data 05H to input : IN ANI 01 80

IES EE Topic wise 2001-2008 Microprocessor

After execution of the two instructions the following flag portions may occur : 1. 2. 3. 4. Zero flag is set Zero flag is reset Carry flag is cleared Auxiliary carry flag is set

Select the correct answer using the codes given below : (A) 1 and 3 (B) 2, 3 and 4 (C) 1, 3 and 4 (D) 1, 2 and 4
MCQ 79

Match List I (Introduction) with List II (Type of Addressing) and select the correct answer : List I A. MOV A, M B. LXIH, E400H C. LDA F1 CDH D. CMC List II 1. Direct addressing 2. Register addressing 3. Implicit addressing 4. Register indirect addressing 5. Immediate addressing Codes : A (A) (B) (C) (D) 5 4 5 4 B 4 5 4 5 C 1 3 2 1 D 3 1 3 3
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MCQ 80

How many and which types of machine cycles are needed to execute PUSH PSW by an Intel 8085 A microprocessor ? (A) 2, Fetch and Memory write (B) 3, Fetch and 2 Memory write (C) 3, Fetch and 2 Memory read (D) 3, Fetch, Memory read and Memory write
MCQ 81

Output of the assembler in machine codes is referred to as (A) Object program (B) Source program (C) Macroinstruction (D) Symbolic addressing
MCQ 82

Three devices A, B and C are connected to an Intel 8085 A microprocessor. Device A has the highest priority and device C has the lowest priority. The correct assignment of interrupt inputs is (A) A uses RST 5.5, B uses RST 6.5 and C uses TRAP (B) A uses RST 5.5, B uses RST 6.5 and C uses RST 7.5 (C) A uses RST 7.5, B uses RST 6.5 and C uses RST 5.5 (D) A uses TRAP, B uses RST 5.5 and C uses RST 6.5
MCQ 83

If the accumulator of an Intel 8085 A microprocessor contains 37 H and the previous operation has set the carry flag, the instruction ACI 56 H will result in (A) 8E H (B) 94 H (C) 7E H (D) 84 H
MCQ 84

Which one of the following statements about RAM is NOT correct ?

www.gatehelp.com (A) RAM stands for random-access memory (B) It is also called read/write memory (C) When power supply is switched off, the information in RAM is usually lost (D) The binary contents are entered or stored in the RAM chip during the manufacturing state
MCQ 85

IES EE Topic wise 2001-2008 Microprocessor

A handshake signal in a data transfer is transmitted (A) Along with the data bits (B) Before the data transfer (C) After the data transfer (D) Either along with the bits or after the data transfer
MCQ 86

Which one of the following is NOT a vectored interrupted ? (A) TRAP (B) INTR (C) RST 3 (D) RST 7.5
MCQ 87

Ports are used to connect the CPU to which of the following units ? 1. 2. 3. 4. Printer Floppy disk drives Video display unit Incoming power supply

Select the correct answer using the codes given below : (A) 1 and 2 (B) 2 and 3 (C) 3 and 4 (D) 1 and 3 Direction : The following item consist of two statements, one labelled as Assertion A and the other labelled as Reason R. You are to
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IES EE Topic wise 2001-2008 Microprocessor

www.gatehelp.com examine these two statements carefully and decide if the Assertion A and the Reason R are individually true and if so, whether the Reason is a correct explanation of the Assertion. Select your answers to these items using the codes given below. Codes : (A) Both A and R are true and R is the correct explanation of A (B) Both A and R are true but R is NOT the correct explanation of A (C) A is true but R is false (D) A is false but R is true
MCQ 88

Assertion (A) : The zero-flag of a 8085 microprocessor is not affected after the execution of the following couple of instructions : MVI MOV B, 03 A, B

Reason (R) : After the execution of a data transfer instruction, zeroflag is set if the accumulator content is zero.
YEAR 2002 MCQ 89

The number of output pins of a 8085 microprocessor are (A) 40 (B) 27 (C) 21 (D) 19
MCQ 90

Consider the execution of the following instructions by a 8085 microprocessor : LXI H, 01FFH SHLD 2050 H After execution the contents of memory locations 2050 H and 2051 H
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www.gatehelp.com and the registers H and L, will be (A) 2050 H " FF; 2051 H " 01; H " FF; L " 01 (B) 2050 H " 01; 2051 H " FF; H " FF; L " 01 (C) 2050 H " FF; 2051 H " 01; H " 01; L " FF (D) 2050 H " FF; 2051 H " 01; H " 00; L " 00
MCQ 91

IES EE Topic wise 2001-2008 Microprocessor

Which one of the following functions is performed by the 8085 instruction MOV H, C ? (A) Moves the contents of H register to C register (B) Moves the contents of C register to H register (C) Moves the contents of C register to HL pair (D) Moves the contents of HL pair to C register
MCQ 92

For 8085 microprocessor, the instruction RST.6 restarts subroutine at address (A) 00H (B) 03H (C) 30H (D) 33H
MCQ 93

Memory-mapped I/O-scheme for the allocation of address to memories and I/O devices, is used for (A) small systems (B) large systems (C) both large and small systems (D) very large systems
MCQ 94

The interfacing device used for the generator of accurate time delay in a microcomputer system is (A) Intel - 8251 (B) Intel - 8257
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IES EE Topic wise 2001-2008 Microprocessor

www.gatehelp.com (C) Intel - 8253 (D) Intel - 8259

YEAR 2001 MCQ 95

The length of a bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an indeterminate number of wait state clock cycles denoted by TW . The wait states are always inserted between (A) T1 and T2 (B) T2 and T3 (C) T3 and T4 (D) T4 and T1
MCQ 96

When RET instruction is executed by any subroutine then (A) the top of the stack will be popped out and assigned to the PC (B) without any operation, the calling program would resume from instruction immediately following the call instruction (C) the PC will be incremented after the execution of the instruction (D) without any operation, the calling program would resume from instruction immediately following the call instruction, and also the PC will be incremented after the execution of the instruction
MCQ 97

Consider the following set of 8085 instructions used to read a byte of data from the output of an ADC. The byte represents digital equivalent of analog input voltage Vin applied to ADC when RD is asserted. ADC GETADC : EQU IN RET When RET is executed 1. Op-code of IN is fetched 2.
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30H ADC

port address 30H is decoded

www.gatehelp.com 3. 4. Op-code of IN is decoded I/O read operation is performed

IES EE Topic wise 2001-2008 Microprocessor

The correct sequence of these operations is (A) 3, 1, 4, 2 (B) 1, 3, 2, 4 (C) 1, 3, 4, 2 (D) 3, 1, 2, 4

In 8085 microprocessor, a number of the form 000XXXX0 stored in the accumulator is processed by the programme (Assume Cy = 0 ) as follows ANI RAL MOV ANI RAL ANI RAL ADD B FFH B, A FFH FFH

The operation carried out by the programme is (A) multiplication of accumulator content by 10 (B) complement of accumulator content (C) multiplication of accumulator content by 9 (D) rotation of accumulator content three times
MCQ 99

Which one of the following circuits transmits two messages simultaneously in one direction ? (A) Duplex (B) Diplex (C) Simplex (D) Quadruplex
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