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Memory Controller: 1 Members Found This Post Helpful

The document discusses CAS latency for DDR2 SDRAM. It explains that a DDR2 memory with a CAS latency of 4 can work with a memory controller that has a latency of 3, as long as the operating frequency is lower than the nominal frequency. It provides a formula showing that lowering the frequency can accommodate a lower CAS latency. An example is given of a DDR2 operating at a lower speed supporting a CAS latency of 3, even though its nominal speed requires a latency of 4.

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0% found this document useful (0 votes)
14 views1 page

Memory Controller: 1 Members Found This Post Helpful

The document discusses CAS latency for DDR2 SDRAM. It explains that a DDR2 memory with a CAS latency of 4 can work with a memory controller that has a latency of 3, as long as the operating frequency is lower than the nominal frequency. It provides a formula showing that lowering the frequency can accommodate a lower CAS latency. An example is given of a DDR2 operating at a lower speed supporting a CAS latency of 3, even though its nominal speed requires a latency of 4.

Uploaded by

Harish Kumar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Hello all, I have few questions regarding CAS Latency.

For example,if the DDR2 SDRAM consists of a CAS Latency of 4,and if the DDR2 SDRAM memory controller generated using MIG has a latency of 3? Does the design work together? Any help would be appreciated. Thanks.
In present, DDR2 CAS Latency is defined for a nominal data rate (DDRAM working data rate). If your design works with a frequency below maximum data rate your design could work properly for a different (lower) latency. The following formula should be respected: 1/Nominal frequency x CAS Latency (4) >= 1/Working frequency x CAS Latency Example DDR2-1066 with CL = 4 will work with systems with DDR2-667 with CL = 3
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AS Latency is a time. It specify the minimum time between a specific column addressing and data available to output. For synchronous RAM this time is done indirectly by using clock cycles. Look on the same data sheet on the same page exist Table 1. It mention that this chip support different CAS Latency for different data rates. Note that during DDRAM configuration a CAS Latency of 3 in your case should be mentioned (in configuration word).

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