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Fa Structure Modelling

This document contains VHDL code for implementing a full adder using a structural modeling approach. It defines the full adder entity with inputs In1, In2, and c_in and outputs sum and c_out. The architecture instantiates two half adder components and one OR gate component, and maps the inputs and outputs to implement the full adder functionality. It also provides the code for the half adder and OR gate components.

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dineshvhaval
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© Attribution Non-Commercial (BY-NC)
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10 views

Fa Structure Modelling

This document contains VHDL code for implementing a full adder using a structural modeling approach. It defines the full adder entity with inputs In1, In2, and c_in and outputs sum and c_out. The architecture instantiates two half adder components and one OR gate component, and maps the inputs and outputs to implement the full adder functionality. It also provides the code for the half adder and OR gate components.

Uploaded by

dineshvhaval
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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VHDL Code for Full Adder using Structural Modelling


library IEEE; use IEEE.std_logic_1164.all;

entity bejoy_fa is port(In1,In2,c_in : in std_logic; sum, c_out : out std_logic); end bejoy_fa;

architecture arc of bejoy_fa is

component half_adder port(a,b : in std_logic; sum, carry : out std_logic); end component;

component or_2 port(a,b : in std_logic; c : out std_logic); end component;

signal s1, s2, s3 : std_logic;

begin

H1: half_adder port map(a=>In1, b=>In2, sum=>s1, carry=>s3);

H2: half_adder port map(a=>s1, b=>c_in, sum=>sum, carry=>s2);

O1: or_2 port map(a=> s2, b=>s3, c=>c_out);

end arc;

entity half_adder is

port (a,b : in bit ; sum,carry : out bit);

end half_adder;

architecture arc of half_adder is

begin

sum<= a xor b; carry <= a and b;

end arc;

entity or_2 is

port (a,b : in bit ; c : out bit);

end or_2;

architecture arc of or_2 is

begin

c<= a or b;

end arc;

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