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Clo Format1 LD

This document contains the course plan and learning objectives/outcomes for a Logic Design course offered at Smt. Kamala and Sri Venkappa. M. Agadi College of Engineering and Technology. The course is intended to teach students about combinational logic, Boolean algebra, minimization techniques like Karnaugh maps, decoders, encoders, multiplexers, adders, latches, flip-flops, registers, counters, synchronous sequential circuits, state diagrams and hardware implementation. The course objectives are for students to understand and apply these concepts, and the outcomes are for students to demonstrate their knowledge and skills in analyzing and designing various digital circuits.

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Sunil Begumpur
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30 views2 pages

Clo Format1 LD

This document contains the course plan and learning objectives/outcomes for a Logic Design course offered at Smt. Kamala and Sri Venkappa. M. Agadi College of Engineering and Technology. The course is intended to teach students about combinational logic, Boolean algebra, minimization techniques like Karnaugh maps, decoders, encoders, multiplexers, adders, latches, flip-flops, registers, counters, synchronous sequential circuits, state diagrams and hardware implementation. The course objectives are for students to understand and apply these concepts, and the outcomes are for students to demonstrate their knowledge and skills in analyzing and designing various digital circuits.

Uploaded by

Sunil Begumpur
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Smt. Kamala and Sri Venkappa. M. Agadi College of Engineering and Technology., Laxmesh ar!

"#$%%& 'Appro(ed )y A*CTE +elhi and Affiliated to VT, -elga.m/ +epartment of Electronics and Comm.nication Comm.nication

Course Plan Semester : III Year: 2013

Program: Electronics and Communication Engineering Course Title: Logic Design Total Content Hours: 52 E"am $ar%s: 100 Lesson Plan &ut#or: Santos# 'u(ari C#ec%ed ',: Course Code: 10ES33 Duration o !inal E"am: 3 #rs Internal $ar%s: 25 Date: 0)*0+*2013 Date:

Course Learning Objectives-CLO &t t#e end o t#e course student s#ould -e a-le to: 1. State /#at is Logic Design and /#, it is re0uired and to descri-e com-inational logic1 to generate s/itc#ing e0uations rom trut# ta-les1 to sim2li , ma"term and minterm e0uations using 3*ma2s. 2. Practice t#e 4uine*$cClus%, minimi5ation tec#ni0ue1 reduced 2rime im2licant ta-les1 $a2 entered 6aria-les. 3. &nal,5e and design decoders and encoders. 7. &nal,5e and design digital multi2le"ers1 adders1 su-tractors. 5. &nal,5e and design t#e -asic -ista-le element1 latc#es and li2* lo2s. ). Practice c#aracteristic e0uations and design registers and counters. 8. 9ecall $ela, and $oore $odels and design s,nc#ronous se0uential +. Construct State diagrams and design counters.

SKSVMACET!L01

+E2T 34 ECE

Smt. Kamala and Sri Venkappa. M. Agadi College of Engineering and Technology., Laxmesh ar!"#$%%& 'Appro(ed )y A*CTE +elhi and Affiliated to VT, -elga.m/ +epartment of Electronics and Comm.nication Comm.nication

Course Learning Outcomes-CLO &t t#e end o t#e course student s#ould -e a-le to: 1. Students /ill demonstrate %no/ledge o Logic Design and s#o/ /#at com-inational logic is and sim2li , t#e e0uations using 3*ma2s. 2. Students /ill demonstrate s%ills to use 4uine*$cClus%, minimi5ation tec#ni0ue1 9educed 2rime im2licant ta-les and ma2 entered 6aria-les. 3. Students /ill demonstrate s%ills to design decoders1 encoders1 digital multi2le"ers1 adders1 su-tractors. 7. Students /ill demonstrate to use Latc#es1 li2* lo2s. 5. Students /ill demonstrate a-ilit, to design registers and counters. ). Students /ill s#o/ /#, $eal, and $oore $odels and /ill demonstrate t#e s%ills to design S,nc#ronous Se0uential Circuit. 8. Students /ill demonstrate an a-ilit, to construct state diagrams. +. Students /ill demonstrate an a-ilit, to anal,5e s,nt#esis in ormation rom entit, and module and to ma2 2rocess and al/a,s in t#e #ard/are domain.

SKSVMACET!L01

+E2T 34 ECE

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