Acer Aspire 4738G (Quanta ZQ9)

5
VER : 1A
BOM P/N
ZQ9 SYSTEM BLOCK DIAGRAM
Description
Channel B
Arrandale
rPGA 989
Dual Channel DDR III
800/1066 MHZ
DDRIII-SODIMM1
DDRIII-SODIMM2
P22
ATI-Park
EXT_HDMI
VRAM DDRIII
PCI-E x16 512MB
P4, 5, 6, 7
IMC
GFX
EXT_CRT
P14,15
P16, 17, 18, 21, 22, 23
FDI
X'TAL
14.318MHz
SLG8LV595
CLOCK
GENERATOR
64Mb * 16 *4 pc
CRT Con.
P23
EXT_LVDS
DMI
DMI(x4)
FDI
P3
DMI
CLK
INT_CRT
USB-8
INT_LVDS
Int. MIC
LVDS/CCD/MIC
Con.
P23
Display
C
SATA 0
SATA - HDD
P28
INT_HDMI
SATA
PS8101
LS
P24
SATA 1
SATA - ODD
P28
USB
P33
Ibex Peak-M
MINI CARD
WLAN
USB-13
PCH
USB-3/9/11
USB/B Con.
(USB Port x2)
PCIE-1
USB-4
BRM 57780
GIGA LAN P26
X'TAL
32.768KHz
P33
P31
AU6437-GBL
Cardreader control
RJ45
P26
X'TAL
25MHz
Cardreader
P27
P8, 9, 10, 11, 12, 13
P33
Bluetooth Con.
X'TAL 25MHz
USB-12
P31
P9
BATTERY
Azalia
RTC
SPI ROM
SPI
IHDA
P9
LPC
ISL88731A
Batery Charger
LPC
Int. MIC
ALC272X
AUDIO CODEC
NPCE781
EC
P30
X'TAL
32.768KHz
P37
UP6111AQDD
P36
RT8206B
3V/5V
Reference
MIC JACK
IV@
EV@
for Discrete Graphic only SKU
Touch Pad
Board Con.
P29
P30
Description
for UMA only SKU
VRAM@
GMT 1453L amp
P30
K/B Con.
for different VRAM parts
HP
do not stuff
P30
W25X40BVSSIG
SPI FLASH P35
+1.5V_SUS
+VGFX_AXG
P40
+1.8V
+VGPU_CORE
(PWM Type)
P41
HPA00835RTER
MAX8792ETD+T
P38
P43
Discharger
P42
P43
P44
Quanta Computer Inc.

P34
PROJECT : ZQ9
Size
Document Number
Date:
Tuesday, June 22, 2010
Rev
1A
Block Diagram
5
Thermal Protection
P44
Fan Driver
P34
ISL62881HRZ-T
P39
RT9018A
+1V
P34
Speaker
+1.05V
RT8207A
P37
ADP3212
CPU core
BOM Option Table
P24
PCIE-6
PCI-E x1
USB-1
USB Port
HDMI Con.
EXT_HDMI
Sheet
1
of
45
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

+3.3V
VIN
+3V_D
VDDR3
dGPU_VRON
PG_GPUIO_EN
VDDC
MOS (AO3413)
P22
ISL6264
+1.5V
PG_1V_EN
VDDCI
ISL62872
P44
+VGPU_CORE (20A)
+3_D (0.5A)
VIN
+1.5V_SUS
+1V (DP PLL PWR)
PG_1.5V_EN
G9334ADJ & MOS
P45
PG_1.5V_EN
+1V (3A)
+5V
PG_1.5V_EN
VDDR4
MOS (AO4710)
P43
P47
+VGPU_IO (4.5A)
VDDR1
+1.8V
MOS (AO6402)
P43
+1.5V_GPU (10A)
dGPU_PWROK
BJT
dGPU_PWR_EN#
P22
+1.8V_GPU (3A)
MOS
AO3413
P22
+5_GPU
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

VIN
VIN
PG_GPUIO_EN
VDDC
dGPU_VRON
ISL6264
PG_1V_EN
VDDCI
ISL62872
P44
+VGPU_CORE (20A)
+1.5V
+1V (DP PLL PWR)
+1.5V_SUS
PG_1.5V_EN
+VGPU_IO (4.5A)
+1.5V_GPU
VDDR1
G9334ADJ & MOS
P45
+1V (3A)
+1.8V
+3V_D
VDDR3
+1.5V_GPU (10A)
+5V
PG_1.5V_EN
VDDR4
MOS (AO3413)
P22
MOS (AO4710)
P43
P47
MOS (AO6402)
P43
+3_D (0.5A)
dGPU_PWROK
BJT
dGPU_PWR_EN#
P22
+1.8V_GPU (3A)
MOS
AO3413
P22
+5_GPU
Thermal Follow Chart
Power States
+3.3V
POWER PLANE
VOLTAGE
DESCRIPTION
CONTROL
SIGNAL
VIN
+10V~+19V
MAIN POWER
ALWAYS
ALWAYS
+VCCRTC
+3V~+3.3V
RTC POWER
ALWAYS
ALWAYS
+3VPCU
+3.3V
EC POWER
ALWAYS
ALWAYS
+5VPCU
+5V
CHARGE POWER
ALWAYS
ALWAYS
+15V
+15V
CHARGE PUMP POWER
ALWAYS
ALWAYS
+3V_S5
+3.3V
LAN/BT/CIR POWER
S5_ON
S0-S5
+5V_S5
+5V
USB POWER
S5_ON
S0-S5
+5V
+5V
HDD/ODD/Codec/TP/CRT/HDMI POWER
MAINON
S0
+3V
+3.3V
PCH/GPU/Peripheral component POWER
MAINON
S0
+1.5VSUS
+1.5V
CPU/SODIMM CORE POWER
SUSON
S0-S3
+0.75V_DDR_VTT
+0.75V
SODIMM Termination POWER
MAINON
S0
+VGFX_AXG
variation
Internal GPU POWER
GFX_ON
S0
+1.8V
+1.8V
CPU/PCH/Braidwood POWER
MAINON
S0
+1.5V
+1.5V
MINI CARD/NEW CARD POWER
MAINON
S0
ACTIVE IN
B
NTC
Thermal
Protection
CPU
CORE PWR
H_ORICHOT#
H/W Throttling
PM_THRMTRIP#
CPU
3V/5 V
SYS PWR
SYS_SHDN#
WIRE-AND
SML1ALERT#
FAN Driver
PCH
FAN
SM-Bus
CPU VTT POWER
MAINON
S0
+1.05V
+1.05V
PCH CORE POWER
MAINON
S0
S0
+1.1V_VTT
+1.05V or +1.1V
+VCC_CORE
variation
CPU CORE POWER
VRON
LCDVCC
+3.3V
LCD POWER
LVDS_VDDEN
+5V_GPU
+5V
SWITCHABLE PWM IC POWER
dGPU_PWR_EN#
EC
CPUFAN#
S0
Discrete enable
+GPU_CORE
+0.9V~+1.1V
GPU CORE POWER
+3V_D
Discrete enable
+GPU_IO
+0.9V~+1.1V
GPU I/O POWER
PG_GPUIO_EN
Discrete enable
+1.5V_GPU
+1.5V
VRAM CORE POWER
PG_1.5V_EN
Discrete enable
+1.8V_GPU
+1.8V
GPU_CRE/LVDS/PLL POWER
+1.5V_GPU
Discrete enable
+1V
+1V
DP/PEG POWER
PG_1V_EN
Discrete enable

PROJECT : ZQ9
Size
Document Number
PWR Status & GPU PWR CRL & THRM

Date:
1
Sheet
8
of
45
Rev
1A
6/21 unstuff
+1.5V
150mA(30mil)
L50
+1.5V_CLK
*PBY160808T-181Y-N/2A/180ohm_6
+VDDIO_CLK
C243
.1u/16V_4
C627
.1u/16V_4
C246
+3V
L23
C238
C267
C251
4.7u/10V_8
.1u/16V_4
.1u/16V_4
R455
<10> CLK_ICH_14M
C614
C244
C607
C609
.1u/16V_4
.1u/16V_4
10u/Y5V_8
10u/Y5V_8
U20
1
17
24
5
29
VDD_DOT
VDD_SRC
VDD_CPU
VDD_27
VDD_REF
CLK_SDATA
CLK_SCLK
31
32
SDA
SCL
33_4
CPU_SEL
30
REF_0/CPU_SEL
XTAL_IN
28
XTAL_IN
Y6
14.318MHz
C612
XTAL_OUT
27
XTAL_OUT
VDD_SRC_I/O
VDD_CPU_I/O
33p/50V_4
33p/50V_4
2
8
9
12
21
26
33
IDT:
AL003197001 (ICS9LVS3197AKLFT)
Realtek: AL000890000 (RTM890N-632-GRT)
Silego: AL000595000 (SLG8LV595VTR)
CPU_CLK select
PBY160808T/2A/180ohm_6 +1.05V
C613
.1u/16V_4
+3V_CLK
BLM18AG601SN1D/200mA/600ohm_6
L48
6/21 add for 3V CLK gen

R565
0_6
20mil
80mA(20mil)
VSS_DOT
VSS_27
VSS_SATA
VSS_SRC
VSS_CPU
VSS_REF
GND
Place each 0.1uF cap as close as

possible to each VDD IO pin. Place
the 10uF caps on the VDD_IO plane.
15
18
DOT_96
DOT_96#
3
4
27M
27M_SS
6
7
SRC_1/SATA
SRC_1#/SATA#
SRC_2
SRC_2#
10
11
13
14
*CPU_STOP#
16
CPU_1
CPU_1#
CPU_0
CPU_0#
20
19
23
22
CKPWRGD/PD#
25
CLK_BUF_DREFCLK <10>
CLK_BUF_DREFCLK# <10>
R448
R447
R130
*EV@33_4
*EV@33_4
C270
*EV@10p/50V_4
CLK_BUF_DREFSSCLK <10>
CLK_BUF_DREFSSCLK# <10>
CLK_BUF_PCIE_3GPLL <10>
CLK_BUF_PCIE_3GPLL# <10>
+3V
10K_4
27M_CLK <17>
27M_CLK_SS <17>
5/13 add for cost down solution

C
6/21 change the order
TP23
TP24
CLK_BUF_BCLK <10>
CLK_BUF_BCLK# <10>
CK_PWRGD_R
ICS9LRS3197AKLFT
+3V
SMBus
CLK Enable
+1.05V
+3V
R543
R451
*10K_4
<10> ICH_SMBDATA
R446
C617
10K_4
*10p/50V/COG_4
CLK_SDATA
CPU_SEL
R545
1K/F_4
2.2K_4
CLK_SDATA <14,15,27>
CK_PWRGD_R
3
Q18
2N7002K
+3V
R542
0
A
CPU_SEL CPU0/1=133MHz
(default)
2.2K_4
1
<10> ICH_SMBCLK
R544
100K/F_4
<38> VR_PWRGD_CK505#
Q19
2N7002K
CLK_SCLK
CLK_SCLK <14,15,27>
Q17
2N7002K
CPU0/1=100MHz

PROJECT : ZQ9
Size
Document Number
Rev
1A
Clock Generator
Date:
5
Sheet
1
of
45
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI)
AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on Arrandale
directly if motherboard only supports discrete graphics. If motherboard supports
integrated graphics but without eDP, these pins can also be connected to GND directly.
Processor Compensation Signals
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
D24
G24
F23
H23
<8>
<8>
<8>
<8>
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
D25
F24
E23
G23
E22
D21
D19
D18
G21
E19
F21
G18
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
D22
C21
D20
C18
G22
E20
F20
G19
FDI_FSYNC0_R
FDI_FSYNC1_R
F17
E17
FDI_INT_R
C17
FDI_LSYNC0_R
FDI_LSYNC1_R
F18
D17
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]
FDI_FSYNC[0]
FDI_FSYNC[1]
FDI_INT
FDI_LSYNC[0]
FDI_LSYNC[1]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
20/F_4
H_COMP3
AT23
R442
20/F_4
H_COMP2
AT24
R173
49.9/F_4 H_COMP1
G16
R440
49.9/F_4 H_COMP0
750/F_4
PEG_RXN[0..15] <16>
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
CPEG_TXN0
CPEG_TXN1
CPEG_TXN2
CPEG_TXN3
CPEG_TXN4
CPEG_TXN5
CPEG_TXN6
CPEG_TXN7
CPEG_TXN8
CPEG_TXN9
CPEG_TXN10
CPEG_TXN11
CPEG_TXN12
CPEG_TXN13
CPEG_TXN14
CPEG_TXN15
C587
C565
C585
C563
C583
C561
C581
C559
C579
C557
C577
C555
C575
C594
C602
C608
[email protected]/10V_4_X7R
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
CPEG_TXP0
CPEG_TXP1
CPEG_TXP2
CPEG_TXP3
CPEG_TXP4
CPEG_TXP5
CPEG_TXP6
CPEG_TXP7
CPEG_TXP8
CPEG_TXP9
CPEG_TXP10
CPEG_TXP11
CPEG_TXP12
CPEG_TXP13
CPEG_TXP14
CPEG_TXP15
C586
C564
C584
C562
C582
C560
C580
C558
C578
C556
C576
C554
C574
C596
C606
C610
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
Use reverse type

(at GPU side)
<11>
AT26
T10
AH24
H_CATERR#
AK14
AT15
H_PECI
H_PROCHOT#
<38> H_PROCHOT#
AN26
PEG_RXP[0..15] <16>
AK15
<11> PM_THRMTRIP#
T20
COMP3
COMP2
BCLK
BCLK#
COMP1
COMP0
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PM_EXT_TS#[0]
PM_EXT_TS#[1]
PRDY#
PREQ#
H_CPURST#
<8>
AP26
AL15
PM_SYNC
PEG_TXN[0..15] <16>
AN14
AN27
<11> H_PWRGOOD
AK13
<8> PM_DRAM_PWRGD
R193
<10,11,25,27,31,35> PLTRST#
PEG_TXP[0..15] <16>
H_VTTPWRGD
AM15
T14
AM26
1.5K/F_4 CPU_PLTRST# AL14
RESET_OBS#
PWR MANAGEMENT
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
Intel(R) FDI
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
R437
R444
CLOCKS
<8>
<8>
<8>
<8>
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
49.9/F_4
PM_SYNC
VCCPWRGOOD_1
VCCPWRGOOD_0
SM_DRAMPWROK
VTTPWRGOOD
TAPPWRGOOD
TCK
TMS
TRST#
JTAG & BPM
B24
D23
B23
A22
PCI EXPRESS -- GRAPHICS
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
R436
B26
A26
B27
A25
THERMAL
<8>
<8>
<8>
<8>
U22B
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI
A24
C23
B22
A21
MISC
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DDR3
MISC
U22A
<8>
<8>
<8>
<8>
TDI
TDO
TDI_M
TDO_M
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
A16
B16
AR30
AT30
CLK_CPU_BCLK <11>
CLK_CPU_BCLK# <11>
T62
T67
T21
D
E16
D16
CLK_PCIE_3GPLL <10>
CLK_PCIE_3GPLL# <10>
A18 DPLL_REF_SSCLK_R
A17 DPLL_REF_SSCLK#_R
R465
R471
R472
R463
F6
AL1
AM1
AN1
*IV@0_4
*IV@0_4
0_4
0_4
DDR3_DRAMRST#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
AN15
AP15
R254
R253
R252
<14,15>
100/F_4
24.9/F_4
130/F_4
R187
R183
PM_EXTTS#0 <14>
10K_4
10K_4
AT28
AP27
XDP_PREQ#
T68
T69
AN28
AP28
AT27
XDP_TCLK
XDP_TMS
XDP_TRST#
T8
T9
T71
AT29
AR27
AR29
AP29
XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M
T70
T66
T65
T64
AN25
H_DBR#_R
AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
R149
DPLL_REF_SSCLK <10>
DPLL_REF_SSCLK# <10>
Layout Note: Place

these resistors
near Processor
*Short_4
+1.05V
PM_EXTTS#1 <15>
XDP_DBRST# <8>
T19
T18
T17
T13
T11
T15
T16
T12
RSTIN#
R196
750/F_4
Clarksfield/Auburndale
<8> FDI_FSYNC0
<8> FDI_FSYNC1
<8>
FDI_INT
<8> FDI_LSYNC0
<8> FDI_LSYNC1
R157
R161
IV@0_4
IV@0_4
FDI_FSYNC0_R
FDI_FSYNC1_R
R171
IV@0_4
FDI_INT_R
R152
R167
IV@0_4
IV@0_4
FDI_LSYNC0_R
FDI_LSYNC1_R
R156
R160
R170
R151
R166
EV@1K_4
EV@1K_4
EV@1K_4
EV@1K_4
EV@1K_4
<The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT>Note that if these signals are left as no connect, there are no functional impacts, but a small amount of power (~15 mW) maybe wasted.
Processor pull-up
Thermaltrip protect
VTT PWR_Good
JTAG MAPPING
5/13 follow ZR7B setting
5/13 follow ZR7B setting
XDP_TDI_R
XDP_TDI
+1.05V
R433
0_4
R429
*0_4
XDP_TDO_M
XDP_TDO
H_CATERR#
H_PROCHOT#
H_CPURST#
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TCLK
XDP_TRST#
+1.05V
6/14 change the P/N
+3V
<8,38> DELAY_VR_PWRGOOD
Q16
FDV301N
R420
R192
R137
R438
R135
R435
R434
R133
R439
51/F_4
49.9/F_4
68_4
*68_4
*51_4
*51_4
*51_4
*51_4
51/F_4
<35>
MPWROK
R176
*0_4
R430
0_4
+1.5VSUS
2
Q15
3 MMBT3904
U5
R179
1K_4
TC7SH08FU
SYS_SHDN#
Scan Chain
(Default)
STUFF -> R469, R491, R507

NO STUFF -> R489, R490
CPU Only
STUFF -> R490, R491

NO STUFF -> R469, R489, R507
GMCH Only
STUFF -> R489, R507

NO STUFF -> R491, R490, R469
H_VTTPWRGD
4
2K/F_4
PM_THRMTRIP# 1
R432
XDP_TDO_R
0.1u/10V_4
<11> PM_THRMTRIP#
0_4
XDP_TDI_M
C309
R209
1K_4
XDP_TDO
R431
R205
1.1K/F_4
<37,44>
R199
3K/F_4
Use a voltage divider with VDDQ

(1.5V) rail (ON in S3) and
resistor combination of 4.75K (to
PM_DRAM_PWRGD VDDQ)/12K(to GND) to generate the
required voltage.
Note: CRB uses a 3.3V (always ON)
rail with 2K and 1K combination.

PROJECT : ZQ9
Size
Document Number
Rev
1A
AUBURNDA 1/4
Date:
5
Sheet
1
of
45
AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3)
U22D
U22C
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
W8
W9
M3
M_B_CLK0 <15>
M_B_CLK0# <15>
M_B_CKE0 <15>
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
V7
V6
M2
M_B_CLK1 <15>
M_B_CLK1# <15>
M_B_CKE1 <15>
SB_CS#[0]
SB_CS#[1]
AB8
AD6
M_B_CS#0 <15>
M_B_CS#1 <15>
SB_ODT[0]
SB_ODT[1]
AC7
AD1
M_B_ODT0 <15>
M_B_ODT1 <15>
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
D4
E1
H3
K1
AH1
AL2
AR4
AT8
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
D5
F4
J4
L4
AH2
AL4
AR5
AR8
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
C5
E3
H4
M5
AG2
AL5
AP5
AR7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
<14> M_A_DQ[63:0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
<14> M_A_BS#0
<14> M_A_BS#1
<14> M_A_BS#2
AC3
AB2
U7
SA_BS[0]
SA_BS[1]
SA_BS[2]
<14> M_A_CAS#
<14> M_A_RAS#
<14> M_A_WE#
AE1
AB3
AE9
SA_CAS#
SA_RAS#
SA_WE#
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
AA6
AA7
P7
M_A_CLK0 <14>
M_A_CLK0# <14>
M_A_CKE0 <14>
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
Y6
Y5
P6
M_A_CLK1 <14>
M_A_CLK1# <14>
M_A_CKE1 <14>
AE2
AE8
M_A_CS#0 <14>
M_A_CS#1 <14>
AD8
AF9
M_A_ODT0 <14>
M_A_ODT1 <14>
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
DDR SYSTEM MEMORY A
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_A_DM[7:0] <14>
B9
D7
H7
M7
AG6
AM7
AN10
AN13
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
C9
F8
J9
N9
AH7
AK9
AP11
AT13
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS#[7:0] <14>
C8
F9
H9
M9
AH8
AK10
AN11
AR13
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS[7:0] <14>
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A[15:0] <14>
B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10
<15> M_B_BS#0
<15> M_B_BS#1
<15> M_B_BS#2
AB1
W5
R7
<15> M_B_CAS#
<15> M_B_RAS#
<15> M_B_WE#
AC5
Y7
AC6
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
DDR SYSTEM MEMORY - B
<15> M_B_DQ[63:0]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
M_B_DM[7:0] <15>
M_B_DQS#[7:0] <15>
M_B_DQS[7:0] <15>
M_B_A[15:0] <15>
Channel A DQ[15,32,48,54], DM[5]

Requires minimum 12mils spacing
with all other signals, including data signals.
Channel B DQ[16,18,36,42,56,57,60,61,62]
Requires minimum 12mils spacing
with all other signals, including data signals.

PROJECT : ZQ9
Size
Document Number
Rev
1A
AUBURNDA 2/4
Date:
5
Sheet
1
of
45
T72
C281
C280
IV@22u/6.3V_8 IV@22u/6.3V_8
C316
330u/2V_7343
5/27 cost down

+
C651
*IV@330U/2V_7343
C298
IV@10u/6.3V_8
C299
IV@10u/6.3V_8
AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15
C313
22U/6.3V_8
C326
22U/6.3V_8
R153
EV@1K_4
SENSE
LINES
+
C635
*IV@330U/2V_7343
5/27 cost down
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
+1.05V
J24
J23
H25
5/27 cost down

C311
10U/6.3V_8
GRAPHICS VIDs
5/27 cost down
AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16
VTT1_45
VTT1_46
VTT1_47
VAXG_SENSE
VSSAXG_SENSE
AR22
AT22
VCC_AXG_SENSE
VSS_AXG_SENSE
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
AM22
AP22
AN22
AP23
AM23
AP24
AN24
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
GFX_VID5
GFX_VID6
AR25
AT25
AM24
<41>
<41>
<41>
<41>
<41>
<41>
<41>
GFX_ON <41>
GFX_DPRSLPVR <41>
GFX_IMON <41>
R147
EV@1K_4
ARD:3A
CFD:6A
C655
22u/6.3V_8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VTT0_59
VTT0_60
VTT0_61
VTT0_62
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
+1.5VSUS
P10
N10
L10
K10
C358
C356
C355
C352
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
C417
C360
C357
1U/6.3V_4
22U/6.3V_8
22U/6.3V_8
+ C363
330U/2V_7343
+1.05V
C660
C654
10U/6.3V_8
10U/6.3V_8
VTT_SELECT
H_PSI#
AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
H_DPRSLPVR
H_VID0 <38>
H_VID1 <38>
H_VID2 <38>
H_VID3 <38>
H_VID4 <38>
H_VID5 <38>
H_VID6 <38>
H_DPRSLPVR
C332
10U/6.3V_8
<38>
C656
10U/6.3V_8
C312
22u/6.3V_8
C330
22u/6.3V_8
<38>
AN35
VTT_SENSE
VSS_SENSE_VTT
10U/6.3V_8
10U/6.3V_8
100/F_4
VCCPLL1
VCCPLL2
VCCPLL3
L26
L27
M26
+1.8V
22U/6.3V_8
4.7U/6.3V_6
2.2U/6.3V_6
1U/6.3V_4
1U/6.3V_4
C258
C274
C231
C233
C239
AJ34
AJ35
B15
A15
<38>
+VCC_CORE
VCCSENSE <38>
VSSSENSE <38>
R103
100/F_4
VTT_SENSE
VSS_SENSE_VTT
T75
T74
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
H_DPRSLPVR
H_PSI#
R388
R395
R387
R394
R389
R396
R400
R409
R401
R410
R404
R413
R402
R411
R403
R412
R419
R418
1K_4
*1K/F_4
1K_4
*1K/F_4
1K_4
*1K/F_4
*1K/F_4
1K_4
*1K/F_4
1K_4
1K_4
*1K/F_4
*1K/F_4
1K_4
1K_4
*1K/F_4
*1K/F_4
1K_4
Note:
For Validating IMVP VR R6451 should be STUFF
and R2N1 NO_STUFF
AUBURNDALE/CLARKSFIELD PROCESSOR (POWER)
+1.05V

HFM_VID : Max 1.4V
LFM_VID : Min 0.65V
PROJECT : ZQ9
Size
Document Number
Rev
1A
AUBURNDA 3/4 (PWR)

Date:
C618
C630
I_MON
R104
VCC_SENSE
VSS_SENSE
J22
J20
J18
H21
H20
H19
G15
H_VTTVID1=Low, 1.1V
H_VTTVID1=High, 1.05V
ISENSE
VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68
0.6A
1.8V
H_PSI#
VTT1_48
VTT1_49
VTT1_50
VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58
PEG & DMI
PSI#
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR
AN33
K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25
1.1V
5/27 cost down

5/27 cost down
<41>
<41>
T73
- 1.5V RAILS
22A
+VGFX_AXG
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
DDR3
1.1V RAIL POWER
U22G
+1.05V
C658
C657
C634
C327
C648
C649
C644
C659
C652
C331
FDI
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44
CPU CORE SUPPLY
18A
AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
POWER
6/21 stuff
VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32
+1.05V
POWER
330u/2V_7343
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
CPU VIDS
330u/2V_7343
C285
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
GRAPHICS
C284
10U/6.3V_8
22U/6.3V_8
10U/6.3V_8
22U/6.3V_8
22U/6.3V_8
10U/6.3V_8
10U/6.3V_8
22U/6.3V_8
22U/6.3V_8
10U/6.3V_8
10U/6.3V_8
22U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
0.1u/10V_4_X7R
0.1u/10V_4_X7R
+
C568
C626
C234
C589
C623
C643
C642
C590
C567
C640
C230
C588
C235
C569
C297
C624
C621
C638
C625
C566
C622
C266
C265
C236
C641
C287
C232
C633
C275
C271
AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)
VTT Rail Values are

Auburndal VTT=1.05V
Clarksfield VTT=1.1V
+VCC_CORE
SENSE LINES
5/27 cost down
U22F
CPU Core Power

ARD:48A
CFD:52A
Sheet
1
of
45
U22I
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W 35
W 34
W 33
W 32
W 31
W 30
W 29
W 28
W 27
W 26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30
K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9
U22E
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
J17
H17
G25
G17
E31
E30
<14> VREF_DQ_DIMM0
<15> VREF_DQ_DIMM1
CFG0
CFG3
CFG4
CFG7
VSS
NCTF
U22H
AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35
AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
AT35
AT1
AR34
B34
B2
B1
A35
TP20
TP22
TP34
TP25
TP26
AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86
B19
A19
RSVD15
RSVD16
A20
B20
RSVD17
RSVD18
U9
T9
RSVD19
RSVD20
AC9
AB9
RSVD21
RSVD22
C1
A3
RSVD_NCTF_23
RSVD_NCTF_24
J29
J28
RSVD26
RSVD27
A34
A33
RSVD_NCTF_28
RSVD_NCTF_29
C35
B35
RSVD_NCTF_30
RSVD_NCTF_31
RESERVED
AUBURNDALE/CLARKSFIELD PROCESSOR (GND)
RSVD32
RSVD33
AJ13
AJ12
RSVD34
RSVD35
AH25
AK26
RSVD36
RSVD_NCTF_37
AL26
AR2
RSVD38
RSVD39
AJ26
AJ27
RSVD_NCTF_40
RSVD_NCTF_41
AP1
AT2
RSVD_NCTF_42
RSVD_NCTF_43
AT3
AR1
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58
AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32
RSVD_TP_59
RSVD_TP_60
KEY
RSVD62
RSVD63
RSVD64
RSVD65
E15
F15
A2
D15
C15
AJ15
AH15
RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
VSS
TP8
TP9
AP34
TP19
AP34 can be NC on CRB; EDS/DG suggestion to GND

Processor Strapping
1
CFG0
(PCI-Epress
Configuration Select)
Single PEG
CFG3
(PCI-Epress Static
Lane Reversal)
Normal Operation
Ts
hI
p
ea
n
ec
n
t
c
Co
d
e
i
lm
l
f
ap
B
i
ro
G
r
c
kn
A
e
CFG4
Disabled; No Physical Display Port
(Embended
Display Port Presence) attached to Embedded Diplay Port
DEFAULT
0
Bifurcation enabled
Lane Numbers Reversed
Enabled; An external Display port
device is connected to the Embedded
Display port
CFG0 R128
*3.01K_NC
CFG3 R125
3.01K/F_4
CFG4 R127
*3.01K
CFG7 R126
*3.01K/F_4

PROJECT : ZR7B
Size
Document Number
Rev
1A
AUBURNDA 4/4
Date:
4
Sheet
1
of
45
AC-coupling CAP place close to PCH
IBEX PEAK-M (DMI,FDI,GPIO)
IBEX PEAK-M (LVDS,DDI)
0-ohm resistor place close to PCH

U21C
BE22
BF21
BD20
BE18
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
BD22
BH21
BC20
BD18
BH25
+1.05V
R441
49.9/F_4
BF25
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
DMI_ZCOMP
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
DMI_IRCOMP
FDI_LSYNC0
FDI_LSYNC1
BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12
FDI_TXP0_R
FDI_TXP1_R
FDI_TXP2_R
FDI_TXP3_R
FDI_TXP4_R
FDI_TXP5_R
FDI_TXP6_R
FDI_TXP7_R
R459
R475
R478
R491
R461
R484
R498
R493
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
BJ14
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
FDI_INT
U21D
SYS_PWROK
T6
M6
B17
K5
RSV_ICH_LAN_RST# A10
D9
<4> PM_DRAM_PWRGD
C16
<35> ICH_RSMRST#
SUS_PWR_ACK_R
M1
P5
<35> DNBSWON#
<35>
R246
PCH_ACIN
*0_4 ACIN_R
P7
PM_BATLOW#
A6
PM_RI#
F14
SYS_RESET#
WAKE#
SYS_PWROK
PWROK
MEPWROK
LAN_RST#
DRAMPWROK
RSMRST#
CLKRUN# / GPIO32
System Power Management
XDP_DBRST#
BH13
FDI_FSYNC1
<4>
BJ12
FDI_LSYNC0
<4>
BG14
FDI_LSYNC1
<4>
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SUS_PWR_DN_ACK / GPIO30
PWRBTN#
ACPRESENT / GPIO31
SLP_S3#
SLP_M#
TP23
BATLOW# / GPIO72
RI#
PMSYNCH
SLP_LAN# / GPIO29
IV@0_4
IV@0_4
<23> INT_TXLCLKOUT<23> INT_TXLCLKOUT+

<23> INT_TXLOUT0<23> INT_TXLOUT1<23> INT_TXLOUT2<23> INT_TXLOUT0+
<23> INT_TXLOUT1+
<23> INT_TXLOUT2+
INT_TXLOUT0INT_TXLOUT1INT_TXLOUT2-
BB47
BA52
AY48
AV47
INT_TXLOUT0+
INT_TXLOUT1+
INT_TXLOUT2+
BB48
BA50
AY49
AV48
AP48
AP47
<25,27>
AY53
AT49
AU52
AT53
<35>
AY51
AT48
AU50
AT51
R234
*Short_4
ICH_SUSCLK
H7
SUSC#
<35>
P12
SUSB#
<35>
R225
Y53
Y51
<23> INT_HSYNC
<23> INT_VSYNC
*0_4
DAC_IREF
TP32
BJ10
PM_SYNC
PM_SLP_LAN#
AA52
AB53
AD53
V51
V53
<23> INT_CRT_DDCCLK
<23> INT_CRT_DDCDAT
N2
F6
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
<23> INT_CRT_BLU
<23> INT_CRT_GRN
<23> INT_CRT_RED
SLP_M#
L_BKLTEN
L_VDD_EN
SDVO_TVCLKINN
SDVO_TVCLKINP
L_BKLTCTL
SDVO_STALLN
SDVO_STALLP
L_DDC_CLK
L_DDC_DATA
SDVO_INTN
SDVO_INTP
R134
1K/F_4
<4>
AD48
AB51
BJ46
BG46
BJ48
BG48
BF45
BH45
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
SDVO_CTRLCLK
SDVO_CTRLDATA
LVD_VREFH
LVD_VREFL
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
<35>
E4
K8
AT43
AT42
INT_TXLCLKOUT- AV53
INT_TXLCLKOUT+ AV51
P8
F3
AB46
V48
[email protected]/F_4 AP39
AP41
R111
R112
<4>
CLKRUN#
IV@10K_4
IV@10K_4
R144
FDI_FSYNC0
Y1
R119
R120
+3V
<4>
PCIE_WAKE#
AB48
Y45
<23> INT_LVDS_EDIDCLK
<23> INT_LVDS_EDIDDATA
BF13
J12
Y48
<23> INT_LVDS_BRIGHT
<4> XDP_DBRST#
T48
T47
<23> INT_LVDS_BLON
<23> INT_LVDS_DIGON
Digital Display Interface
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
LVDS
<4>
<4>
<4>
<4>
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12
R454
R470
R481
R487
R464
R480
R500
R495
CRT_BLUE
CRT_GREEN
CRT_RED
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
CRT_DDC_CLK
CRT_DDC_DATA
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
T51
T53
SDVO_CTRLCLK <24>
SDVO_CTRLDAT <24>
BG44
BJ44
AU38
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
INT_HDMI_HPD
INT_HDMITX2N_R
INT_HDMITX2P_R
INT_HDMITX1N_R
INT_HDMITX1P_R
INT_HDMITX0N_R
INT_HDMITX0P_R
INT_HDMICLK-_R
INT_HDMICLK+_R
C249
C247
C242
C245
C253
C250
C237
C241
<24>
INT_HDMITX2N
INT_HDMITX2P
INT_HDMITX1N
INT_HDMITX1P
INT_HDMITX0N
INT_HDMITX0P
INT_HDMICLKINT_HDMICLK+
<24>
<24>
<24>
<24>
<24>
<24>
<24>
<24>
C
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
<4>
<4>
<4>
<4>
BD24
BG22
BA20
BG20
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
FDI
<4>
<4>
<4>
<4>
BC24
BJ22
AW20
BJ20
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI
<4>
<4>
<4>
<4>
FDI_TXN0_R
FDI_TXN1_R
FDI_TXN2_R
FDI_TXN3_R
FDI_TXN4_R
FDI_TXN5_R
FDI_TXN6_R
FDI_TXN7_R
Y49
AB49
BE44
BD44
AV40
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36
U50
U52
BC46
BD46
AT38
R place close to PCH
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
R425
IV@150_4 INT_CRT_BLU
R426
IV@150_4 INT_CRT_GRN
R427
IV@150_4 INT_CRT_RED
IbexPeak-M_R1P0
TP18
IbexPeak-M_R1P0
PCH Pull-high/low
+3V_S5
System PWR_OK
+3V
XDP_DBRST#
R226
PM_RI#
R184
10K_4
PM_BATLOW#
R514
10K_4
+3V_S5
8.2K_4
1K_4
C636
PCIE_WAKE#
R230
10K_4
ICH_RSMRST#
R482
10K_4
PM_SLP_LAN#
R248
*10K_4
RSV_ICH_LAN_RST#
R499
10K_4
SUS_PWR_ACK_R
R530
10K_4
SYS_PWROK
R477
10K_4
ACIN_R
R227
10K_4
DELAY_VR_PWRGOOD need PU 2K to +3V.

PU at power side
*.1u_4
R523
1
SYS_PWROK
DELAY_VR_PWRGOOD
4
2
U24
CLKRUN#
R538
PWROK_EC
<4,38>
<35>
100K_4
TC7SH08FU
PROJECT : ZQ9
Size
Document Number
Rev
1A
IBEX PEAK-M 1/6

Date:
5
Sheet
1
of
45
RTC Circuitry
2
1
15p/50V_4
Y1
1
BAT54C
C662
1u/10V_4
BT1
R474
C663
1u/10V_4
RTC_RST#
C14
SRTC_RST#
D17
C650
1u/10V_4
R479
+VCCRTC
1M_4
SM_INTRUDER#
A16
PCH_INVRMEN
J1
*SHORT_ PAD1
A14
RTCX1
RTCX2
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
RTCRST#
FWH4 / LFRAME#
SRTCRST#
INTRUDER#
LDRQ0#
LDRQ1# / GPIO23
INTVRMEN
SERIRQ
D33
B33
C32
A32
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
C34
LPC_LFRAME#
<27,35>
<27,35>
<27,35>
<27,35>
<27,35>
D
A34
F34
R222
10K_4
AB9
+3V
IRQ_SERIRQ
<35>
RTC_CONN
B13
D13
SRTC_RST#
20K/F_4
1
1
2
U21A
RTC_X1
RTC_X2
15p/50V_4
J2
*SHORT_ PAD1
2
R473
1K_4
R195
10M_4
32.768KHZ
C328
LPC
RTC_RST#
20K/F_4
3
4
R483
RTC
CR1
+3VPCU
VCCRTC_1
1
2
C335
+VCCRTC
SPKR
P1
ACZ_RST#
C30
G30
<29> PCH_AZ_CODEC_SDIN0
F30
E32
F32
+3V_S5
HDA Bus
R460
ACZ_SDOUT
B29
PCH_GPIO33
H32
PCH_GPIO13
*10K_4
<24> HDMI_HPD_PCH#
J30
M3
K3
<29> PCH_AZ_CODEC_SYNC
R453
33_4
ACZ_SYNC
R449
33_4
ACZ_RST#
R456
33_4
ACZ_SDOUT
K1
<29> PCH_AZ_CODEC_RST#
J2
J4
<29> PCH_AZ_CODEC_SDOUT
R450
<29> PCH_AZ_CODEC_BITCLK
33_4
SPI_CLK_R
BA2
SPI_CS0#_R
AV3
SPI_CS1#
AY3
ACZ_BIT_CLK
+3VPCU
C628
*27p_4
R525
*10K_4
SPI_SI_R
AY1
SPI_SO_R
AV1
HDA_BCLK
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
HDA_SYNC
SPKR
HDA_RST#
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
HDA_SDIN0
HDA_SDIN1
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
IHDA
<29>
A30
D29
SPKR
HDA_SDIN2
HDA_SDIN3
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
HDA_SDO
HDA_DOCK_EN# / GPIO33
HDA_DOCK_RST# / GPIO13
SATA
ACZ_SYNC
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
JTAG_TCK
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
JTAG_TMS
JTAG_TDI
JTAG
ACZ_BIT_CLK
Internal weak pull-down

VCCVRM=>+1.8V (default)
external pull-up
VCCVRM=>+1.5V
JTAG_TDO
TRST#
SATAICOMPO
SATAICOMPI
AK7
AK6
AK11
AK9
SATA_RXN0_C
SATA_RXP0_C
SATA_RXN0_C <28>
SATA_RXP0_C <28>
SATA_TXN0 <28>
SATA_TXP0 <28>
AH6
AH5
AH9
AH8
SATA_RXN1_C
SATA_RXP1_C
SATA_RXN1_C <28>
SATA_RXP1_C <28>
SATA_TXN1 <28>
SATA_TXP1 <28>
AF11
AF9
AF7
AF6
Note:
SATA port2/3 may not be available on all PCH sku
(HM55 support 3 port only)
AH3
AH1
AF3
AF1
AD9
AD8
AD6
AD5
AD3
AD1
AB3
AB1
AF16
R182
AF15
37.4/F_4
+1.05V
SPI_CLK
SATA_ACT# <32>
SPI_CS0#
SPI_CS1#
SATALED#
SPI_MOSI
SATA0GP / GPIO21
SPI
HDA_SYNC (PCH strap pin)
SPI_MISO
SATA1GP / GPIO19
T3
TP13
Y9
R240
43K/F_4
+3V
V1
R521
43K/F_4
+3V
IbexPeak-M_R1P0
PCH Strap Pin Configuration Table-1

INTVRMEN Integrated 1.05V VRM Enable /
Disable
1 = Integrated VRM is enabled

0 = Integrated VRM is disabled
+VCCRTC
R489
330K_6
PCH_INVRMEN
SPI_MOSI
TPM Functionality
Disable
1 = Enabled
0 = Disable
+3V
R540
*1K_4
SPI_SI_R
SPKR
Reboot option at power-up
0 = Default Mode (Internal weak Pull-down)

1 = No Reboot Mode with TCO Disabled
+3V
R532
PCH SPI
B
HDA_DOCK_EN Flash Descriptor

Security Override
#/GPIO33
0 = Flash Descriptor Security will be overridden

1 = Security measure defined in the Flash
Descriptor will be enabled.
GNT0#,
GNT1#
(0,0) = LPC
(1,0) = PCI
*1K/F_4 SPKR
B
PCH_GPIO33
R164
R145
*1K/F_4
*10K_4
+3V
+3V
U25
SPI_CS0#_R
SPI_CLK_R
SPI_SI_R
SPI_SO_R
1
6
5
2
3
CE#
SCK
SI
SO
VDD
HOLD#
WP#
VSS
W25Q32BVSSIG
+3V
R541
R129
R122
R123
R131
8
7 R539
3.3K/F_4
GNT2#/
GPIO53
4
C671
.1u/10V_4
GNT3#/
GPIO55
3.3K/F_4
NV_ALE
NV_CLE
GPIO8
Boot BIOS Strap
(0,1) = Reserved NAND

<10>
(1,1) = SPI
PCI_GNT0#
<10> PCI_GNT1#
ESI compatible mode is for server

platforms only
ESI Strap
(Server Only)
R158
<10> PWM_SELECT#
GPIO15
GPIO27
+3V
*1K/F_4
Top-Block
Swap Override
IntelR Anti-Theft Technology
HDD Data Protection
(Intel AT-d) Enable
0 = Top Block Swap Mode

1 = Default Mode (Internal pull-up)
1 = Enabled
0 = Disabled (Default)
<10>
NV_ALE
R202
*1K/F_4
+1.8V
DMI Termination
Voltage
DMI termination voltage. Weak

internal pull-up. Do not pull low.
<10>
NV_CLE
R206
*1K/F_4
+1.8V
Reserved
<10> PCI_GNT3#
This signal has a weak internal pull up.

NOTE: This signal should not be pulled low<11>
RSV_GPIO8
R421
R204
R203
1K_4
1K_4
*1K_4
*1K_4
Reserved
On-Die PLL Voltage

Regulator
<internal weak pull-up>
0 = Intel ME Crypto Transport Layer Security

(TLS) cipher suite with no confidentiality
1 = Intel ME Crypto Transport Layer Security<11>
(TLS) cipher suite with confidentiality
0 = Disables the VccVRM.
1 = Enables the internal VccVRM to have
a clean supply for analog rails.
CR_WAKE#
<11> PCH_GPIO27
*10K/F_4
10K_4
+3V_S5
*1K_4
R244
1K_4
R221
*10K_4
+3V_S5

PROJECT : ZQ9
Size
Document Number
Rev
1A
IBEX PEAK-M 2/6

Date:
5
Sheet
1
of
45
U21B
U21E
<27>
PCI_GNT0#
PCI_GNT1#
PWM_SELECT#
PCI_GNT3#
F48
K45
F36
H53
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
B41
K53
A36
A48
PCI_RST#
PCI_RST#
K6
PCI_SERR#
PCI_PERR#
E44
E50
PCI_IRDY#
TP15
PCI_DEVSEL#
PCI_FRAME#
A42
H44
F46
C46
PCI_PLOCK#
D49
PCI_STOP#
PCI_TRDY#
D41
C48
ICH_PME#
M7
PCI_PLTRST#
R423
TP21
R105
CLK_PCI_FB R117
<27> CLK_LPC_DEBUG
B
<35> CLK_PCI_775
22_4
22_4
22_4
CLK_LPC_DEBUG_C
CLK_PCI_PCCARD
CLK_PCI_775_C
CLK_PCI_FB_C
D5
N52
P53
P46
P51
P48
NV_WE#_CK0
NV_WE#_CK1
PIRQA#
PIRQB#
PIRQC#
PIRQD#
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
PCIRST#
SERR#
PERR#
IRDY#
PAR
DEVSEL#
FRAME#
PLOCK#
USBRBIAS#
STOP#
TRDY#
USBRBIAS
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
BA32
BB32
BD32
BE32
BF33
BH33
BG32
BJ32
NV_ALE
NV_CLE
BD3
AY6
NV_ALE <9>
NV_CLE <9>
AU2 NV_RCOMP R508
<27>
<27>
<27>
<27>
LAN
*32.4/F_4
PCIE_RX6PCIE_RX6+
PCIE_TX6PCIE_TX6+
C259
C268
0.1u/10V_4_X7R PCIE_TXN6_C
0.1u/10V_4_X7R PCIE_TXP6_C
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
BA34
AW34
BC34
BD34
AT34
AU34
AU36
AV36
AV7
AY8
AY5
BG34
BJ34
BG36
BJ36
AV11
BF5
SML0ALERT# / GPIO60
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
USBP1USBP1+
USBP4USBP4+
<33>
<33>
<33>
<33>
AK48
AK47
MB USB
BLUETOOTH 3.0
CLK_PCIE_REQ0#
AM43
AM45
EHCI1
CLK_PCIE_REQ1#_R
TP29
TP30
USB port6/7 may not be available on all PCH sku
(HM55 support 12port only)
USBP8USBP8+
USBP9USBP9+
<23>
<23>
<33>
<33>
USBP11USBP11+
USBP12USBP12+
USBP13USBP13+
<33>
<33> USB/B-USB1-1
<31>
<31> Card Reader
<27,33>
<27,33>Mini Card (WLAN
B25 USB_BIAS R466
<27> PCIE_CLK_REQ2#
U4
AM47
AM48
<27> CLK_PCH_SRC2#
<27> CLK_PCH_SRC2
Camera
R531
*Short_4
CLK_PCIE_REQ2#_R
USB/B-USB1-2
TP28
TP27
P9
N4
AH42
AH41
CLK_PCIE_REQ3#
EHCI2
A8
AM51
AM53
& BT 2.0)
CLK_PCIE_REQ4#
M9
D25
TP4
PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6
SML1DATA / GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
PERN8
PERP8
PETN8
PETP8
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_BCLK_N
CLKIN_BCLK_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
RSV_SMBALERT#
H14
ICH_SMBCLK
C8
ICH_SMBDATA
J14
RSV_SML0ALERT#
C6
SMB_CLK_ME0
G8
SMB_DATA_ME0
M14
RSV_SML1ALERT# R242
E10
SMB_CLK_ME1
G12
SMB_DATA_ME1
ICH_SMBCLK <3>
ICH_SMBDATA <3>
T13
CL_CLK1
T11
CL_DATA1
T9
CL_RST1#
*0_4
SML1ALERT# <11,34,35>
CL_CLK1 <27>
CL_DATA1 <27>
CL_RST1# <27>
5/25 add net
PEG_A_CLKRQ# / GPIO47
PERN7
PERP7
PETN7
PETP7
CLKOUT_PCIE3N
CLKOUT_PCIE3P
REFCLK14IN
H1
PEG_CLKREQ#_R
AD43
AD45
CLK_PCIE_VGA# <16>
CLK_PCIE_VGA <16>
AN4
AN2
CLK_PCIE_3GPLL# <4>
CLK_PCIE_3GPLL <4>
AT1
AT3
DPLL_REF_SSCLK# <4>
DPLL_REF_SSCLK <4>
AW24
BA24
CLK_BUF_PCIE_3GPLL# <3>
CLK_BUF_PCIE_3GPLL <3>
AP3
AP1
CLK_BUF_BCLK# <3>
CLK_BUF_BCLK <3>
F18
E18
CLK_BUF_DREFCLK# <3>
CLK_BUF_DREFCLK <3>
AH13
AH12
CLK_BUF_DREFSSCLK# <3>
CLK_BUF_DREFSSCLK <3>
P41
CLK_ICH_14M <3>
C600
CLKIN_PCILOOPBACK
CLKOUT_PCIE4N
CLKOUT_PCIE4P
XTAL25_IN
XTAL25_OUT
H6
XCLK_RCOMP
CLKOUT_PCIE5N
CLKOUT_PCIE5P
CLKOUTFLEX0 / GPIO64
USB_OC0# <33>
TP5
TP11
TP10
AK53
AK51
<25> CLK_PCIE_LOM#
<25> CLK_PCIE_LOM
USB_OC4_5# <33>
<25> CLK_PCIE_LAN_REQ#
USB_OC6#
USB_OC7#
SML0DATA
SML1ALERT# / GPIO74
B9
J42
CLK_PCI_FB
AH51
AH53
XTAL25_IN
XTAL25_OUT
18p/50V_4
R428
1M_4
AF38 XCLK_RCOMP R141
90.9/F_4
Y5
25MHz
C599
+1.05V
18p/50V_4
22.6/F_4
AJ50
AJ52
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4_5#
SML0CLK
SML1CLK / GPIO58
Port1 and port9 can be used on debug mode
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24
N16
J16
F16
L16
E14
G16
F12
T15
SMBDATA
PERN2
PERP2
PETN2
PETP2
SMBus
AU30
AT30
AU32
AV32
SMBCLK
Link
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
SMBALERT# / GPIO11
Controller
AW30
BA30
BC30
BD30
CLK_PCIE_REQ5#
PME#
PLTRST#
AV9
BG8
PERN1
PERP1
PETN1
PETP1
PCI-E*
NVRAM
NV_RB#
NV_WR#0_RE#
NV_WR#1_RE#
0.1u/10V_4_X7R PCIE_TXN1_C
0.1u/10V_4_X7R PCIE_TXP1_C
PEG
F51
A46
B45
M53
NV_RCOMP
C615
C616
<9>
<9>
<9>
<9>
TP3
PCI_GNT0#
PCI_GNT1#
PWM_SELECT#
PCI_GNT3#
PCI_REQ0#
PCI_REQ1#
dGPU_SELECT#
PCI_REQ3#
NV_ALE
NV_CLE
Wireless
BG30
BJ30
BF29
BH29
TP1
G38
H51
B37
A44
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
<25> PCIE_RX1<25> PCIE_RX1+

<25> PCIE_TX1<25> PCIE_TX1+
From CLK BUFFER
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
NV_DQS0
NV_DQS1
AY9
BD1
AP15
BD8
R233
*Short_4
PCIE_CLK_REQB#
P13
TP6
TP7
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ# / GPIO56
Clock Flex
J50
G42
H47
G34
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
PCI
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
USB
H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36
T45
BOARD_ID1
P43
BOARD_ID2
T42
BOARD_ID3
N50 dGPU_EDIDSEL# R121
*10K_4
+3V
IbexPeak-M_R1P0
IbexPeak-M_R1P0
6/9 set for board ID

+3V
+3V_S5
+3V_S5
+3V_S5
+3V_S5
6
7
8
9
10
5
4
3
2
1
USB_OC1#
USB_OC0#
USB_OC6#
USB_OC7#
8.2K_10P8R
CLK_PCIE_REQ0#
10K_4
CLK_PCIE_REQ3#
10K_4
CLK_PCIE_REQ4#
10K_4
CLK_PCIE_REQ5#
10K_4
PCIE_CLK_REQB#
10K_4
IV@10K_4 PEG_CLKREQ#_R
R534
10K_4
5
PCI_PLTRST#
2
4
PLTRST# <4,11,25,27,31,35>
+3V
3
U7
TC7SH08FU
6
7
8
9
10
R251
R407
10K_4
R408
*10K_4 BOARD_ID3 R414
BOARD_ID2 R136
10K_4
*10K_4
R180
10K_4
<35> 2ND_MBCLK
CLK_PCIE_REQ1#_R
2.2K_4
SMB_CLK_ME1
3
Q4
2N7002K
+3V_S5
BOARD_ID1
+3V
RP4
PCI_PIRQD#
PCI_REQ1#
PCI_FRAME#
PCI_TRDY#
*10K_4 BOARD_ID1 R132
+3V
C353
.1u/10V_4
R406
Not Defined
+3V
5
4
3
2
1
PCI_REQ3#
PCI_PIRQB#
PCI_REQ0#
PCI_PIRQH#
High = 80port output to LPC

BOARD_ID2
8.2K_10P8R
dGPU_SELECT#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
CLK_PCIE_REQ2#_R
R138
R139
R422
R143
R518
10K_4
8.2K_4
8.2K_4
8.2K_4
10K_4
R529
EV@10K/F_4 PEG_CLKREQ#_R
R181
Low = 80port output to PCI
USB_OC3#
USB_OC2#
USB_OC4_5#
R245
R513
R229
R247
R232
R517
+3V_S5
RP2
BOARD_ID3
Low = Reserved (Default)
<35> 2ND_MBDATA
100K_4
+3V
2.2K_4
High = Reserved
1
3
Q5
2N7002K
SMB_DATA_ME1
RP1
R249
PCI_PIRQC#
PCI_PIRQA#
PCI_STOP#
PCI_IRDY#
*0_4
+3V
6
7
8
9
10
5
4
3
2
1
PCI_DEVSEL#
PCI_PLOCK#
PCI_PERR#
PCI_SERR#
+3V_S5
R504
R211
R243
R512
R511
R214
R212
8.2K_10P8R
10K_4
10K_4
10K_4
2.2K_4
2.2K_4
2.2K_4
2.2K_4
RSV_SMBALERT#
RSV_SML0ALERT#
RSV_SML1ALERT#
ICH_SMBCLK
ICH_SMBDATA
SMB_CLK_ME0
SMB_DATA_ME0

PROJECT : ZQ9
Size
Rev
1A
IBEX PEAK-M 3/6

Date:
Document Number
1
Sheet
10
of
45
GPU RST#
5/18 change for discrete only

D
R73
IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)

U21F
SIO_EXT_SMI#
C38
<35> SIO_EXT_SCI#
SIO_EXT_SCI#
D37
TACH2 / GPIO6
BOARD_ID0
J32
TACH3 / GPIO7
TP14
<9>
CR_WAKE#
F10
LAN_DISABLE#
K9
CR_WAKE#
T7
dGPU_HOLD_RST#
<19> dGPU_PWROK
GPIO22
PCH_GPIO27
PCH_GPIO27
TP17
TP12
CLK_CPU_BCLK# <4>
AM1
CLK_CPU_BCLK <4>
BG10
H_PECI <4>
T1
SIO_RCIN#
BE10
H_PWRGOOD <4>
V13
V6
GPIO38
dGPU_PWR_EN# should be stable

before dGPU_VRON enable
SAVE_LED#
TP33
R524
<10,34,35> SML1ALERT#
EC suggestion use GPIO49 for FAN control
*Short_4
AB7
AB13
V3
P3
GPIO45
H3
RST_GATE#
F1
SV_SET_UP
AB6
SATA5GP
AA4
GPIO57
SATA5GP / GPIO49 / TEMP_ALERT# is used to

alert for EC when CPU or Graph/Memory
controllers' temperature go out of limit.
So connecting GPIO49 to EC and avoid this
pin to be used for other purpose
AM3
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
AB12
F8
A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53
2dGPU_HOLD_RST#
U3
*EV@TC7SH08FU
R70
*EV@100K_4
GPIO15
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
M11
dGPU_PRSNT#
A20GATE
SIO_A20GATE <35>
TACH0 / GPIO17
STP_PCI#
dGPU_PWR_EN#
LAN_PHY_PWR_CTRL / GPIO12
U2
<4,10,25,27,31,35> PLTRST#
GPIO8
SATA4GP / GPIO16
Y7
<16>
AF48
AF47
F38
TP_PCH_GPIO28
TP16
<19,42> dGPU_VRON
CLKOUT_PCIE7N
CLKOUT_PCIE7P
AA2
H10
<9>
GPU_RST#
SCLOCK / GPIO22
GPIO24
PECI
RCIN#
GPIO27
CPU
RSV_GPIO8
*[email protected]_4
C137
AH45
AH46
TACH1 / GPIO1
GPIO28
PROCPWRGD
THRMTRIP#
BD10
PCH_THRMTRIP#_R R197
STP_PCI# / GPIO34
GPIO Pull-up/Pull-down
<35>
56/F_4
R200
+3V_S5
PM_THRMTRIP# <4>
56/F_4
+1.05V
TP_PCH_GPIO28
GPIO45
RST_GATE#
GPIO57
LAN_DISABLE#
SATACLKREQ# / GPIO35
SATA2GP / GPIO36
TP1
SATA3GP / GPIO37
TP2
SLOAD / GPIO38
TP3
SDATAOUT0 / GPIO39
TP4
TP5
TP6
SDATAOUT1 / GPIO48
TP7
SATA5GP / GPIO49
TP8
GPIO57
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
TP9
RSVD
<9>
RSV_GPIO8
CLKOUT_PCIE6N
CLKOUT_PCIE6P
<35> SIO_EXT_SMI#
TP2
+3V
BMBUSY# / GPIO0
MISC
Y3
GPIO
BMBUSY#
NCTF
TP31
EV@0_4
BA22
AY45
AY46
TP16
TP17
TP18
TP19
NC_1
M18
AK41
AK42
SAVE_LED#
STP_PCI#
R519
R228
10K_4
10K_4
GPIO38
R535
10K_4
BMBUSY#
R522
8.2K_4
SV_SET_UP
R241
10K_4
SV_SET_UP
M30
1-X High = Strong (Default)
N30
GPIO57 stuff PD and not stuff PU for Intel suggestion at 6/1
H12
GPIO57
AA23
R207
10K_4
AB45
AB42
TP24
10K_4
10K_4
*10K_4
10K_4
10K_4
N32
AB38
INIT3_3V#
R533
R520
R536
R537
R224
M32
NC_3
NC_5
SIO_RCIN#
SIO_A20GATE
dGPU_HOLD_RST#
SATA5GP
GPIO22
+3V
AF13
NC_2
NC_4
10K_4
10K_4
10K_4
*10K_4
AV45
AJ24
TP15
R146
R445
R223
R154
AV43
N18
TP14
SIO_EXT_SMI#
SIO_EXT_SCI#
dGPU_PWR_EN#
dGPU_PWROK
+3V
BB22
TP11
TP13
10K_4
10K_4
10K_4
*10K_4
10K_4
AW22
TP10
TP12
R239
R516
R515
R208
R231
+3V
AB41
R148
*10K_4
R238
IV@10K_4dGPU_PRSNT# R220
BOARD_ID0
R155
10K_4
EV@10K_4
dGPU always exist
T39
5/18 separate for 14" & 15"

P6
High = 15"
BOARD_ID0
C10
Low = 14"
IbexPeak-M_R1P0
High = Disable
RSV_GPIO8
Low = Enable

PROJECT : ZQ9
Size
Document Number
Date:
Rev
1A
IBEX PEAK-M 4/6

5
Sheet
1
11
of
45
1u/6.3V_4
VCCCORE(+1.05V) = 1.432A(80mils)
D
40mA(15mils)
R174
*SHORT0603
L49
+1.05V
+1.05V_PCH_VCCDPLL_EXP
*1uh_6
C629
+V1.1LAN_VCCAPLL_EXP
AK24
C289
C292
C305
C294
C282
10U/6.3V_8
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
AN30
AN31
R113
*SHORT0603
+3V_VCCA3GBG
R185
*SHORT0603
+VCCAFDI_VRM
R118
*1uH_6
AP43
AP45
AT46
AT45
BJ18
+1.05V_VCCDPLL_FDI
AM23
VCCVRM[1]
VCCFDIPLL
VCCIO[1]
C645
*10u/6.3V_6
+1.05V_VCCAUX
*0_6
AF23
AF24
SP@
UMA=CH31004KB17<0.01u>
MXM=CS00002JB38<0_ohm>
C300
1U/6.3V_4
VCCTX_LVDS= 59mA(15mils)
VCCTX_LVDS
L24
C256
C255
C248
[email protected]/25V_4
IV@22u/6.3V_8
[email protected]_8/250mA
+1.8V
TP_PCH_VCCDSW
C307
1u/6.3V_4
AD41
VCC3_3 = 357mA(30mils)
AB35
AD35
Y20
AD38
AD39
AB34
VCC3_3[4]
AP53
+3V_VCC_GIO
R417
*SHORT0603
AF43
VCCME(+1.05V) = 1.849A(100mils)
+3V
C279
+1.05V
.1u/16V_4
R140
*SHORT0805
R150
0_8
AF41
+1.05V_VCCEPW
AF42
V39
C257
22U/6.3V_8
V42
C269
22U/6.3V_8
Y39
C277
1U/6.3V_4
Y41
C278
1U/6.3V_4
Y42
VCCVRM= 196mA(15mils)
VCC3_3[1]
AT22
+V1.1LAN_VCCAPLL_FDI
R175
+1.05V
C482 change to 0 ohm resistor.
VCC3_3[3]
AP51
AT24
AT16
VCCDMI[1]
+VCCVRM
R178
+VCCDMI
R194
*SHORT0603
*Short_4
+V1.5S_1.8S
+1.05V
VCCDMI= 61mA(15mils)
C324
1u/10V_4
AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15
VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]
+VCCRTCEXT
0.1u/10V_4_X7R
C334
R210
*SHORT0805
+1.8V
+V1.1LAN_VCCA_A_DPL
68mA(15mils)
.1u/16V_4
+V1.1LAN_VCCA_B_DPL
69mA(15mils)
C288
C286
C273
VCCME3_3= 85mA(15mils)
+3V_VCCME_SPIR201
*SHORT0603
+3V
BD51
BD53
AH23
AJ35
AH35
VCCIO = 3.062A(150mils)
AM8
AM9
AP11
AP9
BB51
BB53
C319
+1.05V
VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]
V9
AU24
+V1.5S_1.8S
VCCPNAND= 156mA(15mils)
VCCPNAND
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCACLK[2]
VCCLAN[1]
VCCLAN[2]
DCPSUSBYP
VCCME[1]
VCCME[2]
VCCME[3]
VCCME[4]
VCCME[5]
VCCME[6]
VCCME[7]
VCCME[8]
VCCME[9]
VCCME[10]
VCCME[11]
VCCME[12]
AU16
VCCDMI[2]
POWER
VCCACLK[1]
VCCLAN = 320mA(30mils)
EV@0_4
AH39
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
FDI
L51
+3V
AH38
VCCALVDS
VCCVRM[2]
37mA(15mils)
+V1.5S_1.8S
IV@0_4
*10uh_8 +V1.1LAN_VCCA_CLK
C597
*10u/6.3V_6
C603
*1u/6.3V_4
L47
+1.05V
V41
VCCIO[54]
VCCIO[55]
AN35
U21J
VCCACLK= 52mA(15mils)
VCCALVDS= 1mA
VCC3_3[2]
+1.05V
+1.05V
[email protected]/25V_4 IV@10u/10V_6 [email protected]/10V_4_X7R

AF51
VSSA_DAC[2]
*10u/6.3V_6
+3V
VSSA_DAC[1]
VSSA_LVDS
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]
+3V
AF53
VCCAPLLEXP
AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27
L44
PBY160808T/2A/180ohm_6
6/14 change the P/N
C604
C572
C598
VCCALVDS R114
VCCIO[24]
BJ24
+VCCA_DAC_1_2
AE52
VCCADAC[2]
HVCMOS
+1.05V
AE50
VCCADAC[1]
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
C329
AF34
AH34
AF32
.1u/16V_4
V12
C325
+VCCSST
0.1u/10V_4_X7R
+V1.1LAN_INT_VCCSUS
0.1u/10V_4_X7R
Y22
C306
USB
10u/6.3V_8
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
3.3 V. This rail should be powered up during S0 system state.

Note that Thermal Sensor shares the same power supply rail with DAC.
The external filters on this pin are not needed in case internal graphic is
disabled so only 3.3-V connection is required.
DCPRTC
VCCVRM[3]
VCCADPLLA[1]
VCCADPLLA[2]
Clock and Miscellaneous
AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31
C283
CRT
C291
LVDS
+1.05V_VCCCORE_ICH
VCC CORE
*SHORT0805
DMI
*SHORT0805
R124
PCI E*
R116
VCCADAC= 69mA(15mils)
NAND / SPI
+1.05V
POWER
U21G
VCCADPLLB[1]
VCCADPLLB[2]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]
VCCSUS3_3[28]
VCCIO[56]
V5REF_SUS
V5REF
PCI/GPIO/LPC
IBEX PEAK-M (POWER)
VCC3_3[8]
VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCCIO[2]
VCC3_3[14]
V24
V26
Y24
Y26
+1.05V
C295
+3V_S5_VCCPUSB
V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26
C303
C290
C302
R172
+3V_S5
+1.05V
V5REF_SUS< 1mA
R468
D17
C639
100/F_4
+5V_S5
RB500V-40
+3V_S5
1U/6.3V_4
V5REF< 1mA
U23
R115
100/F_4
+5V
RB500V-40
+3V
V23
D4
V5REF_SUS
F24
C240
K49
V5REF
J38
+3V_VCCPPCI
R142
1U/6.3V_4
*SHORT0603 +3V
VCC3_3 = 0.357A(30mils)
L38
C261
0.1u/10V_4_X7R
C260
0.1u/10V_4_X7R
M36
N36
P36
U35
AD13
31mA(15mils)
VCCIO[4]
VCCSATAPLL[1]
VCCSATAPLL[2]
DCPSST
+V1.1LAN_VCCAPLL
AK3
AK1
L28
C668
*1u/6.3V_4
*10uh_8
+1.05V
C351
*10u/6.3V_6
DCPSUS
VCCIO[9]
*SHORT0603
AH22
+V1.1LAN_VCC_SATA
AT20
+V1.5S_1.8S
R526
*SHORT1206+1.05V
B
R213
*SHORT0603
+V1.5S_1.8S
C344
.1u/16V_4
C345
.1u/16V_4
R168
+3V_S5
*SHORT0603 +3V_S5_VCCPSUS
Internal weak pull-down

VCCVRM=>+1.8V (default)
external pull-up
VCCVRM=>+1.5V
U19
U20
C314
VRM enable by strap pin GPIO27

which supply clean 1.05V for
[VCCACLK,VCCAPLLEXP,VCCFDIPLL,VCCSATAPLL]
0.1u/10V_4_X7R U22
VCCSUS3_3[29]
VCCSUS3_3[30]
VCCSUS3_3[31]
VCCSUS3_3[32]
VCC3_3 = 0.357A(30mils)
R186
+3V
*SHORT0603 +3V_VCCPCORE
V15
V16
5/27 cost down

+1.05V
L45
C318
VCC3_3[6]
V_CPU_IO >1mA(15mils)
10uh_8
R198
VCC3_3[7]
+1.05V
R424
0_8
+V1.1LAN_VCCA_B_DPL
C601
C342
C338
C336
4.7U/6.3V_6
0.1u/10V_4_X7R
0.1u/10V_4_X7R
C664
C665
0.1u/10V_4_X7R
0.1u/10V_4_X7R
AT18
AU18
V_CPU_IO[1]
V_CPU_IO[2]
VCCRTC= 2mA(15mils)
A12
+VCCRTC
220u_3528
VCCRTC
IbexPeak-M_R1P0
VCCIO[11]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
0_6
+VTT_VCCPCPU
VCCIO[10]
VCCIO[12]
+V1.1LAN_VCCA_A_DPL
*10uh_8
+
C592
*220u_3528
L46
0.1u/10V_4_X7R Y16
VCC3_3[5]
VCCVRM[4]
VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]
HDA
+1.8V
HDA_SYNC (PCH strap pin)
SATA
VCCSUS3_3 = 163mA(20mils)
VCCVRM=196mA(15mils)
PCI/GPIO/LPC
P18
CPU
R169
*SHORT0805
*SHORT0603
VCCIO[3]
RTC
+1.05V
R162
0.1u/10V_4_X7R
0.1u/10V_4_X7R
0.022U/16V_4
VCCSUS3_3 = 0.163A(20mils)
IbexPeak-M_R1P0
1U/6.3V_4
VCCSUSHDA
C320
1u/10V_4
AH19
AD20
AF22
AD19
AF20
AF19
AH20
AB19
AB20
AB22
AD22
VCCME = 1.849A(100mils)
+1.05V_VCCEPW
AA34
Y34
Y35
AA35
L30
+V3.3A_1.5A_HDA_IO
R163
*Short_4
+3V_S5
VCCSUSHDA= 6mA(15mils)
C276
1u/10V_4

PROJECT : ZQ9
Size
Document Number
Rev
1A
IBEX PEAK-M 5/6

Date:
5
Sheet
1
12
of
45
U21I
IBEX PEAK-M (GND)

D
U21H
AB16
VSS[0]
AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
IbexPeak-M_R1P0
A
AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47
AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]
H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14
IbexPeak-M_R1P0

PROJECT : ZQ9
Size
Document Number
Rev
1A
IBEX PEAK-M 6/6

Date:
5
Sheet
1
13
of
45
+1.5VSUS
M_A_DQ[63:0] <5>
R270
R269
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
10K_4
10K_4
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_CS#0
M_A_CS#1
M_A_CLK0
M_A_CLK0#
M_A_CLK1
M_A_CLK1#
M_A_CKE0
M_A_CKE1
M_A_CAS#
M_A_RAS#
M_A_WE#
<3,15,27> CLK_SCLK
<3,15,27> CLK_SDATA
<5> M_A_ODT0
<5> M_A_ODT1
<5> M_A_DM[7:0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
DIMM0_SA0
DIMM0_SA1
CLK_SCLK
CLK_SDATA
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
116
120
ODT0
ODT1
11
28
46
63
136
153
170
187
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
<5> M_A_DQS[7:0]
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
<5> M_A_DQS#[7:0]
PC2100 DDR3 SDRAM SO-DIMM

(204P)
JDIM1A
<5> M_A_A[15:0]
M_A_DQ4
M_A_DQ0
M_A_DQ2
M_A_DQ3
M_A_DQ1
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ12
M_A_DQ13
M_A_DQ11
M_A_DQ10
M_A_DQ8
M_A_DQ9
M_A_DQ14
M_A_DQ15
M_A_DQ17
M_A_DQ20
M_A_DQ18
M_A_DQ19
M_A_DQ16
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ28
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ29
M_A_DQ31
M_A_DQ30
M_A_DQ36
M_A_DQ33
M_A_DQ35
M_A_DQ34
M_A_DQ32
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ45
M_A_DQ44
M_A_DQ47
M_A_DQ42
M_A_DQ41
M_A_DQ40
M_A_DQ46
M_A_DQ43
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ62
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ63
M_A_DQ58
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DDR3-DIMM1_H=8.0_Reverse
2.48A
+3V
M3 solution
<7> VREF_DQ_DIMM0
R266
*M3@0_6
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
199
VDDSPD
77
122
125
NC1
NC2
NCTEST
198
30
EVENT#
RESET#
+SMDDR_VREF_DQ0
1
+SMDDR_VREF_DIMM
126
+SMDDR_VREF_DIMM
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
+1.5VSUS
R276
*10K_4
VREF_DQ
VREF_CA
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
VTT1
VTT2
203
204
GND
GND
205
206
+0.75V_DDR_VTT
+SMDDR_VREF
R275
*SHORT0603+SMDDR_VREF_DIMM
R264
*10K_4
C403
470p/X7R_4
+1.5VSUS
M1 solution
+SMDDR_VREF
Place these Caps near So-Dimm0.
<4> PM_EXTTS#0
<4,15> DDR3_DRAMRST#
JDIM1B
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

(204P)
R268
R259
*10K/F_4
*SHORT0603+SMDDR_VREF_DQ0
R260
*10K/F_4
C380
470p/X7R_4
+1.5VSUS
+SMDDR_VREF_DIMM
C366
10u/6.3V_6
C381
10u/6.3V_6
C369
10u/6.3V_6
C377
.1u/16V_4
C387 5/27
.1u/16V_4
+ C367
C379
*330u/2V_7343
.1u/16V_4
C365
10u/6.3V_6
C391
10u/6.3V_6
C372
10u/6.3V_6
+3V
C370
.1u/16V_4
C371
.1u/16V_4
+SMDDR_VREF_DQ0
cost down
C376
.1u/16V_4
C378
C385
C383
.1u/16V_4
2.2u/6.3V_6
2.2u/6.3V_6
+0.75V_DDR_VTT
5/27 cost down

C397
2.2u/6.3V_6
C394
.1u/16V_4
C393
1U/6.3V_4
C375
1U/6.3V_4
C374
1U/6.3V_4
C389
1U/6.3V_4
C373
C396
C412
4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6
PROJECT : ZQ9
Size
Document Number
Rev
1A
DDRIII SO-DIMM-0
Date:
5
Sheet
1
14
of
45
M_B_DQ[63:0] <5>
JDIM2A
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
10K_4
10K_4
R295
R298
+3V
M_B_BS#0
M_B_BS#1
M_B_BS#2
M_B_CS#0
M_B_CS#1
M_B_CLK0
M_B_CLK0#
M_B_CLK1
M_B_CLK1#
M_B_CKE0
M_B_CKE1
M_B_CAS#
M_B_RAS#
M_B_WE#
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
116
120
ODT0
ODT1
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
11
28
46
63
136
153
170
187
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DIMM1_SA0
DIMM1_SA1
<3,14,27> CLK_SCLK
<3,14,27> CLK_SDATA
<5> M_B_ODT0
<5> M_B_ODT1
<5> M_B_DM[7:0]
<5> M_B_DQS[7:0]
<5> M_B_DQS#[7:0]
M_B_DQ5
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ0
M_B_DQ4
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ18
M_B_DQ17
M_B_DQ16
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ26
M_B_DQ25
M_B_DQ30
M_B_DQ27
M_B_DQ29
M_B_DQ24
M_B_DQ28
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ45
M_B_DQ47
M_B_DQ43
M_B_DQ44
M_B_DQ41
M_B_DQ46
M_B_DQ42
M_B_DQ48
M_B_DQ53
M_B_DQ50
M_B_DQ54
M_B_DQ52
M_B_DQ49
M_B_DQ51
M_B_DQ55
M_B_DQ60
M_B_DQ57
M_B_DQ63
M_B_DQ58
M_B_DQ59
M_B_DQ56
M_B_DQ62
M_B_DQ61
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

(204P)
<5> M_B_A[15:0]
5/26 change the footprint
+1.5VSUS
2.48A
+3V
<4> PM_EXTTS#1
<4,14> DDR3_DRAMRST#
M3 solution
R302
<7> VREF_DQ_DIMM1
*M3@0_6
+SMDDR_VREF_DQ1
+SMDDR_VREF_DIMM
+SMDDR_VREF
R299
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
199
VDDSPD
77
122
125
NC1
NC2
NCTEST
198
30
EVENT#
RESET#
1
126
VREF_DQ
VREF_CA
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
+1.5VSUS
M1 solution
JDIM2B
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
R301
*10K/F_4
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

(204P)
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
VTT1
VTT2
203
204
GND
GND
205
206
+0.75V_DDR_VTT
*SHORT0603+SMDDR_VREF_DQ1
R304
*10K/F_4
C452
470p/X7R_4
+1.5VSUS
Place these Caps near So-Dimm1.

+SMDDR_VREF_DIMM
C438
10u/6.3V_6
C435
10u/6.3V_6
C437
10u/6.3V_6
C434
.1u/16V_4
+ C450
C413
330u/2V_7343
.1u/16V_4
C439
10u/6.3V_6
C436
10u/6.3V_6
C408
10u/6.3V_6
+3V
C407
.1u/16V_4
+SMDDR_VREF_DQ1
C405
.1u/16V_4
C406
.1u/16V_4
C416
C440 C444
.1u/16V_4
C433
.1u/16V_4
2.2u/6.3V_6
2.2u/6.3V_6
+0.75V_DDR_VTT
5/27 for cost down

A
C443
2.2u/6.3V_6
C427
.1u/16V_4
C425
1U/6.3V_4
C414
1U/6.3V_4
C424
1U/6.3V_4
C415
1U/6.3V_4
C411
C421
4.7U/6.3V_6 4.7U/6.3V_6
C402
4.7U/6.3V_6

PROJECT : ZQ9
Size
Document Number
Rev
1A
DDRIII SO-DIMM-1
Date:
5
Sheet
1
15
of
45
GPU_1(VGA)
<4> PEG_TXP[0..15]
<4> PEG_TXN[0..15]
<4> PEG_RXP[0..15]
D
<4> PEG_RXN[0..15]
0518 SWAP PCIE for VGA side
PEG_TXN[0..15]
PEG_RXP[0..15]
PEG_RXN[0..15]
0518 SWAP PCIE for VGA side

<4> PEG_TXP15
<4> PEG_TXN15
<4> PEG_TXP14
<4> PEG_TXN14
<4> PEG_TXP13
<4> PEG_TXN13
<4> PEG_TXP12
<4> PEG_TXN12
<4> PEG_TXP10
<4> PEG_TXN10
<4>
<4>
PEG_TXP9
PEG_TXN9
<4>
<4>
PEG_TXP8
PEG_TXN8
<4>
<4>
PEG_TXP7
PEG_TXN7
<4>
<4>
PEG_TXP6
PEG_TXN6
<4>
<4>
PEG_TXP5
PEG_TXN5
<4>
<4>
PEG_TXP4
PEG_TXN4
<4>
<4>
PEG_TXP3
PEG_TXN3
<4>
<4>
PEG_TXP2
PEG_TXN2
<4>
<4>
PEG_TXP1
PEG_TXN1
<4>
<4>
PEG_TXP0
PEG_TXN0
PEG_TXP15
PEG_TXN15
AA38
Y37
PCIE_TX0P
PCIE_TX0N
Y33
Y32
CPEG_RXP15
CPEG_RXN15
C116
C107
PEG_TXP14
PEG_TXN14
Y35
W36
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
W33
W32
CPEG_RXP14
CPEG_RXN14
C122
C117
PEG_TXP13
PEG_TXN13
W38
V37
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
U33
U32
CPEG_RXP13
CPEG_RXN13
C126
C123
PEG_TXP12
PEG_TXN12
V35
U36
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
U30
U29
CPEG_RXP12
CPEG_RXN12
C127
C135
PEG_TXP11
PEG_TXN11
U38
T37
PCIE_RX4P
PCIE_RX4N
PCIE_TX4P
PCIE_TX4N
T33
T32
CPEG_RXP11
CPEG_RXN11
C136
C151
PEG_TXP10
PEG_TXN10
T35
R36
PCIE_RX5P
PCIE_RX5N
PCIE_TX5P
PCIE_TX5N
T30
T29
CPEG_RXP10
CPEG_RXN10
C150
C159
PEG_TXP9
PEG_TXN9
R38
P37
PCIE_RX6P
PCIE_RX6N
PCIE_TX6P
PCIE_TX6N
P33
P32
CPEG_RXP9
CPEG_RXN9
C160
C172
PEG_TXP8
PEG_TXN8
P35
N36
PCIE_RX7P
PCIE_RX7N
PCIE_TX7P
PCIE_TX7N
P30
P29
CPEG_RXP8
CPEG_RXN8
C181
C180
PEG_TXP7
PEG_TXN7
N38
M37
PCIE_RX8P
PCIE_RX8N
PCIE_TX8P
PCIE_TX8N
N33
N32
CPEG_RXP7
CPEG_RXN7
C190
C189
PEG_TXP6
PEG_TXN6
M35
L36
PCIE_RX9P
PCIE_RX9N
PCIE_TX9P
PCIE_TX9N
N30
N29
CPEG_RXP6
CPEG_RXN6
C198
C197
PEG_TXP5
PEG_TXN5
L38
K37
PCIE_RX10P
PCIE_RX10N
PCIE_TX10P
PCIE_TX10N
L33
L32
CPEG_RXP5
CPEG_RXN5
C207
C206
PEG_TXP4
PEG_TXN4
K35
J36
PCIE_RX11P
PCIE_RX11N
PCIE_TX11P
PCIE_TX11N
L30
L29
CPEG_RXP4
CPEG_RXN4
C205
C204
PEG_TXP3
PEG_TXN3
J38
H37
PCIE_RX12P
PCIE_RX12N
PCIE_TX12P
PCIE_TX12N
K33
K32
CPEG_RXP3
CPEG_RXN3
C202
C203
PEG_TXP2
PEG_TXN2
H35
G36
PCIE_RX13P
PCIE_RX13N
PCIE_TX13P
PCIE_TX13N
J33
J32
CPEG_RXP2
CPEG_RXN2
C212
C213
PEG_TXP1
PEG_TXN1
G38
F37
PCIE_RX14P
PCIE_RX14N
PCIE_TX14P
PCIE_TX14N
K30
K29
CPEG_RXP1
CPEG_RXN1
C209
C208
PEG_TXP0
PEG_TXN0
F35
E37
PCIE_RX15P
PCIE_RX15N
PCIE_TX15P
PCIE_TX15N
H33
H32
CPEG_RXP0
CPEG_RXN0
C211
C210
PCIE_RX0P
PCIE_RX0N
PCI EXPRESS INTERFACE
<4> PEG_TXP11
<4> PEG_TXN11
U15A
PEG_TXP[0..15]
PEG_RXP15 <4>
PEG_RXN15 <4>
PEG_RXP14 <4>
PEG_RXN14 <4>
PEG_RXP13 <4>
PEG_RXN13 <4>
PEG_RXP12 <4>
PEG_RXN12 <4>
PEG_RXP11 <4>
PEG_RXN11 <4>
PEG_RXP10 <4>
PEG_RXN10 <4>
PEG_RXP9 <4>
PEG_RXN9 <4>
PEG_RXP8 <4>
PEG_RXN8 <4>
PEG_RXP7 <4>
PEG_RXN7 <4>
PEG_RXP6 <4>
PEG_RXN6 <4>
PEG_RXP5 <4>
PEG_RXN5 <4>
PEG_RXP4 <4>
PEG_RXN4 <4>
PEG_RXP3 <4>
PEG_RXN3 <4>
PEG_RXP2 <4>
PEG_RXN2 <4>
PEG_RXP1 <4>
PEG_RXN1 <4>
PEG_RXP0 <4>
PEG_RXN0 <4>
CLOCK
AB35
AA36
<10> CLK_PCIE_VGA
<10> CLK_PCIE_VGA#
For Broadway, Madison and Park

the PWRGOOD ball must be conneccted to ground
R52
<11> GPU_RST#
EV@10K_4
PCIE_REFCLKP
PCIE_REFCLKN
CALIBRATION
AJ21
AK21
AH16
NC#1
NC#2
PWRGOOD
AA30
PERSTB
PCIE_CALRP
Y30
R72
[email protected]/F_4
PCIE_CALRN
Y29
R74
EV@2K/F_4
+1V
Madison
AJ007720T02
Park
AJ077400T08
A
+1.0V
For M97, Broadway, Madison and Park PCIE_VDDC is 1.0V
EV@Park_M2
PROJECT : ZQ9
Size
Document Number
Rev
1A
Madison/Park M2-PCIE I/F

Date:
5
Sheet
1
16
of
45
U15B
GPU_2(VGA)
U15G
TXCAP_DPA3P
TXCAM_DPA3N
TX0P_DPA2P
TX0M_DPA2N
MUTI GFX
DPA
TX1P_DPA1P
TX1M_DPA1N
AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
NC on Park
GPU Power-on sequence
<21> RAM_STRAP0
<21> RAM_STRAP1
<21> RAM_STRAP2
1 => MAINON
2 => +VGPU_CORE
3 => +1V
4 => +1.5V_GPU
5 => +1.8V_GPU
6 => GPU_RST#
T32
1.8V GPIO
NC on Park
+3V_D
DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
DPB
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N
TX0P_DPC2P
TX0M_DPC2N
DPC
TX1P_DPC1P
TX1M_DPC1N
TX2P_DPC0P
TX2M_DPC0N
TXCDP_DPD3P
TXCDM_DPD3N
TX3P_DPD2P
TX3M_DPD2N
DPD
R47
EV@10K_4
R49
EV@10K_4
TX4P_DPD1P
TX4M_DPD1N
I2C
AK26
AJ26
TX5P_DPD0P
TX5M_DPD0N
1/21 ramp remove IO_VID0

<23> EV_LVDS_BLON
5/17 change to test pad
+3V_D
<21> GPU_GPIO11
<21> GPU_GPIO12
<21> GPU_GPIO13
R347
3.3V GPIO
T33
T35
<42>
*EV@10K_4
VID1
<21> ALT#_GPIO17
<42>
+3V_D
VID2
R352
5/17 change to test pad
T34
5/17 delete workaround
EV@10K_4
R358
*EV@10K/F_4
<3>
27M_CLK
+3V_D
5/17 delete
27M_CLK
*EV@10K_4
R41
D3D
R359
B
*EV@10K/F_4
<24> HDMI_HP_EV
AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
AK24
+1.8V_GPU
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF
GENERICG
G
GB
B
BB
DAC1
HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
R2
R2B
G2
G2B
B2
B2B
C
Y
COMP
AU26
AV25
HDMITX1P <24>
HDMITX1N <24>
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
AT27
AR26
HDMITX2P <24>
HDMITX2N <24>
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
AR30
AT29
AK27
AJ27
VARY_BL
DIGON
AJ38
AK37
AG38
AH37
AF35
AG36
TXOUT_U3P
TXOUT_U3N
AT33
AU32
AH35
AJ36
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
AR32
AT31
<23>
<23>
AK35
AL36
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
AV31
AU30
EV_LVDS_BRIGHT
EV_LVDS_VDDEN
LVTMDP
AU14
AV13
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
AT15
AR14
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
AU16
AV15
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
AT17
AR16
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
AU20
AT19
AP34
AR34
EV_TXLCLKOUT+ <23>
EV_TXLCLKOUT- <23>
AW37
AU35
EV_TXLOUT0+ <23>
EV_TXLOUT0- <23>
AR37
AU39
EV_TXLOUT1+ <23>
EV_TXLOUT1- <23>
AP35
AR35
EV_TXLOUT2+ <23>
EV_TXLOUT2- <23>
AN36
AP37
TXOUT_L3P
TXOUT_L3N
AT21
AR20
Channel D N.C for Park-M2
AU22
AV21
EV@Park_M2
AT23
AR22
AD39
AD37
EV_CRT_RED
AE36
AD35
EV_CRT_GRN
<23>
AF37
AE38
EV_CRT_BLU
<23>
AC36
AC38
AB34
EV_HSYNC
EV_VSYNC
R71
<21,23>
<21,23>
R60
EV@150/F_4
R62
EV@150/F_4
<23>
R65
EV@150/F_4
EV@499/F_4
AD34
AE34
AVDD
AC33
AC34
VDD1DI
+1.8V_GPU
(1.8V@70mA AVDD)
AVDD
AC30
AC31
R67
EV@0_4
AD30
AD31
R56
EV@0_4
AF30
AF31
R57
EV@0_4
L16
C99
C89
EV@1u/6.3V_4
EV@SBY100505T-121Y-N/300mA/120ohm_4
C90
EV@10u/6.3V_6
(1.8V@100mA VDD1DI)
VDD1DI
AC32
AD32
AF32
L15
C72
DAC2 will be NC on future ASIC
C75
EV@1u/6.3V_4
EV@SBY100505T-121Y-N/300mA/120ohm_4
C70
EV@10u/6.3V_6
H2SYNC
V2SYNC
HPD1
A2VDD
A2VDDQ
VREFG
A2VSSQ
C60
R35
EV@249/F_4
HDMITX0P <24>
HDMITX0N <24>
DAC2
R29
EV@499/F_4
AH13
HDMICLK+ <24>
HDMICLK- <24>
AT25
AR24
R
RB
VDD2DI
VSS2DI
VREFG
LVDS CONTROL
AU24
AV23
SCL
SDA
GENERAL PURPOSE I/O
<21> GPU_GPIO0
<21> GPU_GPIO1
<21> GPU_GPIO2
<21> GPIO3_SMBDAT
<21> GPIO4_SMBCLK
R2SET
AD29
AC29
T4
AG31
AG32
VDD1DI
R58
EV@0_4
V2SYNC
R59
AG33
AD33
EV@0_4
+3V_D
(3.3V@130mA A2VDD)
A2VDDQ
C80
AF33
AA29
<21>
R69
EV@715/F_4
+1.8V(75mA)
+1.8V_GPU
L12
DPLL_PVDD
EV@SBY100505T-121Y-N/300mA/120ohm_4
C57
EV@10u/6.3V_6
C58
EV@1u/6.3V_4
DDC/AUX
5/13 add for cost down solution
C65
<3> 27M_CLK_SS
C502
EV@SBY100505T-121Y-N/300mA/120ohm_4
C50
C62
EV@10u/6.3V_6
EV@1u/6.3V_4
+1.8V(5mA)
L14
EV@SBY100505T-121Y-N/300mA/120ohm_4
C63
C71
EV@10u/6.3V_6
Y3
EV@27MHZ
C501
XTALI_27M
XTALO_27M
R360
EV@1M/F_4
AV33
AU34
AUX1P
AUX1N
DPLL_VDDC
DDC2CLK
DDC2DATA
XTALIN
XTALOUT
AUX2P
AUX2N
DDCCLK_AUX3P
DDCDATA_AUX3N
EV@27p/50V_4
<21>
<21>
+1.8V_GPU
AN31
EV@27p/50V_4
DPLL_VDDC
C41
DPLL_VDDC
TS_VDD
DDC1CLK
DDC1DATA
DPLL_PVDD
DPLL_PVSS
L9
AM32
AN32
*EV@0_4
+1.0V(125mA)
+1V
R357
PLL/CLOCK
DPLL_PVDD
AF29
AG29
GPU_D+
GPU_DT36
TS_VDD
AK32
AJ32
AJ33
DPLUS
DMINUS
THERMAL
DDCCLK_AUX4P
DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N
TS_FDO
TSVDD
TSVSS
DDC6CLK
DDC6DATA
NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N
AM26
AN26
MXM_DDCCK <24>
MXM_DDCDAT <24>
HDMI
+1.8V_GPU
AM27
AL27
(1.8V@2mA A2VDDQ)
A2VDDQ
AM19
AL19
C100
AN20
AM20
AL30
AM30
EV@SBY100505T-121Y-N/300mA/120ohm_4
C103
EV@1u/6.3V_4
T2
AL29
AM29
AN21
AM21
EV_LVDS_DDCCLK
EV_LVDS_DDCDAT
AJ30
AJ31
EV_CRTDCLK
EV_CRTDDAT
AK30
AK29
L41
<23>
<23>
<23>
<23>
DDC AUX4 NC for Park_M2

LVDS
CRT
DDC AUX7 NC for Park_M2

EV@Park_M2
PROJECT : ZQ9
Size
Document Number
Rev
1A
Madison/Park M2-HOST I/F

Date:
5
Sheet
1
17
of
45
GPU_3(VGA)
Park M2-channel B used(S3 package use Channel A)
+1.5V_GPU
R83
MVREFDA
R84
EV@100/F_4
C200
+1.5V_GPU
R81
MVREFSA
R82
EV@100/F_4
C199
+1.5V_GPU
R80
EV@243/F_4
R79
EV@243/F_4
R53
EV@243/F_4
R77
EV@243/F_4
R78
R51
EV@243/F_4
EV@243/F_4
Note by AN_M96_C1
6/9 stuff all for Park by AMD's suggestion
MVREFDA
MVREFSA
L18
L20
L27
N12
AG12
M12
M27
AH12
MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0
MAA1_7/MAA_A15_BA1
WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7
GDDR5/DDR2/GDDR3
EDCA0_0/QSA_0/RDQSA_0
DDBIA0_0/QSA_0B/WDQSA_0
ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1
MVREFDA
MVREFSA
CKEA0
CKEA1
MEM_CALRN0
MEM_CALRN1
MEM_CALRN2
WEA0B
WEA1B
GDDR5
DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63
MEMORY INTERFACE A
C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5
DDR2
GDDR5/GDDR3
DDR3
MEM_CALRP1
MEM_CALRP0
MEM_CALRP2
MAA0_8
MAA1_8
<22> VMB_RDQS[7..0]
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
<22> VMB_WDQS[7..0]
<22> VMB_MA[13..0]
<22>
<22>
<22>
VMB_DQ[63..0]
VMB_DM[7..0]
U15D
DDR2
GDDR3/GDDR5
DDR3
VMB_RDQS[7..0]
VMB_WDQS[7..0]
VMB_DQ0
VMB_DQ1
VMB_DQ2
VMB_DQ3
VMB_DQ4
VMB_DQ5
VMB_DQ6
VMB_DQ7
VMB_DQ8
VMB_DQ9
VMB_DQ10
VMB_DQ11
VMB_DQ12
VMB_DQ13
VMB_DQ14
VMB_DQ15
VMB_DQ16
VMB_DQ17
VMB_DQ18
VMB_DQ19
VMB_DQ20
VMB_DQ21
VMB_DQ22
VMB_DQ23
VMB_DQ24
VMB_DQ25
VMB_DQ26
VMB_DQ27
VMB_DQ28
VMB_DQ29
VMB_DQ30
VMB_DQ31
VMB_DQ32
VMB_DQ33
VMB_DQ34
VMB_DQ35
VMB_DQ36
VMB_DQ37
VMB_DQ38
VMB_DQ39
VMB_DQ40
VMB_DQ41
VMB_DQ42
VMB_DQ43
VMB_DQ44
VMB_DQ45
VMB_DQ46
VMB_DQ47
VMB_DQ48
VMB_DQ49
VMB_DQ50
VMB_DQ51
VMB_DQ52
VMB_DQ53
VMB_DQ54
VMB_DQ55
VMB_DQ56
VMB_DQ57
VMB_DQ58
VMB_DQ59
VMB_DQ60
VMB_DQ61
VMB_DQ62
VMB_DQ63
VMB_MA[13..0]
VMB_BA0
VMB_BA1
VMB_BA2
VMB_BA0
VMB_BA1
VMB_BA2
A32
C32
D23
E22
C14
A14
E10
D9
C34
D29
D25
E20
E16
E12
J10
D7
A34
E30
E26
C20
C16
C12
J11
F8
J21
G19
H27
G27
J14
H14
K23
K19
K20
K17
+1.5V_GPU
K24
K27
M13
K16
R61
K21
J20
MVREFDB
MVREFSB
K26
L15
R66
EV@100/F_4
H23
J19
C102
+3V_D
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
Y12
AA12
DDR2
GDDR5/GDDR3
DDR3
DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63
MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1
WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
DDBIB0_0/QSB_0B/WDQSB_0
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1
MVREFDB
MVREFSB
WEB0B
WEB1B
D3D
R46
R63
*EV@10K_4
EV@10K_4 AD28
AK10
AL10
GDDR5
<22> VMB_DM[7..0]
MEMORY INTERFACE B
<22> VMB_DQ[63..0]
U15C
DDR2
GDDR3/GDDR5
DDR3
TESTEN
CLKTESTA
CLKTESTB
MAB0_8
MAB1_8
DRAM_RST
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_BA2
VMB_BA0
VMB_BA1
H3
H1
T3
T5
AE4
AF5
AK6
AK5
VMB_DM0
VMB_DM1
VMB_DM2
VMB_DM3
VMB_DM4
VMB_DM5
VMB_DM6
VMB_DM7
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
VMB_RDQS0
VMB_RDQS1
VMB_RDQS2
VMB_RDQS3
VMB_RDQS4
VMB_RDQS5
VMB_RDQS6
VMB_RDQS7
QSB[7..0]
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
VMB_WDQS0
VMB_WDQS1
VMB_WDQS2
VMB_WDQS3
VMB_WDQS4
VMB_WDQS5
VMB_WDQS6
VMB_WDQS7
QSB#[7..0]
T7
W7
VMB_ODT0 <22>
VMB_ODT1 <22>
L9
L8
VMB_CLKP0
VMB_CLKN0
AD8
AD7
VMB_CLKP1
VMB_CLKN1
T10
Y10
VMB_RAS0#
VMB_RAS1#
W10
AA10
VMB_CAS0#
VMB_CAS1#
P10
L10
VMB_CS0#
AD10
AC10
VMB_CS1#
U10
AA11
VMB_CKE0
VMB_CKE1
N10
AB11
VMB_WE0#
VMB_WE1#
T8
W8
VMB_MA13
AH11
R37
VMB_CLKP0
VMB_CLKN0
<22>
<22>
VMB_CLKP1 <22>
VMB_CLKN1 <22>
VMB_RAS0#
VMB_RAS1#
<22>
<22>
VMB_CAS0#
VMB_CAS1#
<22>
<22>
VMB_CS0#
<22>
VMB_CS1#
<22>
VMB_CKE0
VMB_CKE1
<22>
<22>
VMB_WE0#
VMB_WE1#
<22>
<22>
EV@10/F_4
R36
EV@51_4
MEM_RST# <22>
B
+1.5V_GPU
AL31
R31
*EV@0_4
RSVD
EV@Park_M2
R68
R32
*EV@0_4
R50
[email protected]_4
C45
EV@120P/50V_4
EV@Park_M2
5/17 Change the design
Place all these components very close to GPU

R55
EV@100/F_4
C82

PROJECT : ZQ9
Size
Document Number
Rev
1A
Madison/Park M2-MEM I/F

Date:
5
Sheet
1
18
of
45
GPU_4(VGA)
U15F
U15E
For DDR3, MVDDQ = 1.5V (7.5A)
MEM I/O
+1.5V_GPU
+1.8V_GPU
PCIE
C195
C179
C194
C59
C148
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
C176
C141
C18
C64
C86
C184
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
C191
C183
C144
C171
C192
C177
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
C145
C186
C175
C170
C185
EV@1u/6.3V_4
C32
C81
C91
EV@10u/6.3V_6
EV@1u/6.3V_4
AF26
AF27
AG26
AG27
+3V_D
C68
C76
C83
C73
EV@10u/6.3V_6
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
AF23
AF24
AG23
AG24
AF13
AF15
AG13
AG15
EV@SBY100505T-121Y-N/300mA/120ohm_4 VDDR4
C87
C97
EV@1u/6.3V_4
PCIE_PVDD
AD12
AF11
AF12
AG11
M20
M21
R371
*EV@0_4
V12
U12
PCIE_VDDR
PCIE_PVDD
EV@SBY100505T-121Y-N/300mA/120ohm_4
MPV18
(1.8V@150mA MPV18)
AM10
SPV10
EV@SBY100505T-121Y-N/300mA/120ohm_4
AN9
AN10
C201
C196
C193
EV@10u/6.3V_6
EV@1u/6.3V_4
T1
AF28
AG28
T3
120 ohm/300mA
(1.0V@120mA SPV10)
EV@SBY100505T-121Y-N/300mA/120ohm_4
C46
C53
EV@10u/6.3V_6
+1V
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
([email protected] PCIE_VDDC)
C158
C167
C182
C187
C138
C178
C161
C188
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@10u/6.3V_6
+VGPU_CORE
(30A or more)
CORE
VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
C154
C147
C120
C118
C153
C92
C98
C157
C156
C108
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
C106
C110
C112
C88
C95
C131
C134
C109
C124
C139
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
C111
C130
C113
C129
C164
C128
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
BIF_VDDC should be connected to VDDC if BACO feature not used.

For BACO, refer to the databook
PIN different between Broadway and Madison
SPV10
SPVSS
AH29
FB_VDDC
FB_VDDCI
FB_GND
Broadway
Madison
N27
VDDC
BIF_VDDC
AL31
TS_A
NC_TS_A
AL21
GND
PX_EN
VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
ISOLATED VDDCI#15
CORE I/O VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13
C162
C119
C152
C169
C104
C163
C165
C155
C166
C168
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
+3V
C93
C174
C132
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
R54
EV@0_6
EV@Park_M2
C66
C78
Fine-tune Power-on sequence
<11,42> dGPU_VRON
R26
*EV@0_4
R22
*EV@0_4
5/24 stuff
VSS_MECH#1
VSS_MECH#2
VSS_MECH#3
A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
AW34
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13
PowerXpress control signal for Madsion and Park only

If not used, can be disconnected.
PX_EN = LOW, turn on
PX_EN = HIGH, turn off
PX_EN is used to turn ON/OFF some
regulators for PowerXpress mode. An
output high 3.3V will turn the regulators
OFF. An output low 0V will turn the
regulators ON. PX_EN outputs low (0V)
by default.
If this signal is unused, it can be NC (not
connected) or connected to ground.
R21
*EV@0_4
+3V_D
R15
*EV@0_4
Pin AL21 to Ground for Broadway
A39
AW1
AW39
*EV@AO3413
Q2
0.5A
+3V_D
C24
C30
*EV@1u/6.3V_4
B-test
Q1
*EV@DTC144EUA
R343
*EV@0_6
R23
EV@0_6
C3C
Spec: 0.15A
Rating: 3A
GND
GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162
GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98
GND#99
EV@Park_M2
0.5A
C69
+3V
R40
5/13 change the enable signal
<35,39,40,43> MAINON
Q8
EV@DTC144EUA
+3V
GPU +3V power
Q7
EV@2N7002K
*EV@AO3413
Q3
*EV@10u/6.3V_6
*[email protected]/10V_4
*EV@1u/6.3V_4
dGPU_PWROK <11>
R363
EV@10K_4
5/24 stuff
+3V_D_S
VDDC_SENSE/VSS_SENSE and
VDDCI_SENSE/VSS_SENSE route as differetial pair
R361
EV@10K_4
+1.8V_GPU
Pin
+3V
GPU all PWROK
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13
(DDR3 1.12V@4A VDDCI) or more
SPV18
PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35
C77
C74
C96
C114
C79
C85
C94
C133
C105
C84
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
L10
MPV18#1
MPV18#2
EV@SBY100505T-121Y-N/300mA/120ohm_4
C44
C56
EV@10u/6.3V_6
+1V
PCIE_PVDD
VOLTAGE
SENESE
(1.8V@75mA SPV18)
L7
NC_VDDRHB
NC_VSSRHB
AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39
EV@HCB1608KF-181T15/1.5A/180ohm_6
C115
C523
C121
C125
C101
C522
C526
C518
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@10u/6.3V_6
+1.8V_GPU
NC_VDDRHA
NC_VSSRHA
L43
+VGPU_CORE
SPV18
L17
AB37
H7
H8
C515
C519
C520
EV@10u/6.3V_6
EV@1u/6.3V_4
+1.8V_GPU
VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6
PLL
(1.8V@40mA PCIE_PVDD)
L42
VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8
(1.8V@400mA PCIE_VDDR)
PCIE_VDDR
C26
C31
+1.8V_GPU
B
VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4
AA31
AA32
AA33
AA34
V28
W29
W30
Y31
L6
VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4
I/O
(3.3V@60mA))
+1.8V_GPU
PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12
POWER
VDDC_CT
EV@SBY100505T-121Y-N/300mA/120ohm_4
PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
LEVEL
TRANSLATION
(1.8V@110mA VDD_CT)
L5
+1.8V_GPU
VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34
AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7
Spec: 0.15A
Rating: 3A
PROJECT :ZQ9
*EV@10u/6.3V_6
*EV@1u/6.3V_4
Size
Document Number
Rev
1A
Madison/Park M2 (PWR/GND)
Date:
5

1
Sheet
19
of
45
GPU_5(VGA)
+1V
U15H
DPA_VDD10
DP C/D POWER
(1.0V@110mA DPA_VDD10)
L11
EV@SBY100505T-121Y-N/300mA/120ohm_4
DP A/B POWER
DPA_VDD18
AP20
AP21
DPC_VDD18#1
DPC_VDD18#2
DPA_VDD18#1
DPA_VDD18#2
AN24
AP24
DPA_VDD18
DPA_VDD10
AP13
AT13
DPC_VDD10#1
DPC_VDD10#2
DPA_VDD10#1
DPA_VDD10#2
AP31
AP32
DPA_VDD10
AN17
AP16
AP17
AW14
AW16
DPC_VSSR#1
DPC_VSSR#2
DPC_VSSR#3
DPC_VSSR#4
DPC_VSSR#5
DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5
AN27
AP27
AP28
AW24
AW26
AP22
AP23
DPD_VDD18#1
DPD_VDD18#2
DPB_VDD18#1
DPB_VDD18#2
AP25
AP26
DPA_VDD18
AP14
AP15
DPD_VDD10#1
DPD_VDD10#2
DPB_VDD10#1
DPB_VDD10#2
AN33
AP33
DPA_VDD10
AN19
AP18
AP19
AW20
AW22
DPD_VSSR#1
DPD_VSSR#2
DPD_VSSR#3
DPD_VSSR#4
DPD_VSSR#5
DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5
AN29
AP29
AP30
AW30
AW32
DPCD_CALR
DPAB_CALR
AW28
C47
C55
C49
EV@10u/6.3V_6
EV@1u/6.3V_4
+1.8V_GPU
(1.8V@130mA DPA_VDD18)
L2
EV@SBY100505T-121Y-N/300mA/120ohm_4
DPA_VDD18
C43
C35
C51
EV@10u/6.3V_6
EV@1u/10V_6
DPA_VDD18
DPE_VDD18
R28
R34
*EV@0_4
DPA_PVDD
DPC_PVDD
R25
DPA_VDD18
DPA_VDD10
R27
EV@150/F_4 DPCD_CALR AW18
AH34
AJ34
DP E/F POWER
DPE_VDD18#1
DPE_VDD18#2
DP PLL POWER
DPA_PVDD
DPA_PVSS
AU28
AV27
DPE_VDD10
AL33
AM33
DPE_VDD10#1
DPE_VDD10#2
DPB_PVDD
DPB_PVSS
AV29
AR28
AN34
AP39
AR39
AU37
AW35
DPE_VSSR#1
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5
DPC_PVDD
DPC_PVSS
AU18
AV17
*EV@0_4
DPE_PVDD
R33
*EV@0_4
DPB_PVDD
*EV@0_4
DPD_PVDD
DPAB_CALR R351
EV@150/F_4
+1.8V_GPU
(1.8V@20mA DPA_PVDD)
DPA_PVDD
DPE_VDD18
R366
*EV@0_4
L3
EV@SBY100505T-121Y-N/300mA/120ohm_4
C29
C38
C40
EV@10u/6.3V_6
EV@1u/6.3V_4
+1.8V_GPU
+1.8V_GPU
L40
(1.8V@400mA DPE/F_VDD18)
EV@HCB1608KF-181T15/1.5A/180ohm_6
DPE_VDD18
+1V
AF34
AG34
(1.0V@400mA DPE/F_VDD10)
180 ohm/1.5A
L13
EV@HCB1608KF-181T15/1.5A/180ohm_6
DPE_VDD10
AK33
AK34
C54
C67
C48
EV@10u/6.3V_6
EV@1u/6.3V_4
AF39
AH39
AK39
AL34
AM34
R362
EV@150/F_4 DPEF_CALR AM39
EV@SBY100505T-121Y-N/300mA/120ohm_4
C25
C28
C34
EV@10u/6.3V_6
EV@1u/6.3V_4
+1.8V_GPU
DPC_PVDD
(1.8V@20mA DPC_PVDD)
L8
DPD_PVDD
DPD_PVSS
AV19
AR18
DPE_PVDD
DPE_PVSS
AM37
AN38
NC_DPF_PVDD
NC_DPF_PVSS
AL38
AM35
DPF_VDD18#1
DPF_VDD18#2
DPE_VDD10
(1.8V@20mA DPB_PVDD)
L4
DPE_VDD18
C511
C509
C510
EV@10u/6.3V_6
EV@1u/6.3V_4
DPB_PVDD
DPF_VDD10#1
DPF_VDD10#2
DPF_VSSR#1
DPF_VSSR#2
DPF_VSSR#3
DPF_VSSR#4
DPF_VSSR#5
EV@SBY100505T-121Y-N/300mA/120ohm_4
C36
C37
C503
EV@10u/6.3V_6
EV@1u/6.3V_4
+1.8V_GPU
DPD_PVDD
(1.8V@20mA DPD_PVDD)
L38
EV@SBY100505T-121Y-N/300mA/120ohm_4
C494
C504
C495
EV@10u/6.3V_6
EV@1u/6.3V_4
+1.8V_GPU
EV@SBY100505T-121Y-N/300mA/120ohm_4
(1.8V@40mA DPE/F_PVDD)
DPE_PVDD
L39
C507
C505
C508
EV@10u/6.3V_6
EV@1u/6.3V_4
A
DPEF_CALR
EV@Park_M2

PROJECT : ZQ9
Size
Document Number
Rev
1A
<Doc>
Date:
5
Sheet
1
20
of
45
PIN STRAPS(VGA)
CONFIGURATION STRAPS
+3V_D
<17> GPU_GPIO0
<17> GPU_GPIO1
R42
*EV@10K_4
R39
*EV@10K_4
Size of the primary memory apertures GPIO[13:11]
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
STRAPS
128 MB
000
256MB
001
64 MB
010
32 MB
011
PIN
TX_PWRS_ENB
GPIO0
TX_DEEMPH_EN
GPIO1
DESCRIPTION OF DEFAULT SETTINGS
DEFAULT
0 = 50% TX OUTPUT SWING

1 = FULL TX OUTPUT SWING
<17> GPIO3_SMBDAT
<17> GPIO4_SMBCLK
R45
*EV@10K_4
R48
*EV@10K_4
BIOS_ROM_EN
GPIO_22_ROMCSB
5/17 Change for ROM table

<17> GPU_GPIO13
<17> GPU_GPIO12
<17> GPU_GPIO11
<17> GPU_GPIO2
<17,23> EV_HSYNC
<17,23> EV_VSYNC
<17>
V2SYNC
R24
*EV@10K_4
R20
*EV@10K_4
R30
EV@10K_4
R38
*EV@10K_4
R368
EV@10K_4
R367
EV@10K_4
R356
*EV@10K_4
More than 512 MB
ROMIDCFG[2:0]
Not Supported
GPIO[13:11]
BIF_GEN2_EN_A
GPIO2
GPIO_8_ROMSO
H2SYNC
GPIO_21_BB_EN
GPIO8
H2SYNC
GPIO21
AUD[1]
HSYNC
AUD[0]
VSYNC
REMARK
PCIE TRANSMITTER DE-EMPHASIS ENABLED

0 = TX DE-EMPHASIS DISABLED
1 = TX DE-EMPHASIS ENABLED
Enable external BIOS ROM device

0 - Disable external BIOS ROM device
1 - Enable external BIOS ROM device
SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT
001
0 = PCIE DEVICE AS 2.5GT/S CAPABLE

1 = PCIE DEVICE AS 5GT/S CAPABLE
Reserved Only
AUD[1:0]
00: NO AUDIO FUNCTION.
01: AUDIO FOR DISPLAYPORT AND HDMI IF
ADAPTER IS DETECTED.
10: AUDIO FOR DISPLAYPORT ONLY.
11
See ROM table
See Audio table
11: AUDIO FOR BOTH DISPLAYPORT AND HDMI.

GPIO_9_ROMSI
0 = VGA controller capacity enable
GPIO9
VIP_DEVICE_STRAP_ENA
EEPROM(VGA) 5/17 delete EEPROM
V2SYNC
0 = DRIVER would ignore the value sample on VHAD_0 during RESET.
DDR3 Memory Aperture size(GPU)
DDR3 Memory size

Vendor
Hynix
Vendor P/N
STN B/S P/N
RAM_STRAP2
RAM_STRAP1
RAM_STRAP0
DVPDATA_2
DVPDATA_1
DVPDATA_0
H5TQ1G63BFR-12C
AKD5LZGTW04 (64M*16)
H5TQ2G63BFR-12C
AKD5MGGTW03 (128M*16)
K4W1G1646E-HC12
AKD5LGGT506 (64M*16)
K4W2G1646B-HC12
AKD5MGGT500 (128m*16)
23EY2387MA12-SZ
AKD5LGGT700
Thermal Sensor(VGA)
Vendor
Samsung
P/N
WINDBOND
AL83L771K01
GMT
AL000780000
USD0.16
AMD
+3V_D_S
+3V_D_S
R365
EV@10K_4
R364
*EV@10K_4
C512
ADDRESS: 98H
U13
SCLK
VCC
<35> MXM_SMDATA12
SDA
DXP
C513
<17> ALT#_GPIO17
ALERT#
DXN
EV@2200p/50V_4
<35> VGA_THERM#
OVERT#
+1.8V_GPU
Samsung - 1Gb
<35> MXM_SMCLK12
GND
GPU_D+
<17> RAM_STRAP2
GPU_D-
<17>
R345
*EV@10K_4
R354
EV@10K_4
R344
*EV@10K_4
R353
EV@10K_4
R346
*EV@10K_4
R355
EV@10K_4
<17>
<17> RAM_STRAP1
EV@G780P81U
RAM_STRAP2 SET DDR3 Vendor

RAM_STRAP[1:0] SET SIZE.
ADDRESS: 98H
<17> RAM_STRAP0
PROJECT :ZQ9
Size
Document Number
Rev
1A
Strip/Thermal
Date:
Sheet

1
21
of
45
Park, M92M Use Channel B Memory Interface Only
VMB_DM[7..0]
<18> VMB_DM[7..0]
<18> VMB_RDQS[7..0]
<18> VMB_WDQS[7..0]
VMB_RDQS[7..0]
QSA[7..0]
VMB_WDQS[7..0]
QSA#[7..0]
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13
<18>
<18>
<18>
VMB_BA0
VMB_BA1
VMB_BA2
<18> VMB_CLKP0
<18> VMB_CLKN0
<18> VMB_CKE0
<18>
<18>
<18>
<18>
<18>
CHANNEL B: 512MB DDR3 (16*64M*4pcs)
VMB_DQ[63..0]
<18> VMB_DQ[63..0]
VMB_ODT0
VMB_CS0#
VMB_RAS0#
VMB_CAS0#
VMB_WE0#
U4
VREFC_VMB1
VREFD_VMB1
M8
H1
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VMB_BA0
VMB_BA1
VMB_BA2
M2
N8
M3
VMB_CLKP0
VMB_CLKN0
VMB_CKE0
J7
K7
K9
VMB_ODT0
VMB_CS0#
VMB_RAS0#
VMB_CAS0#
VMB_WE0#
K1
L2
J3
K3
L3
VMB_RDQS3
VMB_RDQS0
F3
C7
VMB_DM3
VMB_DM0
E7
D3
VMB_WDQS3
VMB_WDQS0
G3
B7
MEM_RST#
T2
<18> MEM_RST#
VMB_ZQ1
L8
U16
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ
NC#J1
NC#L1
NC#J9
NC#L9
E3
F7
F2
F8
H3
H8
G2
H7
VMB_DQ24
VMB_DQ26
VMB_DQ31
VMB_DQ27
VMB_DQ30
VMB_DQ28
VMB_DQ29
VMB_DQ25
D7
C3
C8
C2
A7
A2
B8
A3
VMB_DQ3
VMB_DQ6
VMB_DQ0
VMB_DQ4
VMB_DQ2
VMB_DQ5
VMB_DQ1
VMB_DQ7
3
0
VREFC_VMB2
VREFD_VMB2
M8
H1
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VMB_BA0
VMB_BA1
VMB_BA2
M2
N8
M3
VMB_CLKP0
VMB_CLKN0
VMB_CKE0
J7
K7
K9
+1.5V_GPU
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
R85
EV@240/F_4
J1
L1
J9
L9
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
VMB_ODT0
VMB_CS0#
VMB_RAS0#
VMB_CAS0#
VMB_WE0#
K1
L2
J3
K3
L3
VMB_RDQS2
VMB_RDQS1
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VMB_DM2
VMB_DM1
E7
D3
VMB_WDQS2
VMB_WDQS1
G3
B7
MEM_RST#
T2
VMB_ZQ2
B1
B9
D1
D8
E2
E8
F9
G1
G9
L8
100-BALL
SDRAM DDR3
EV@VRAM _DDR3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
DML
DMU
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
DQSL
DQSU
RESET
ZQ
NC#J1
NC#L1
NC#J9
NC#L9
E3
F7
F2
F8
H3
H8
G2
H7
VMB_DQ20
VMB_DQ18
VMB_DQ16
VMB_DQ21
VMB_DQ19
VMB_DQ22
VMB_DQ17
VMB_DQ23
D7
C3
C8
C2
A7
A2
B8
A3
VMB_DQ15
VMB_DQ10
VMB_DQ14
VMB_DQ9
VMB_DQ12
VMB_DQ8
VMB_DQ13
VMB_DQ11
2
1
VREFC_VMB3
VREFD_VMB3
M8
H1
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VMB_BA0
VMB_BA1
VMB_BA2
M2
N8
M3
VMB_CLKP1
VMB_CLKN1
VMB_CKE1
J7
K7
K9
+1.5V_GPU
BA0
BA1
BA2
R374
EV@240/F_4
J1
L1
J9
L9
U14
VREFCA
VREFDQ
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
B2
D9
G7
K2
K8
N1
N9
R1
R9
<18> VMB_CLKP1
<18> VMB_CLKN1
<18> VMB_CKE1
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
<18>
<18>
<18>
<18>
<18>
VMB_ODT1
VMB_CS1#
VMB_RAS1#
VMB_CAS1#
VMB_WE1#
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VMB_ODT1
VMB_CS1#
VMB_RAS1#
VMB_CAS1#
VMB_WE1#
K1
L2
J3
K3
L3
VMB_RDQS4
VMB_RDQS7
F3
C7
VMB_DM4
VMB_DM7
E7
D3
VMB_WDQS4
VMB_WDQS7
G3
B7
MEM_RST#
T2
VMB_ZQ3
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ
R348
EV@240/F_4
100-BALL
SDRAM DDR3
EV@VRAM _DDR3
BOT Down
L8
U2
VREFCA
VREFDQ
NC#J1
NC#L1
NC#J9
NC#L9
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
VMB_DQ32
VMB_DQ37
VMB_DQ35
VMB_DQ36
VMB_DQ33
VMB_DQ38
VMB_DQ34
VMB_DQ39
VREFC_VMB4
VREFD_VMB4
M8
H1
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
D7
C3
C8
C2
A7
A2
B8
A3
VMB_DQ63
VMB_DQ59
VMB_DQ60
VMB_DQ56
VMB_DQ62
VMB_DQ57
VMB_DQ61
VMB_DQ58
VMB_BA0
VMB_BA1
VMB_BA2
M2
N8
M3
VMB_CLKP1
VMB_CLKN1
VMB_CKE1
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
VMB_ODT1
VMB_CS1#
VMB_RAS1#
VMB_CAS1#
VMB_WE1#
K1
L2
J3
K3
L3
VMB_RDQS5
VMB_RDQS6
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VMB_DM5
VMB_DM6
E7
D3
VMB_WDQS5
VMB_WDQS6
G3
B7
MEM_RST#
T2
4
7
+1.5V_GPU
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5V_GPU
VMB_ZQ4
B1
B9
D1
D8
E2
E8
F9
G1
G9
L8
J1
L1
J9
L9
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
VMB_DQ50
VMB_DQ55
VMB_DQ48
VMB_DQ52
VMB_DQ51
VMB_DQ54
VMB_DQ49
VMB_DQ53
5
D
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
CK
CK
CKE
DQSL
DQSU
VMB_DQ46
VMB_DQ42
VMB_DQ47
VMB_DQ41
VMB_DQ45
VMB_DQ40
VMB_DQ44
VMB_DQ43
+1.5V_GPU
BA0
BA1
BA2
ODT
CS
RAS
CAS
WE
E3
F7
F2
F8
H3
H8
G2
H7
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
DML
DMU
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
DQSL
DQSU
RESET
ZQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
NC#J1
NC#L1
NC#J9
NC#L9
100-BALL
SDRAM DDR3
EV@VRAM _DDR3
TOP Up
Group-B0 VREF
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
R64
EV@240/F_4
100-BALL
SDRAM DDR3
EV@VRAM _DDR3
TOP Down
VREFCA
VREFDQ
BOT Up
Group-B1 VREF
+1.5V_GPU
+1.5V_GPU
R379
R76
VREFC_VMB1
R384
+1.5V_GPU
C542
R372
VREFD_VMB1
R75
+1.5V_GPU
C140
+1.5V_GPU
R383
R17
+1.5V_GPU
R369
+1.5V_GPU
R43
R19
VREFC_VMB2
VREFD_VMB2
VREFC_VMB3
VREFD_VMB3
VREFC_VMB4
VREFD_VMB4
R373
C535
R382
C540
R16
C21
R370
C521
R44
C61
R18
C22
Group-B0 decoupling CAP
MEM_B0 CLK
+1.5V_GPU
Group-B1 decoupling CAP
+1.5V_GPU
MEM_B1 CLK
+1.5V_GPU
VMB_CLKP1
VMB_CLKP0
VMB_CLKN1
C532
C525
C536
C533
C531
C215
C20
C530
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
VMB_CLKN0
R381
R380
C16
C216
C214
C23
C516
C143
C39
C499
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
+1.5V_GPU
R350
R349
+1.5V_GPU
C493
C545
C534
C17
C217
C146
C524
C142
C218
C19
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
C541
C27
C500
C33
C517
C529
C42
C537
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
EV@1u/6.3V_4
+1.5V_GPU
+1.5V_GPU
C527
C173
C543
C544
C528
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
C498
C149
C52
C496
C497
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
EV@10u/6.3V_6
PROJECT : ZQ9
Size
Document Number
Date:
Rev
1A
MEMORY 2 channel B
5
Sheet
1
22
of
45
CRT Switch
CRT
C272
0_ohm Resistor place close to Joint-Point
<8> INT_CRT_RED
<8> INT_CRT_GRN
<8> INT_CRT_BLU
<8> INT_VSYNC
<8> INT_HSYNC
A
R95
R94
R93
INT_VSYNC
INT_HSYNC
RN7
1
3
IV@0_4P2R
2
4
VSYNC
HSYNC
INT_CRT_DDCDAT
INT_CRT_DDCCLK
RN8
1
3
IV@0_4P2R
2
4
CRTDDATA
CRTDCLK
IV@0_4
IV@0_4
IV@0_4
VGA_RED
VGA_GRN
VGA_BLU
D16
SSM22LLPT
CRTVDD5
SMD1206P110TFT
VGA_RED
L27
BLM18BA750SN1D/0.3A/75ohm_6
CRT_R1
VGA_GRN
L26
CRT_G1
L25
VGA_BLU
CN8
CRT-CONN
6
1
7
2
8
3
9
4
10
5
CRT_B1
R189
R177
R165
C322
C308
C293
C637
C647
C653
150/F_4
150/F_4
150/F_4
10p/50V_4
10p/50V_4
10p/50V_4
10p/50V_4
10p/50V_4
10p/50V_4
11
CRT_11
12
DDCDAT_1
13
CRTHSYNC
14
CRTVSYNC
15
DDCCLK_1
T22
17
<8> INT_CRT_DDCDAT
<8> INT_CRT_DDCCLK
INT_CRT_RED
INT_CRT_GRN
INT_CRT_BLU
0.1u/10V_4_X7R
F2
2
+5V
16
IV@
EV@
EV_CRT_BLU
EV_CRT_GRN
EV_CRT_RED
<17> EV_CRT_BLU
<17> EV_CRT_GRN
<17> EV_CRT_RED
<17,21> EV_HSYNC
<17,21> EV_VSYNC
<17> EV_CRTDCLK
<17> EV_CRTDDAT
R391
R397
R399
EV@0_4 VGA_BLU
EV@0_4 VGA_GRN
EV@0_4 VGA_RED
EV_HSYNC
EV_VSYNC
RN15 EV@0_4P2R
1
2
3
4
EV_CRTDCLK
EV_CRTDDAT
RN16 EV@0_4P2R
1
2
3
4
HSYNC
VSYNC
6/21 change to 0 ohm
+3V
CRTDCLK
CRTDDATA
C301
U23
CRTVDD5
CRT_BYP
7
8
0.1u/10V_4_X7R
C632
.22u/25V_6
+3V
VCC_SYNC SYNC_OUT2
SYNC_OUT1
VCC_DDC
BYP
SYNC_IN2
VCC_VIDEO
SYNC_IN1
16
14
CRT_VSYNC2
CRT_HSYNC2
R458
R457
CRTVSYNC
CRTHSYNC
0_4
0_4
VSYNC
HSYNC
15
13
CRTVDD5
+3V
C315
CRT_R1
CRT_G1
CRT_B1
0.1u/10V_4_X7R
3
4
5
6
VIDEO_1
VIDEO_2
VIDEO_3
DDC_IN1
DDC_IN2
DDC_OUT1
DDC_OUT2
GND
10
11
CRTDCLK
CRTDDATA
9
12
DDCCLK_1
DDCDAT_1
R462
R469
2.7K_4
2.7K_4
R452
R476
2.7K_4
2.7K_4
C661
*.1u/10V_4
CRTVDD5
C620
*10p/50V_4
CRTVSYNC
C619
*10p/50V_4
CRTHSYNC
C631
10p/50V_4
DDCCLK_1
C646
10p/50V_4
DDCDAT_1
CM2009-02QR
LVDS
LVDS
LCD Power
+3V
VIN
+3V
C8
C7
C2
0.1u/10V_4_X7R
1000p/50V_4
C3
C1
4.7u/25V_8
U1
1000p/50V_4
1U/6.3V_4
5/7 add
4
C14
C11
*1u/6.3V_4
LVDS_VDDEN
R8
R14
*SHORT0805
*SHORT0805
R9
R10
+3V
INVCC0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
<8> INT_LVDS_BRIGHT
EV@0_4
*0_4
R13
IV@0_4
IV@0_4P2R TXLCLKOUT+
TXLCLKOUTIV@0_4P2R TXLOUT0+
TXLOUT0IV@0_4P2R TXLOUT1+
TXLOUT1IV@0_4P2R TXLOUT2+
TXLOUT2-
R5
*1u/6.3V_4
*.1u/10V_4
*2.2u/10V_8
0.1u/10V_4_X7R.01u/25V_4
C4
5
22u/6.3V_8
USBP8-_R
USBP8+_R
CCD-USB
CCD_PWR
0_6
LVDS_BRIGHT
BL_ON
R6
BLM15AG121SS1/0.5A/120ohm_4
R4
100K_4
Backlight Control
+3VPCU
34
31
R375
*100K_4
34
LID591#
31
<35>
LID591#,EC intrnal PU
LVDS
+3V
CCD +3V-current budget 0.2A
2
4
2
4
2
4
2
4
*1u/6.3V_4
C10
D14
BAS316
5/21 Change the LVDS connector and swap

R2
*0_4
R376
L1
2
3
<10> USBP8+
<10> USBP8-
R377
2
3
1
4
1
4
USBP8+_R
USBP8-_R
10K_4
BL_ON
10K_4
RFCMF1632100M3T/200mA/90ohm
R3
*0_4
LVDS_BRIGHT
BL#
+3VPCU
LVDS_BLON
100K_4
EC_FPBACK#
<35>
Q9
DTC144EUA
Q11
2N7002K
0.1u/10V_4_X7R
2
Q10
2N7002K
2
R378
C491
RN10 1
3
RN13 1
3
RN12 1
3
RN11 1
3
RN4
TXLCLKOUTTXLCLKOUT+
C13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
R7
R12
2
4
2
4
2
4
2
4
RN3
INT_TXLCLKOUT+
INT_TXLCLKOUTINT_TXLOUT0+
INT_TXLOUT0INT_TXLOUT1+
INT_TXLOUT1INT_TXLOUT2+
INT_TXLOUT2-
<8> INT_TXLCLKOUT+
<8> INT_TXLCLKOUT<8> INT_TXLOUT0+
<8> INT_TXLOUT0<8> INT_TXLOUT1+
<8> INT_TXLOUT1<8> INT_TXLOUT2+
<8> INT_TXLOUT2-
1
3
1
3
1
3
1
3
RN2
TXLOUT2TXLOUT2+
5/7 add
+3V
C9
<17> EV_TXLCLKOUT<17> EV_TXLCLKOUT+

<17> EV_TXLOUT0<17> EV_TXLOUT0+
EV@0_4P2R TXLCLKOUTTXLCLKOUT+
EV@0_4P2R TXLOUT0TXLOUT0+
RN5
TXLOUT1TXLOUT1+
C12
C5
EV_TXLCLKOUTEV_TXLCLKOUT+
EV_TXLOUT0EV_TXLOUT0+
LCD_EDIDCLK
LCD_EDIDDATA
TXLOUT0TXLOUT0+
IV@0_4P2R
LCD_EDIDCLK
2
LCD_EDIDDATA
4
IV@0_4P2R
LVDS_VDDEN
2
LVDS_BLON
4
C6
INT_LVDS_DIGON
INT_LVDS_BLON
<8> INT_LVDS_DIGON
<8> INT_LVDS_BLON
<35> CONTRAST
<17> EV_LVDS_BRIGHT
RN9
1
3
RN6
1
3
INT_LVDS_EDIDCLK
INT_LVDS_EDIDDATA
<8> INT_LVDS_EDIDCLK
<8> INT_LVDS_EDIDDATA
GND
ON/OFF
LCDVCC
EV_LVDS_VDDEN
EV_LVDS_BLON
<17> EV_LVDS_VDDEN
<17> EV_LVDS_BLON
2.2K_4
2.2K_4
RN1 EV@0_4P2R
LCD_EDIDCLK
1
2
LCD_EDIDDATA
3
4
RN14 EV@0_4P2R
LVDS_VDDEN
1
2
LVDS_BLON
3
4
EV_LVDS_DDCCLK
EV_LVDS_DDCDAT
<17> EV_LVDS_DDCCLK
<17> EV_LVDS_DDCDAT
GND
CN5
0_6
0_ohm Resistor place close to Joint-Point
OUT
IN
AAT4280-4
0.8A
R11
LCDVCC
VIN
*1u/6.3V_4
IN
LID591#
HE1
PT3661-BB
D13
*VPORT_6
PROJECT : ZQ9
PT3661-BB : AL003661003
EM-6781-T3 : AL006781000
Size
Document Number
Date:
Rev
1A
CRT/LVDS/CAMERA/LID
Lid Switch (Hall sensor)

5
23
Sheet
8
of
45
SW@HDMI-detect
+3V
I@ HDMI LEVEL SHIFTER

R282
<9> HDMI_HPD_PCH#
+3V
To MXM
*0_4
R278
10K_4
+3V
EV@
C667
C349
C350
C666
[email protected]/6.3V_6
R219
+3V
*4.7K_4
DDCBUF_EN
CFG
+3V
HDMI_HPD_EC#
<35> HDMI_HPD_EC#
HDMI_HP_EV
+5V
+3V
R283
*10K_4
Active Buffer
<8> INT_HDMITX0N
<8> INT_HDMITX0P
+3V
<8> INT_HDMITX2N
<8> INT_HDMITX2P
<8> INT_HDMITX1P
<8> INT_HDMITX1N
+3V
GND
OUT_D1OUT_D1+
VCC
OUT_D2OUT_D2+
GND
OUT_D3OUT_D3+
VCC
OUT_D4OUT_D4+
1
2
3
4
5
6
7
8
9
10
11
12
<8> INT_HDMICLK+
<8> INT_HDMICLK-
GND
IN_D1IN_D1+
VCC
IN_D2IN_D2+
GND
IN_D3IN_D3+
VCC
IN_D4IN_D4+
GND
R547
R548
4.7K_4
*4.7K_4
PC0
R549
*4.7K_4
PC1
R510
R217
*4.7K_4
*4.7K_4
DDCBUF_EN
R509
R218
*4.7K_4
*4.7K_4
CFG
+3V
PC0
PC1
from PCH
R188
LS_REXT
+3V
24
23
22
21
20
19
18
17
16
15
14
13
MB_HDMITX0N
MB_HDMITX0P
+3V
MB_HDMITX2N
MB_HDMITX2P
I2C
MB_HDMITX1P
MB_HDMITX1N
+3V
5/14 change design
MB_HDMICLK+
MB_HDMICLK-
D19 2
+5V
5/24 change to +3V
IV@PS8101
+3V
R528
1.5K_4
<17> MXM_DDCCK
L
H
L
H
*EV@0_4
IV@499/F_4
6/18 stuff & unstuff
D18 2
+5V
PC0
internal PD
PC1
internal PD
DDCBUF_EN
internal PD
CFG
internal PD
DDC_EN
internal PU
R191
IV@0_4 HDMI_DDCDATA_SW
R190
IV@0_4
R486
R485
+3V
R237
[email protected]_4
Q13
HDMI_DDCCLK_SW
R527
1.5K_4
EV@BSN20
<17> MXM_DDCDAT
+3V
1RB501V-40
+3V
<8> SDVO_CTRLCLK
8dB
4dB
12dB
0dB
HDMI_DDCCLK_MB
3
R215
Control by pin4 HPDEN_R
<8> SDVO_CTRLDAT
L
L
H
H
EV@BSN20
+3V
5/24 change to +3V
PC1 PC0
PIN4 PIN3 EQ Control
1RB501V-40
+3V
R236
[email protected]_4
Q14
<8> INT_HDMI_HPD
Equalization Control
Q20
2N7002D
6/11 change the P/N
36
35
34
33
32
31
30
29
28
27
26
25
37
38
39
40
41
42
43
44
45
46
47
48
49
from PCH
GND
CCT2
CCT1
VCC
DDC_EN
GND
HPD_SINK
SDA_SINK
SCL_SINK
GND
VCC
OE#
5/19 stuff
HDMI_MB_HP
GND
VCC
TRIM
HPDEN
GND
REXT
HPD_S
SDA_S
SCL_S
NC
VCC
GND
U6
+3V
C321
6/11 change the P/N

Q21
EV@2N7002D
close to pin2/11/15/21/26/33/40/46
C341
<17>
C346
R277
EV@10K_4
IV@
HDMI_MB_HP
HDMI_DDCDATA_MB
HDMI_DDCCLK_MB
HDMI_HPD_EC#
[email protected]_4
[email protected]_4
HDMI_DDCDATA_MB
3
R216
*EV@0_4
6/18 stuff & unstuff
AC-coupling CAP place close to HDMI-connector
Switchable Graphic HDMI source
EMI
From GPU
HDMI connector
MB_HDMITX2P
<17> HDMITX0N
<17> HDMITX0P
<17> HDMITX2N
<17> HDMITX2P
C347
C348
MB_HDMITX0N
MB_HDMITX0P
C343
C340
MB_HDMITX2N
MB_HDMITX2P
C339
C337
MB_HDMITX1P
MB_HDMITX1N
C333
C323
MB_HDMICLK+
MB_HDMICLK-
R502
CN11
*100/F_4
MB_HDMITX2P
MB_HDMITX2N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
MB_HDMITX2N
MB_HDMITX1P
MB_HDMITX1P
<17> HDMITX1P
<17> HDMITX1N
<17> HDMICLK+
<17> HDMICLK-
R496
MB_HDMITX1N
MB_HDMITX0P
*100/F_4
MB_HDMITX1N
MB_HDMITX0N
MB_HDMICLK+
MB_HDMITX0P
R488
R492
R494
R497
R501
R503
R505
R506
EV@499/F_4
EV@499/F_4
EV@499/F_4
EV@499/F_4
EV@499/F_4
EV@499/F_4
EV@499/F_4
EV@499/F_4
R507
+5V
*100/F_4
F1
SMD1206P110TFT
2
1
MB_HDMITX0N
MB_HDMICLK+
5/7 change
R490
MB_HDMICLK-
*100/F_4
D20
HDMI_DDCCLK_MB
HDMI_DDCDATA_MB
SSM22LLPT
HDMI_MB_HP
R271
*Short_4
Q12
R467
*EV@1M_4
MB_HDMICLK-
R546
20
23
22
21
HDMI
100K_4
EV@2N7002D
+5V
SHELL1
D2+
D2 Shield
D2D1+
D1 Shield
D1D0+
D0 Shield
D0GND
CK+
CK Shield GND
CKCE Remote
NC
DDC CLK
DDC DATA
GND
+5V
HP DET
SHELL2
6/11 change the P/N

PROJECT : ZQ9
Size
Document Number
Date:
Rev
1A
HDMI (PS8101)
5
Sheet
1
24
of
45
Giga-LAN BCM57780
+3V_S5
U8
15mil
42
+3V_S5
6
15
41
VAUX_12
D
L53
15mil
VAUX_12
C673
C677
BLM18AG601SN1_6
AVDDL
4.7U/6.3V_6
0.1u/10V_4_X7R
27
33
39
VDDO
BIASVDDH
VDDC
VDDC
VDDC
XTALVDDH
AVDDL
AVDDL
AVDDL
AVDDH
BCM57780
7mm X 7mm
AVDDH
25
BIASVDD
C382
L30
BLM18AG601SN1_6
0.1u/10V_4_X7R
14
XTALVDD
C685
L56
BLM18AG601SN1_6
0.1u/10V_4_X7R
30
AVDDH
L52
C674
36
48-Pin QFN
L54
15mil
C390
C388
BLM18AG601SN1_6
L55
GPHY_PLLVDD
4.7U/6.3V_6
0.1u/10V_4_X7R
15mil
BLM18AG601SN1_6
C679
C681
PCIE_PLLVDD
4.7U/6.3V_6
0.1u/10V_4_X7R
24
18
21
GPHY_PLLVDDL
C675
TRD3_N
TRD3_P
TRD2_N
TRD2_P
PCIE_PLLVDDL
TRD1_N
TRD1_P
PCIE_PLLVDDL
TRD0_N
TRD0_P
<10> PCIE_RX1+
<10> PCIE_RX1<10> PCIE_TX1+
<10> PCIE_TX1<8,27> PCIE_WAKE#
<4,10,11,27,31,35> PLTRST#
<10> CLK_PCIE_LOM
<10> CLK_PCIE_LOM#
C404
C410
0.1u/10V_4_X7R PCIE_RXP1_LAN_R 17
0.1u/10V_4_X7R PCIE_RXN1_LAN_R 16
22
23
4
2
20
19
LINKLED#
SPD100LED#
SPD1000LED#
TRAFFICLED#
PCIE_TXDP
PCIE_TXDN
PCIE_RXDP
PCIE_RXDN
WAKE#
PERST#
PCIE_REFCLK_P
PCIE_REFCLK_N
MODE
+3V
VMA_PRES
LOW_PWR
1K/F_4
4.7K_4
40
1
EEDATA
R286
200_4
XTALO
XTALI
13
12
R267
1.24K/F_4
RDAC
26
33p_4
1.2H
Y2
25MHz
<26>
<26>
35
34
LAN_TRD2N
LAN_TRD2P
<26>
<26>
31
32
LAN_TRD1N
LAN_TRD1P
<26>
<26>
29
28
LAN_TRD0N
LAN_TRD0P
<26>
<26>
LAN_LINKLED#
LAN_ACTLED#
LAN_ACTLED#
<26>
<26>
44
BCM_EEC
43
BCM_EED
XTALO
XTALI
VAUX_12
SR_VDDP
SR_VDD
L32
11
8
10
9
4.7uh
Don't route under Choke.
+3V_S5
C687
RDAC
4.7U/6.3V_6
2
C419
LAN_LINKLED#
VMAIN_PRSNT
LOW_PWR
SR_LX
SR_VFB
C420
0.1u/10V_4_X7R
LAN_TRD3N
LAN_TRD3P
EECLK
R272
R290
0.1u/10V_4_X7R
37
38
48
47
46
45
BLM18AG601SN1_6
C686
C418
0.1u/10V_4_X7R
C422
10u/6.3V_6
0.1u/10V_4_X7R
33p_4
+3V_S5
R291
*4.7K_4
CLK_REQ#
NC
*Short_4BCM_CLKREQ#
GND
R292
49
<10> CLK_PCIE_LAN_REQ#
BCM57780
+3V_S5
+3V_S5
VAUX_12
C683
C401
6/18 change to use internal ROM
EEPROM
LAN POWER
4.7U/6.3V_6
0.1u/10V_4_X7R
20mil
C680
R287
*1K_4
4.7U/6.3V_6
C682
0.1u/10V_4_X7R
C678
0.1u/10V_4_X7R
C399
0.1u/10V_4_X7R
R289
1K_4
BCM_EED
BCM_EEC
U27
5
6
7
R284
R294
1K_4
*1K_4
SDA
SCL
A0
A1
A2
1
2
3
WP
GND
*24LC02
VCC
+3V_S5
C423
*0.1u/10V_4_X7R
EEPROM Strapping
EEPROM Type
A version Still mount the EEPROM
EECLK EEDATA
24LC02
Internal

PROJECT : ZQ9
Size
Document Number
Rev
1A
GLAN BCM57780
Date:
5
Sheet
1
25
of
45
TRANSFORMER
U26
A
C362
TCT1
TD1+
TD1-
MCT1
MX1+
MX1-
24
23
22
X-TX0P
X-TX0N
C361
<25> LAN_TRD0P
<25> LAN_TRD0N
1
2
3
0.1u/10V_4_X7R
0.1u/10V_4_X7R
<25> LAN_TRD1P
<25> LAN_TRD1N
4
5
6
TCT2
TD2+
TD2-
MCT2
MX2+
MX2-
21
20
19
X-TX1P
X-TX1N
C368
7
8
9
TCT3
TD3+
TD3-
MCT3
MX3+
MX3-
18
17
16
X-TX2P
X-TX2N
C364
<25> LAN_TRD2P
<25> LAN_TRD2N
0.1u/10V_4_X7R
0.1u/10V_4_X7R
<25> LAN_TRD3P
<25> LAN_TRD3N
10
11
12
TCT4
TD4+
TD4-
MCT4
MX4+
MX4-
15
14
13
X-TX3P
X-TX3N
R250
CN9
LAN_ACTLED#
<25> LAN_ACTLED#
+3V_S5
220_8
LAN_ACT_LED_PWR
9
10
X-TX0P
X-TX0N
X-TX1P
X-TX2P
X-TX2N
X-TX1N
X-TX3P
X-TX3N
1
2
3
4
5
6
7
8
LAN_LINKLED#
LAN_LNK_LED_PWR
11
12
TRANSFORMER
R255
75/F_8
R256
75/F_8
R257
75/F_8
R258
75/F_8
<25> LAN_LINKLED#
+3V_S5
Delta LFE9276D-R (DB0ZY8LAN00)
R263
220_8
YELLOW_N
YELLOW_P
GND2
GND1
0+
01+
2+
213+
3-
14
13
R265
R235
*0_6
*0_6
GREEN_N
GREEN_P
RJ45
C672
1500p/3KV_18
LAN_ACTLED#
LAN_LINKLED#
C354
C384
*0.1u//50V_8
*0.1u//50V_8

PROJECT : ZQ9
Size
Document Number
Rev
1A
LAN Transformer and RJ45

Date:
1

7
Sheet
26
of
8
45
Debug
<10>
<10>
<10>
*Short_4 CL_DATA1_WLAN
*Short_4 CL_CLK1_WLAN
R561
R555
R307
*0_4
*0_4
*0_4
CL_RST1#_WLAN
CL_DATA1_WLAN
CL_CLK1_WLAN
+WL_VDD
A
<10>
<10>
PCIE_TX6+
PCIE_TX6-
<10>
<10>
PCIE_RX6+
PCIE_RX6-
<10> CLK_PCH_SRC2
<10> CLK_PCH_SRC2#
<10> PCIE_CLK_REQ2#
PCIE_WAKE#_R
+WL_VDD
R303
*SHORT0805 +WL_VDD
LTS_AAA-PCI-046-K01
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
UIM_C4
UIM_C8
15
13
11
9
7
5
3
1
GND
REFCLK+
REFCLKGND
CLKREQ#
Reserved
Reserved
WAKE#
+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
W_DISABLE#
GND
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
+WL_VDD
UIM_VPP
UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR
+1.5V
GND
+3.3V
16
14
12
10
8
6
4
2
A_LFRAME#_R
A_LAD3_R
A_LAD2_R
A_LAD1_R
A_LAD0_R
C457
10u/6.3V_8
+1.5V
RF_LED#
C458
0.1u/10V_4
C697
*0.1u/10V_4
C432
*0.1u/10V_4
RF_LED# <32>
USB_Wifi+
USB_Wifi-
5/13 change to 6.3V

CLK_SDATA <3,14,15>
CLK_SCLK <3,14,15>
+1.5V
+1.5V
+WL_VDD
+1.5V
PLTRST#
R293
R288
R285
R281
R280
PLTRST# <4,10,11,25,31,35>
RF_EN <35>
0_4
0_4
0_4
0_4
0_4
Debug
LPC_LFRAME# <9,35>
LPC_LAD3 <9,35>
LPC_LAD2 <9,35>
LPC_LAD1 <9,35>
LPC_LAD0 <9,35>
C695
1000p/50V_4
C684
0.1u/10V_4
C688
10u/6.3V_8
6/9 stuff all for debug
+WL_VDD
53
+WL_VDD
+3V
H=7.0mm
CN13
CL_RST1#
CL_DATA1
CL_CLK1
Check LED signal. (active high or low)

R556
R306
<10>
PCI_RST#
<10> CLK_LPC_DEBUG
GND
+3.3V: 1000mA
+3.3Vaux:330mA
+1.5V:500mA
GND
MINI-CARD WLAN(MPC)
54
<8,25> PCIE_WAKE#
Q6
*DTC144EUA
PCIE_WAKE#_R
1
modify 10/19
USB_Wifi+
USB_Wifi-
R575
R576
*0_4
*0_4
USBP13+
USBP13-
<10,33>
<10,33>

PROJECT : ZQ9
Size
Document Number
Date:
Rev
1A
MINI PCI-E card/TV

1
Sheet
27
8
of
45
EE RETURN-PATH CAPACITORS
MAIN SATA HDD
VIN
5/13 update the P/N and F/P
CN12
GND23
23
GND1
RXP
RXN
GND2
TXN
TXP
GND3
1
2
3
4
5
6
7
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
RSVD
GND
12V
12V
12V
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GND24
24
C426
+VGPU_CORE
0.1u/25V_4_X5R
6/18 stuff for EMI
SATA_TXP0_C
SATA_TXN0_C
C461
C459
.01u/25V_4
.01u/25V_4
SATA_RXN0
SATA_RXP0
C456
C453
.01u/25V_4
.01u/25V_4
SATA_TXP0 <9>
SATA_TXN0 <9>
SATA_RXN0_C <9>
SATA_RXP0_C <9>
C224
*0.1u/25V_4_X5R
C669
*0.1u/25V_4_X5R
C15
0.1u/25V_4_X5R
C514
*.1u/10V_4
+5V
C711
*.1u/10V_4
C670
*.1u/10V_4
C718
.1u/10V_4
C719
.1u/10V_4
C720
.1u/10V_4
6/18 stuff for EMI

6/18 add for EMI
+3V
+1.05V
+5V_S5
+5V_HDD
C506
.1u/10V_4
6/18 stuff for EMI
C359
R550
+5V
MAIN_SATA
C553
*.1u/10V_4
C704
*.1u/10V_4
C479
.1u/10V_4
*.1u/10V_4
6/18 stuff for EMI
*SHORT0805
+5V_HDD
C676
C386
C400
C398
C395
C392
*100u/6.3V_3528
10u/10V_6
*.1u/16V_4
*.1u/16V_4
.01u/25V_4
.01u/25V_4
C462
*.1u/10V_4
C489
*.1u/10V_4
5/25 reserve for EMI
6/21 add
5/27 cost down
ODD (SATA)
CN7
C
GND14
14
C
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
DP
5V
5V
MD
GND
GND
8
9
10
11
12
13
GND15
15
SATA_TXP1_C
SATA_TXN1_C
C317
C310
.01u/25V_4
.01u/25V_4
SATA_RXN1
SATA_RXP1
C304
C296
.01u/25V_4
.01u/25V_4
SATA_TXP1 <9>
SATA_TXN1 <9>
SATA_RXN1_C <9>
SATA_RXP1_C <9>
+5V
SATA_DP
R159
*1K_4
R443
C263
C262
C254
C264
C252
.01u/25V_4
.01u/25V_4
*.1u/16V_4
*.1u/16V_4
10u/10V_6
+5V_ODD
*SHORT0805
C611
*100u/6.3V_3528
5/27 cost down
SATA_ODD_H=7.7
D
5/26 change the footprint
PROJECT : ZQ9
Size
Document Number
SATA-HDD/ODD/USB-ESATA
Date:
1
Sheet
4
28
of
45
Rev
1A
Codec(ADO)
HP
<30>
HP-R
<30>
HP-L
MUTE(AMP)
SENSEB
R313 5.1K/F_4
<30> HPOUT_JD
MIC1-VREFO <30>
ADOGND
Place next to pin 27
FRONT-L= (L+R)/2
6/21 change the P/N
5/11 update
5/11 Del FRONT-R

C478
C477
FRONT-L
C473
ADOGND
Speaker
C476
+5VA
0.1u/10V_4 10u/6.3V_6
C474
2.2u/6.3V_6 2.2u/6.3V_6
C471
0.47u/10V_6
Bypass
VO2
FRONT-L
C480
*0.47u/10V_6 FRONT-R-1
R315
22K/F_6
FRONT-R-2
IN-
GND
C483
0.47u/10V_6
R319
22K/F_6
FRONT-R+2
IN+
VDD
SHUTDOWN
VO1
ADOGND
26
MIC1-R
21
MIC1-L
DMIC-CLK3/4
MIC2-R
SPDIFO2
MIC2-L
DMIC-CLK1/2
<30>
MIC1-L
<30>
R320
+3V
MIC
C470
C490
0.1u/10V_4 0.1u/10V_4 4.7U/6.3V_6
*100K_4
R314
0_4
+3V_S5
20
MIC2-VREFO
19
18
<35> AMP_MUTE#
17
MIC2_INT_R
C463
1u/10V_6
16
MIC2_INT_L
C460
1u/10V_6
MIC2_INTL1_R R308
1K_4
MIC2_INTL1
U29
4
EAPD#
*TC7SH08FU
R316
*0_4
R323
*10K_4
HP_MUTE# <30>
C485
*4.7u/10V_6
15
14
SENSEA
13
PCBEEP
RESET#
SYNC
<30>
R305
20K/F_4 MIC1_JD
MIC1_JD
<30>
ANALOG
12
11
10
DVDD-IO
SDATA-IN
DVSS2
Sense A
LINE2-L
DVDD1
SPDIFO1
Split by DGND
LINE2-R
BIT-CLK
EAPD
MIC1-R
MIC2-VREFO
LINE1-VREFO
48
NC
SDATA-OUT
47
LINE2-VREFO
ALC272X<LQFP-48>
AVSS2
46
SURR-R
C469
INSPKR-
6/18 change AMP & modify the circuit
ADOGND
27
28
25
AVDD1
AVSS1
VREF
30
31
32
33
29
MIC1-VREFO
CBP
CBN
CPVEE
HPOUT-R
22
MIC1-L
45
EAPD#
34
MIC1-R
JDREF
44
Split by DGND
HPOUT-L
SURR-L
40
DIGITAL
35
39
DVSS1
T27
Sense B
36
T28
DMIC-3/4/GPIO1
ANALOG
FRONT-R
T29
23
43
<30>
ADOGND
24
LINE1-L
42
FRONT-R+1
Change to 0.47U to reduce popping noise
INSPKR+
ADOGND
G1442P81U
LINE1-R
41
ADOGND
ADOGND
ADOGND
4.7U/6.3V_6
AVDD2
20K/F_4
10u/6.3V_6
MONO-OUT
DMIC-1/2/GPIO0
R309
ADOGND
C475
0.1u/10V_4
38
C468
C466
10u/6.3V_6 0.1u/10V_4
C472
37
MONO-OUT
+5VA
FRONT-L
U10
5/10 Add
+5VA
U11
MONO-OUT
DIGITAL
1.6Vrms
+3V
PCBEEP
C448
C451
1u/10V_6 BEEP_1
C447
C428
10u/6.3V_6 0.1u/10V_4
100p/50V_4
R297
47K/F_4
SPKR
<9>
R296
4.7K_4
5/24 Delete
Place next to pin 1
+3V
PCH_AZ_CODEC_RST#
PCH_AZ_CODEC_SYNC
C430
ACZ_SDIN0_R
C445
Power (ADO)
DIGITAL
+5V
ANALOG
L58
<9>
*22p/50V_4
R551
22_4
PCH_AZ_CODEC_SDIN0
2
A
SHDN
SET
<9>
PCH_AZ_CODEC_BITCLK
<9>
INT MIC array
Place in Bottom of codec
CN4
R553
R569
R564
R563
R571
R311
C464
C689
*29.4K/F_4
*G923-330T1UF
R566
*10K/F_4
C707
C709
0_4
0_4
0_4
0_4
*0_4
*1000p/50V_4
*1000p/50V_4
1
2
R337
C492
INT_MIC
*22P_4
A
5/12 update Mic Partnumber & Footprint
C710
ADOGND
C467 .1U_4
Tied at one point only under

the codec or near the codec
5/27 cost down

ADOGND
PROJECT : ZQ9
ADOGND
Size
ADOGND
cap place close to MIC-connector
C730, C787 close U37 pin3 and L65

5
MIC2-VREFO
2.2K_4
*0_4
*10u/10V_3216
5/27 cost down
MIC2_INTL1
1
2
ADOGND
+
*0.1u/10V_4
6/18 stuff for EMI
*10u/10V_3216 *0.1u/10V_4
C708
R331
22p/50V_4
GND
10u/6.3V_6
Place next to pin 9
<9>
PCH_AZ_CODEC_SDOUT
UPB201209T-310Y-N/6A/31ohm_8
OUT
0.1u/10V_4
C429
U30
IN
C441
*100p/50V_4
+5VA
3
<9>
C431
Rev
1A
REALTEK ALC663&888/MDC
Date:
Document Number
Sheet
1
29
of
45
MIC
<29> MIC1-VREFO
D10
BAS316
D11
BAS316
Internal Speaker
Normal OPEN Jack
R325
4.7K/F_4
R324
4.7K/F_4
CN18
<29>
<29>
MIC1-L
C482
4.7u/6.3V_6
MIC1_L2
R318
1K/F_4
MIC1_L3
MIC1-R
C481
4.7u/6.3V_6
MIC1_R2
R317
1K/F_4
MIC1_R3
<29>
L35
L34
BLACK
1
2
6
3
4
MIC1_L
MIC1_R
MIC1_JD
CN16
<29>
<29>
INSPKRINSPKR+
R572
R570
R_SPK-_1
R_SPK+_1
*SHORT0603
*SHORT0603
2
1
MIC1_JD
2
1
INT_Speaker
5
MIC
C486
470p/50V_4
Max. 100mVrms input for Mic-IN
C484
470p/50V_4
MIC1_JD
C713
C714
*0.22u/25V_6 *0.22u/25V_6
ADOGND
ADOGND
D21
*VPORT_6
ADOGND
C
HP/SPDIF
<29>
HP_MUTE#
BLACK
<29>
HP-L
HP-L-2 R328
HP-R-2 R327
HPL-1
HPR-1
L37
L36
1 CN17
2
6
3
4
HPL_SYS
HPR_SYS
HP-L-2
Q23
*FDV301N
R322
56/F_4
56/F_4
C488
R326
R329
C487
*1K_4
*1K_4
2200p/50V_4 2200p/50V_4
<29>
8
5
JA6331-0230T3B-8H
HPOUT_JD
0_6
ADOGND
ADOGND
HP_MUTE#
B
<29>
HP-R
HP-R-2
Q24
*FDV301N
R321
0_6
HPOUT_JD
D12
2
*VPORT_6
ADOGND
PROJECT : ZQ9
Size
Document Number
Rev
1A
AMP /AUDIO JACK CONN

Date:
5
Sheet
1
30
of
45
2 IN 1 CARD READER (SD/MMC)
CARD READER Controller
SD_WP
SD_CMD
SD_DAT3
SD_DAT2
4
CD/SW
13
SD-CARD
GND1
VCC_XD
DATA1
DATA0
VSS2
CLK
VDD
VSS1
CMD
DATA3
DATA2
14
SD_CLK
WP/SW
SW COM
10
9
8
7
6
5
3
2
1
GND
CN3
SD_DAT1
SD_DAT0
11
12
SD_CD#
5/10 Del R40001

VCC_XD
C454
C442
4.7u/10V_6
Clock input selection

'1' for 48MHz input [Default,Internal PU]
'0' for 12MHz input
C708 close PIN48, 47
+3V_VDD
C692
C694
0.1u/16V_4
0.1u/16V_4
T95
48
47
46
45
44
43
42
41
40
39
38
37
5/10 Modify
+3V_VDD
U28
C700 *0.47u/10V_6
+3V
R557
*SHORT0603
C701
+3V_VDD
4.7u/10V_6
R560 330_4
<10>
<10>
USBP12+
USBP12C698
C699
*5p/50V_4
*5p/50V_4
XI
XO
+1.8V_VDD
1
2
3
4
5
6
7
8
9
10
11
12
8/14 C707 close PIN11, 12
CTRL0, CRTL 1 trace length shorter ,

and surround with GND.
VDDHM
GND
VDD
XTALSEL
TRIST
NBMD
CTRL1
CTRL3
DATA1
DATA0
DATA7
DATA6
<4,10,11,25,27,35> PLTRST#
*100K_4
GPON7
EXT48IN
RSTN
REXT
VD33P
DP
DM
VS33P
XI
XO
VDD
VDD
AU6437-GBL
36
35
34
33
32
31
30
29
28
27
26
25
CTRL0
CTRL2
GPI4
DATA0
SD_DAT0
DATA1
SD_DAT1
DATA2
SD_DAT2
DATA3
SD_DAT3
T89
DATA3
DATA2
GPI2
T90
EEPDATA
GPI1
T91
T92
Close to connector
2
13
14
15
16
17
18
19
20
21
22
23
24
CTRL0
DATA5
CTRL2
GPI4
DATA4
DATA3
DATA2
XDWPN
GPI2
XDCEN
EEPDATA
GPI1
V18
CF_V33
VCC33
AGND5V
V33
VDDHM
GND
VDD
CTRL4
XDCDN
SDWPEN
EEPCLK
R559
Close to CN14 pin 14 & pin23

4.7u CAP close to pin23
5/10 change Card Redaer conn
footpirnt sdcard-sdsn09-08-xa-11p-smt
8/14 ZH7 remove R136, R591 and C775
*Short_4
DFHS11FR033
T97
XTALSEL
R562
Second
0.1u/16V_4
XTALSEL
CRMD_N
NBMD
CTRL1
CTRL3
DATA1
DATA0
*Short_4
DFHS11FR011
C743 close PIN46, 47
+1.8V_VDD
R554
Main
crystal trace width needs at least 10 mils.
8/14 pin13 output 20mils

EEPCLK
18p/50V_4
XI
4.7u/10V_6
C703
18p/50V_4
CTRL0
R558
270K_4
*0_4
VCC_XD
Y7
12MHz
T94
VCC_XD
C696
C702
XO
+1.8V_VDD
+3V_VDD
+3V_VDD
C690
C691
4.7u/10V_6
0.1u/16V_4
R300
SD_CLK
CTRL1
SD_WP
CTRL2
SD_CMD
CTRL3
SD_CD#
C449
*10p/50V_4
R552
SD write protect
1:decided by SDWP[Default]
0:letting SD always
write-able
PROJECT : ZQ5
Size
Document Number
Rev
1A
AU6433 CardReader
Date:
A
Sheet
E
31
of
43
LED
+3V_S5
POWER
+3V
5/13 Delete CAP & NUM LED
LED3
<35>
LED1
Power LED
Amber
Bule
R1
SUSLED#
<35> PWRLED#
182/F_4
R340
715/F_4
R342
20/F_4
2
1
LED_A/B
Blue
R339
*1M_4
R336
*1M_4
+3VPCU
+3VPCU
Battery
Amber
LED4
<35> BATLED1#
<35> BATLED0#
R338
715/F_4
R335
20/F_4
2
1
LED_A/B
Blue
+3V
+3V
HDD
WIFI LED
+3V
Amber
LED5
R333
10K/F_4 1
Bule
R341
182/F_4
R332
R334
<27> RF_LED#
SATA_ACT#
<9>
SATA_LED#_R LED2
715/F_4
U12
*TC7SH08FU
LED_AMBER
*Short_4

PROJECT : ZQ9
Size
Document Number
Rev
1A
POWER/MMB/LAUNCH/LED
Date:
5
Sheet
32
1
of
45
USB
BLUETOOTH CONNECTOR for 2.0

6/18 add
+5V_S5
CN19
+3V_S5
BT_POWER_2
C455
U9
1U/6.3V_4
D
<35>
USBON#
2
3
IN1
IN2
4
1
EN#
GND
OUT3
OUT2
OUT1
8
7
6
OC#
USBPWR1
+ C717
2.2u/6.3V_6
AO3413
5
4
3
2
1
USB_BT+_R
USB_BT-_R
Q25
C715
1000p/50V_4
T102
BT_LED_2
<35> BT_POWERON#
C693
+
7
6
BT_CONN
C465
1000p/50V_4
R574
L59
3 3
2 2
<10,27> USBP13+
<10,27> USBP13-
330u/6.3V_6X5.7
G547F2P81U
0_4
4
1
4
1
C716
*.01u/16V_4
USB_BT+_R
USB_BT-_R
*RFCMF1632100M3T/200mA/90ohm
R573
0_4
<10> USB_OC0#
R310
1
2
3
4
8
7
6
5
8
7
6
5
BT_POWER
AO3413
+ C705
2.2u/6.3V_6
5
4
3
2
1
USBP4+_R
USBP4-_R
Q22
C706
1000p/50V_4
T101
BT_LED
1
4
USBP1-_R
USBP1+_R
DLW21HN900SQ2L/300mA/90ohm
R312
*0_4
RV2
RV1
*EGA-0402
*EGA-0402
7
6
BT_CONN
1
4
2
3
CN15
<35> BT_POWERON#
1
2
3
USBP1USBP1+
+3V_S5
USB_MB_Turbo
*0_4
L33
<10>
<10>
BLUETOOTH CONNECTOR for 3.0
CN14
1
2
3
4
USBP1-_R
USBP1+_R
<10>
<10>
R567
L57
3 3
2 2
USBP4+
USBP4-
C712
*.01u/16V_4
0_4
4
1
4
1
USBP4+_R
USBP4-_R
C
*RFCMF1632100M3T/200mA/90ohm
R568
0_4
+5V_S5
USB/B
5/13 reserve pi-filter

C446
*1u/6.3V_4
R279
0_1206
C409
*1u/6.3V_4
USB_DB FFC CONN
R261
*0_4
L29
<10>
<10>
USBP9+
USBP9-
2
3
2
3
1
4
1
4
USBP9+_R
USBP9-_R
<10> USB_OC4_5#
R262
*0_4
USBP11-_R
USBP11+_R
R274
USBP9-_R
USBP9+_R
*0_4
L31
<10>
<10>
USBP11+
USBP11-
2
3
2
3
1
4
1
4
USBP11+_R
USBP11-_R
<35>
USBON#
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
17
1
18
CN10
R273
*0_4
5/11 update the footprint

A

PROJECT : ZQ9
Size
Document Number
Rev
1A
USB/ BT
Date:
5
Sheet
1
33
of
45
CPU FAN
CN2
MY7
MY6
MY5
MY4
MY11
MY10
MY9
MY8
MY15
MY14
MY13
MY12
MX4
MX5
MX6
MX7
C549
2.2U_6
10K_4
6/20 change th P/N
<35>
VO
GND
/FON GND
GND
VSET GND
CPUFAN#
CN6
VIN
<10,11,35> SML1ALERT#
<35>
FANSIG
U17
2
3
5
6
7
8
TH_FAN_POWER
G995P1U
1
2
3
C547
C548
C546
2.2U_6
.01U_4
*.01U_4
FAN_CONN
FANPWR = 1.6*VSET
27
28
KB
+3VPCU
MX1
MX0
R385
+5V
MY3
MY2
MY1
MY0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
MX6
MX7
MY17
MY16
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
MX7
MX6
MX5
MX4
MX3
MX2
MX1
MX0
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
MX7
MX6
MX5
MX4
MX3
MX2
MX1
MX0
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
MX3
MX2
MX4
MX5
7
8
5
6
3
4
1
2
CP6
*100p/50Vx4
7
8
5
6
3
4
1
2
CP5
*100p/50Vx4
7
8
5
6
3
4
1
2
CP4
*100p/50Vx4
7
8
5
6
3
4
1
2
CP3
*100p/50Vx4
7
8
5
6
3
4
1
2
CP2
*100p/50Vx4
7
8
5
6
3
4
1
2
CP1
*100p/50Vx4
C222 *100p/50V_4
C221 *100p/50V_4
+3V
K/B
RP3
10
9
8
7
6
TOUCHPAD & Switch CONN.
10K_10P8R
1 MX3
2 MX2
3 MX1
4 MX0
5
+5V
+5V
L20
+TPVDD
0_6
C223
HOLE
R86
10K_4
R87
10K_4
0.1u/10V_4_X7R
CN1
HOLE2
HOLE18
HOLE19
*hg-c315d110p2 *HG-C315D154P2 *H-C256D161P2
7
6 7
6
8
5 8
5
9
4 9
4
HOLE21
HOLE3
*H-C197D87P2 *H-C94D94N
HOLE5
*h-c1417d1417na1457
<35>
TPDATA
<35>
TPCLK
L18
0_6
L19
0_6
TPDATA_R
TPCLK_R
*.01u/25V_4
*.01u/25V_4
5/12 add
LEFT#
HOLE11
*H-TC256BC165D165P2
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
HOLE12
*H-TC256BC165D165P2
SW3
3
1
RIGHT#
HOLE6
HOLE17
HOLE10
HOLE16
HOLE7
*hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2
7
6 7
6 7
6 7
6 7
6
8
5 8
5 8
5 8
5 8
5
9
4 9
4 9
4 9
4 9
4
13
14
Aces 88501-120N
HOLE8
*H-TC256BC165D165P2
1
2
3
6/18 change
1
2
3
1
2
3
1
2
3
1
2
3
HOLE13
HOLE14
HOLE15
HOLE4
HOLE9
*hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2
7
6 7
6 7
6 7
6 7
6
8
5 8
5 8
5 8
5 8
5
9
4 9
4 9
4 9
4 9
4
C220
RIGHT#
1
2
3
1
2
3
C219
1
2
3
4
5
6
7
8
9
10
11
12
LEFT#
2
4
SW2
3
1
SWITCH_1.5
2
4
SWITCH_1.5
HOLE20
*H-C256D161P2
5/24 add
PAD2
*SPAD-C200NP
PAD3
*SPAD-C200NP
6/21 add
A
PAD1
*SPAD-C200NP
5/21 add
1
2
3
HOLE1
*HG-C315D118P2
7
6
8
5
9
4
5/27 Delete HOLE4, HOLE22
PROJECT : ZQ9
Size
Document Number
Rev
1A
KB/FAN/TP+FP
Date:
5
Sheet
1
34
of
45
EC(KBC)
L22
PBY160808T-250Y-N/3A/25ohm_6
I/O ADDRESS SETTING(KBC)
+A3VPCU
+3V
C226
30mil
C227
0.1u/10V_4_X7R
10u/10V_6
+3VPCU
R108
1
E775AGND
2.2_6
2
D15
0.03A(30mils)
+3VPCU_EC
0.1u/10V_4_X7R
*.1u/16V_4
0.1u/10V_4_X7R U18
C570
C571
4.7U/6.3V_6
0.1u/10V_4_X7R
0.1u/10V_4_X7R
*.1u/16V_4
C225
VDD
4.7U/6.3V_6
C229
102
C551
AVCC
C593
VCC1
VCC2
VCC3
VCC4
VCC5
C538
19
46
76
88
115
BAS316
C573
C595
E775AGND
10u/6.3V_8 ICMNT
C605
D3
<11> SIO_EXT_SCI#
C228
*10p/50V_4
BAS316
EC_FPBACK#
<23> EC_FPBACK#
PLTRST#
<33> USBON#
<9> IRQ_SERIRQ
6
NOCIR#
T60
<4,10,11,25,27,31>
29
USBON#
123
IRQ_SERIRQ
125
9
<11> SIO_EXT_SMI#
<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
<36>
MBCLK
<36>
MBDATA
<10> 2ND_MBCLK
<10> 2ND_MBDATA
R390
<8> ICH_SUSCLK
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
54
55
56
57
58
59
60
61
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
MBCLK
MBDATA
2ND_MBCLK
2ND_MBDATA
70
69
67
68
TPCLK
TPDATA
PCH_ACIN
<34>
TPCLK
<34>
TPDATA
<8> PCH_ACIN
<33> BT_POWERON#
<19,39,40,43> MAINON
T55
124
PLTRST#
72
71
10
11
12
13
MAINOND
*Short_4
E775_32KX1
R392
*20M_6
E775_32KX2
R398
Y4
77
79
GPIO94/DA0
GPI95/DA1
GPI96/DA2
GPI97
101
105
106
107
GPIO11/CLKRUN
GPIO85/GA20
D/A
KBRST/GPIO86
LPC
ECSCI/GPIO54
GPIO24/LDRQ
GPIO10/LPCPD
LREST
GPIO67/PWUREQ
SERIRQ
GPIO65/SMI
GPIO
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
KBSOUT0/JENK
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KB
KBSOUT4/JEN0
KBSOUT5/TDO
KBSOUT6/RDY
KBSOUT7
KBSOUT8
KBSOUT9/SDP_VIS
KBSOUT10/P80_CLK
KBSOUT11/P80_DAT
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17
GPIO17/SCL1
GPIO22/SDA1
GPIO73/SCL2
GPIO74/SDA2
PS/2
TIMER
GPIO77/SPI_DI
GPO76/SPI_DO/SHBM
GPIO75/SPI_SCK
SPI
GPIO72/IRRX1/SIN2
GPIO70/IRRX2_IRSL0
GPIO71/IRTX/SOUT2
GPIO87/CIRRXM/SIN_CR
GPIO34/CIRRXL
GPIO16/CIRTX
GPO83/SOUT_CR/XORTR
F_SDI
F_SDO
F_CS0
F_SCK
FIU
GPIO55/CLKOUT/IOX_DIN
GPIO02
4
L21
GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
GPIO66/G_PWM
SHBM=0: Enable shared memory with host BIOS
WL_SW
T58
VCC_POR
PBY160808T-250Y-N/3A/25ohm_6
C552
*15p/50V_4
VREF
T6
T7
31
117
63
ACIN
NBSWON#
<34>
T61
MXM_SMDATA12 <21>
BATLED0# <32>
BATLED1# <32>
VRON <38>
SUSLED# <32>
AC_OFF
AMP_MUTE# <29>
T49
T48
T47
T46
R92
R91
MXM_SMCLK12
MXM_SMDATA12
R100
R98
2ND_MBCLK
2ND_MBDATA
R88
R89
10K_4
10K_4
VGA_THERM#
R416
EV@10K_4
+3V_D_S
[email protected]_4
[email protected]_4
T44
DNBSWON# <8>
T50
ODDLED
T45
SUSON <40>
FANSIG <34>
CONTRAST <23>
T63
PWRLED# <32>
T5
SPI FLASH(KBC)
T54
T51
SHBM_R
+3VPCU
U19
SPI_SDI_uR R99
75
73
74
113
14
114
111
RSMRST#_uR
R90
*Short_4
PWROK_EC_uR
R386
*Short_4
86
87
90
92
SPI_SDI_uR
SPI_SDO_uR_R
SPI_CS0#_uR
SPI_SCK_uR_R
30
ECDB_CLOCK
T43
85
VCC_POR#
R415
104
VREF_uR
T53
R96
ICH_RSMRST# <8>
SUSC# <8>
PWROK_EC <8>
RF_EN <27>
P_SAVE_LED#
22_4 SPI_SDI_uR_R
*100K_4
7/24 modify
+3VPCU
HWPG
R101
10K_4
SPI_SDO_uR
SPI_SCK_uR
SPI_CS0#_uR
T59
R97
22_4
SPI_SDO_uR
R102
22_4
SPI_SCK_uR
R107
47K/F_4
*Short_4
SO
VDD
SI
HOLD
SCK
WP
CE
VSS
W25X40BVSSIG
8
7
C591
0.1u/10V_4
1/13 Comfirm by vendor mail :

If the Southbridge enables 'Long Wait Abort' by
default, the flash device should be 50MHz (or faster)
HWPG(KBC)
+3VPCU
+3V
+A3VPCU
R110
10K_4
SM BUS ARRANGEMENT TABLE

SM Bus 1
<43> HWPG_1.8V
Battery
<39> HWPG_1.05V
SM Bus 2
PCH
SM Bus 3
GPU-I2C
SM Bus 4
N/A
<40> HWPG_1.5V
1u/6.3V_4
E775AGND
<37> SYS_HWPG
<41> HWPG_GFX
POWER-ON Switch(KBC)
10K_4
10K_4
D/C#
<36>
S5_ON <37,44>
HDMI_HPD_EC# <24>
32
118
62
81
84
83
82
MBCLK
MBDATA
+3V
T52
3G_SW
+3VPCU
<36>
LID591# <23>
SUSB# <8>
MXM_SMCLK12 <21>
C539
E775AGND
10K_4
1/13 Comfirm by vendor mail :

Disabled ('1') if using FWH device on LPC.
Enabled ('0') if using SPI flash for both system BIOS and EC firmware
VGA_THERM# <21>
CPUFAN#
R405
SHBM_R
SHBM
SML1ALERT# <10,11,34>
ICMNT <36>
SM BUS PU(KBC)
64
95
93
94
119
109
120
65
66
15
16
17
20
21
22
23
24
25
26
27
28
91
110
112
80
TEMP_MBAT <36>
5/17 Change to test pad
GPIO00/32KCLKIN
NPCE781
GPIO01/TB2
GPIO03
GPIO06/IOX_DOUT
GPIO07
GPIO23/SCL3
GPIO30/CIRTX2
GPIO31/SDA3
GPIO32/D_PWM
GPIO33/H_PWM
GPIO36
GPIO40/F_PWM
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO45/E_PWM
GPIO46/CIRRXM/TRST
GPO47/SCL4
GPIO50/TDO
GPIO51
GPIO52/CIRTX2/RDY
GPIO53/SDA4
GPIO81
GPO82/TEST
GPO84/TRIST
GPIO41
GPIO56/TA1
GPIO20/TA2/IOX_DIN
GPIO14/TB1
SMB IR
GPIO37/PSCLK1
GPIO35/PSDAT1
GPIO26/PSCLK2
GPIO27PSDAT2
GPIO25/PSCLK3
GPIO12/PSDAT3
*33K/F_4
C550
*32.768KHz
*15p/50V_4
97
98
99
100
108
96
VCORF
<11> SIO_RCIN#
122
AGND
121
GPIO90/AD0
GPIO91/AD1
GPIO92/AD2
GPIO93/AD3
GPIO05
GPIO04
VCORF_uR 44
*22_4
CLKRUN#
<11> SIO_A20GATE
A/D
103
<8>
R106
CLK_PCI_775
LFRAME
LAD0
LAD1
LAD2
LAD3
LCLK
GND1
GND2
GND3
GND4
GND5
GND6
CLK_PCI_775
3
126
127
128
1
2
5
18
45
78
89
116
<9,27> LPC_LFRAME#
<9,27> LPC_LAD0
<9,27> LPC_LAD1
<9,27> LPC_LAD2
<9,27> LPC_LAD3
<10> CLK_PCI_775
0.01u/16V_4
D9
BAS316
D7
BAS316
D8
BAS316
D6
BAS316
D5
IV@BAS316
HWPG
R109
*Short_4
MPWROK <4>
INTERNAL KEYBOARD STRIP SET(KBC)
6/21 unstuff
SW1
*MSK:NTC031-AC1G-A120T
D2
BAS316
1
3
NBSWON#
R393
10K_4
D1
*VPORT_6
+3VPCU
MY0
2
4
5
6
PROJECT : ZQ9
Size
5/13 change the location

4
Rev
1A
WPCE781 & FLASH

Date:
Document Number
Sheet
1
35
of
45
POWER_JACK
dcjk-2dc2003-000111-3p-v
PJ1
1
2
VA1
6/9 change the P/N to 3720
PD6
SBR1045SP5-13
1
PL2
HI0805R800R-00_8
VA
PQ29
FDD6685
VIN
PQ27
FDD6685
VA2
7
6
5
4
PC82
0.1u/50V_6
PC81
0.1u/50V_6
PL1
HI0805R800R-00_8
PR147
220K_4
PR145
0.01_3720
PR146
SHORT_PAD_4
PD5
SMAJ20A
PR144
SHORT_PAD_4
PC6
0.1u/50V_6
PC1
2200p/50V_6
PR156
33K/F_4
5/14 add short PAD
CSIN_1
CSIP_1
PC79
PC80
2200p/50V_6*47u/25V_6.3*6
1
PD1
SW1010CPT
5/12 EMI RESERVE
PR148
220K_4
5/14 add short PAD
D/C#
PR157
10K_4
<35>
PR149
*SHORT_PAD_4
PC78
0.1u/50V_6
PQ28
IMD2AT108
CSIN_1
2
PQ32
DMN601K-7
CSIP_1
VIN
PC11
1u/16V_6
PR8
10/F_4
PC14
0.1u/50V_6
27 CSIN
PC7
1u/16V_6
21
5
6
7
8
ISL88731_VDDP
PD7
*RB500V-40
<35>
MBDATA
<35>
MBCLK
ACIN
PR5
49.9/F_6
SDA
UGATE
24
SCL
PHASE
23
ISL88731_PHASE
13
ACOK
LGATE
20
ISL88731_LGATE
PGND
19
22
DCIN
88731ACSET
PC2
100p/50V_6
ACIN
VREF
ICOMP
PU1
ISL88731A
CSOP
CSON
17 CSON
NC
16
VBF
15
GND
29
PR152
100K_4
PR10
2.21K/F_4
PR155
*4.7_6
CSOP_1
PC88
*680p/50V_6
CSOP_1
PC85
2200p/50V_6
PC86
10u/25V_1206
PC87
10u/25V_1206
BAT-V
BAT-V
0618 change to AO4468
PR1
10/F_4
GND
BAT-V
PR2
100_4
12
TEMP_MBAT <35>
NC
TEMP_MBAT
VCOMP
NC
BAT-V
PR4
*SHORT0402
NC
14
PR153
100_4
ICM
10 1
2
3
4
5
6
7
9 8
0.01_3720
PR158
PL5
6.8uH
PC8
0.1u/50V_6
5
PL3
HI0805R800R-00_8
PQ31
AO4468
PQ30
AO4468
18 CSOP
BAT-V
C114F3-108A1-L_Batt_Conn
PR3
10/F_4
MBAT+
PR12
22K/F_4
PL4
HI0805R800R-00_8
PC10
0.1u/50V_8
88731B_1
PR11
82.5K/F_4
PC3
0.1u/50V_6
2
1
PR6
2.7_6
25 88731B_2
10
PC9
0.1u/50V_6
DCIN
VDDP
BOOT
ISL88731_UGATE
PR7
100K_4
<35>
VDDSMB
PC84
10u/25V_1206
PC83
2200p/50V_6
3
2
1
11
VCC
PC12
0.1u/50V_6
+3VPCU
CSSN
NC
GND
GND
GND
GND
CSSP
+3VPCU
3
2
1
26
1
33
32
31
30
28 CSIP
PR159
4.7_6
5
6
7
8
PR9
10/F_4
+3VPCU
PJ2
PC5
47p/50V_6
PC4
47p/50V_6
PC13
0.01u/50V_6
ICMNT
PR154
*SHORT_PAD_4
PR150
100_4
PR151
100_4
PC15
PC16
*1u/16V_6 0.01u/50V_6
MBCLK
<35>
MBDATA
<35>
ISL88731 thermal pad

tie to Pin12
ICMNT
<35>
PC17
*0.01u/50V_6
PU6
CM1293A-04SO
TEMP_MBAT
CH1
VN
CH2
CH4
VP
CH3
MBDATA
+3VPCU
MBCLK
PROJECT : ZQ9
Size
Add ESD diode base on EC FAE suggestion
Rev
1A
Charger(ISL88731A)
Date:
Document Number
Sheet

1
36
of
MAIND
MAIND
<40,43>
VL
6/14 remove JP2 , T25 and T26
<4,44> SYS_SHDN#
PR112
*SHORT_PAD_4
VIN
PR111
39K/F_4
3V5V_EN
PR110
*SHORT_PAD_4
4.7u/25V_0805
PR108
*SHORT_PAD_4
PC70
4.7u/10V_8
PR232
*SHORT_PAD_4
PR133
*SHORT_PAD_4
PC165
2.2n/50V_4
PC171
4.7u/25V_0805
OCP:9A
1
4.7u/25V_0805
PC169
PC173
100u/25V_6X5.7
PC170
VL
VIN
8206_ONLDO
0.1u/50V_6
5V_DL
4
PD9
*SX34
PC66
0.1u/50V_6
PC58
*680p/50V_6
PQ11
AO4710
1
2
3
PR117
*SHORT_PAD_4
6/9 unstuff
PR107
1/F_6
3
2
1
3V_LX
SKIP
DDPWRGD_R
3V_EN
5
6
7
8
PR130
220K/F_4
2
PR126
*0_4
PC59
*680p/50V_6
PC65
0.1u/50V_6
PR106
1/F_6
2
PR98
*4.7_6
PD10
*SX34
LDOREFIN
LDO
VIN
NC
ONLDO
VCC
TON
REF
REFIN2
1
6/9 unstuff
PQ12
AO4710
PR124
+3VPCU_OUT
+
PC178
0.1u/50V_6
PC175
330u/6.3V_6X5.7
*SHORT_PAD_4
1
PR129
2
*0_4
3V_DL
32
31
30
29
28
27
26
25
REFIN2
ILIM2
OUT2
SKIP#
PGOOD2
EN2
DH2
LX2
PU5
RT8206B
PL14
2.2uH
PC174
330u/6.3V_6X5.7
PR97
*4.7_6
PAD
PAD
PAD
PC177
35
34
33
PQ14
AO4468
3
2
1
8
7
6
5
1
PR116
147K/F_4
BYP
OUT1
FB1
ILIM1
PGOOD1
EN1
DH1
LX1
PAD
PAD
17
18
19
20
21
22
23
24
1
2
3
5V_LX
PR125
*0_4
9
10
11
12
DDPWRGD_R 13
5V_EN 14
15
16
37
36
BST1
DL1
PVCC
NC
GND
PGND
DL2
BST2
+5VPCU
C
PR233
*0_6
8
7
6
5
4
3
2
1
PR134
150K_4
5V_DH
PQ13
AO4468
PL13
2.2uH
3V_DH
PC176
*10u/25V_1206
PC73
0.1u/50V_6
REF
8
7
6
5
+3VPCU
PC71
0.01u/16V_4
+5VPCU
6.8A
PR234
*0_4
5
6
7
8
PC74
1u/16V_6
PC72
0.1u/50V_6
5A
PR135
390K_4
3V_EN
5V_EN
PC63
2.2n/50V_6
OCP:6.5A
2
PD3
CHN217
SKIP
VL
PC77
0.1u/50V_6
PD4
CHN217
*SHORT_PAD_4
PR235
PR104
*SHORT_PAD_6
PC76
0.1u/50V_6
1
+15V_ALWP
+15V
PR132
22_8
2
PR137
*200K/F_4
PC69
0.1u/50V_6
PR139
22_8
PR143
1M_6
+5VPCU
PR142
*1M_6
+5VPCU
+3VPCU
PQ56
AO4468
PQ58
AO4468
PQ57
AO3404
0.23A
PQ19
DMN601K-7
PC75
*2.2n/50V_4
3
2
1
PQ18
DMN601K-7
3
2
1
3
2
1
+3V_S5
PQ17
DMN601K-7
PR141
1M_6
PQ16
DTC144EU
SYS_HWPG <35>
PR114
*SHORT_PAD_4
PQ15
AO4468
2
2
DDPWRGD_R
MAIND 4
MAIND
<35,44> S5_ON
+3VPCU
S5D
S5D
PR109
*100K/F_4
PR138
22_8
VIN
OCP:9A
L(ripple current)
=(9-3.3)*3.3/(2.2u*0.5M*9)
=1.9A
5
6
7
8
PR140
1M_6
+15V
+5V_S5
5
6
7
8
+3V_S5
+3VPCU
Iocp=9-(1.9/2)=8.05A
Vth=8.05A*14.2mOhm=114.31mV
R(Ilim)=(114.31mV*10)/5uA=228.62K
Ipeak(choke)=11.479A
PR105
*39K/F_4
5
6
7
8
VIN
PR131
*0_4
PR115
*SHORT_PAD_4
L(ripple current)
=(9-5)*5/(2.2u*0.4M*9)=2.525A
Iocp=6.5-(2.525/2)=5.24A
Vth=5.24A*14.2mOhm=0.074V
R(Ilim)=(0.07437V*10)/5uA=148.74K
Ipeak(choke)=10.687A
REF
OCP:6.5A
B
2
PR113
*0_4
PC64
1u/16V_6
1
PC67
0.1u/50V_6
PR231
*SHORT_PAD_6
PR103
*0_6
+5VPCU_FB
+5V_S5
+5V
2.85A
2.171A
+3V
PROJECT : ZQ9
2.66A
Size
Document Number
Rev
1A
SYSTEM 5V/3V (RT8206)

Date:
5
Sheet
1
37
of
VID 1.2875V
H_VID2
PR197
*0_4
H_VID3
+VCC_CORE
Countinue current:36A
Peak current:48A
OCP minimum 55A
Loadline=1.9mV/A (IMVP 6.5)
Rilm=1.69K
VIN
6/14 remove JP7,T56 and T57
PQ41
AOL1448
*0_4
<4,8>
PR198
DELAY_VR_PWRGOOD
Connect to input caps

1
H_VID1
H_VID0
*0_4
*0_4
PR200
PR199
+3VPCU
PR55
1K/F_4
PR52
649K/F_4
PR203
PR39
1.91K/F_4
PR50
*499/F_4
1
2
3
38
39
AGND
DRVH1
35
3212_DH1
49
AGND
BST1
36
3212_BOOT1
PR38
2.2_6
41
PSI#
34
3212_SW1
31
3212_DL1
10
H_VID2
<6>
H_VID3
<6>
H_VID4
<6>
H_VID5
<6>
H_VID6
PR37
VRON
PR32
<6> H_DPRSLPVR
PR36
100K/F_4
26
CPU_VID2
46
VID2
BOOT2
25 3212_BOOT2
CPU_VID3
45
CPU_VID4
44
CPU_VID5
43
CPU_VID6
42
*SHORT_PAD_4 VR_ON
DPRSLPVR_R 40
499/F_4
PC27
150p/50V_4
PR49
2.2_6
VID3
VID4
PC133
4.7u/25V_8
3212_FB
PC132
4.7u/25V_8
SW2
29
3212_DL2
1
PQ46
AOL1718
VID6
EN
DRVL2
DPRSLPVR
PQ47
AOL1718
6/21 stuff 6/21 unstuff
PR54
*2.2/F_6
4
4
PGND
30
SWFB2
28
PC32
*1000P/50V_6
CLK_EN#
PR48
100/F_4
PWM3
SWFB1
SWFB3
PC117
0.1u/50V_6
PC128
*330u/2V_7343
PR60
10/F_6
PC30
330u/2V_7343
3212_CS_PH2
5/19 change to 0603
OD3#
33
PR44
100/F_4
3212_CS_PH1
B
3212_CSSUM
19
FB
PR61
127K/F_6
PR58
165K/F_4
PR56
127K/F_6
PC34
1000p/50V_4
PC33
560P/50V_4
COMP
CSCOMP
1.65K/F_4
CSREF
RPM
14
13
PR204
4.75K/F_4
1
2
Short the net trace
LLINE
17
3212_CSCOMP
ILIM
21
3212_ILIM
PR57
73.2K/F_4
Close to Phase 1 Inductor
PR51
1.69K/F_4
18
IMON
IREF
PR190
220K_6 NTC
20
FBRTN
RT
15
1000p/50V_4
+VCC_CORE
PL9
0.36uH
3212_SW2
PC26
12p/50V_4
3212_COMP 7
PC127
PC134
4.7u/25V_8
PC31
0.22u/25V_6
27
VID5
CSSUM
PR45
39.2K/F_4
PC135
0.1u/50V_6
PR59
*SHORT_PAD_4
24
3212_CSREF
PC126
0.082u/16V_4
<6>
3212_DH2
1.91K/F_4
23
3212_FBRTN
PQ48
AOL1448
4.7U/6.3V_6
DRVH2
PC28
150p/50V_4
VID1
22
PR46
32
47
4
PR43
PVCC
CPU_VID1
<3> VR_PWRGD_CK505#
+3VPCU
PC29
ADP3212
VID0
<6>
48
H_VID1
CPU_VID0
+5VPCU
PU2
TRDET#
VARFR
<6>
PC137
100u/25V_6X5.7
TTSNS
H_VID0
5.1K/F_4 8
9
11
PR47
1
2
3
PC129
1
*0.01U/16V_4
<6>
7.32K/F_4
+5VPCU
+5VPCU
PR191
<35>
DRVL1
PR207
*220K_6 NTC
VIN
This NTC Close to Phase 1 Inductor
Panasonic
ERT-J0EV474J
6/14 remove JP8,T76 and T77
VR_TT
1
2
3
PC25
0.22u/25V_6
SW1
PR31
*SHORT_PAD_4
5/19 change to 0603
12
1
2
3
PSI#_1
H_PSI#
PR33
10/F_6
PR30
*SHORT_PAD_4
<4> H_PROCHOT#
<6>
PQ9
*DMN601K-7
PC22
330u/2V_7343
PC123
*330u/2V_7343
PWRGD
PH1
VCC
PC23
2.2U/6.3V_6
RAMP
+1.05V
PC24
*1000P/50V_6
PH0
37
3212_VCC
+
PC136
0.1u/50V_6
6/21 stuff
16 3212_RAMP
PR34
10_6
6/21 unstuff
PR35
*2.2/F_6
4
*SHORT_PAD_8
PQ42
AOL1718
PQ43
AOL1718
+5VPCU
*SHORT_PAD_4
CSREF
PR53
*SHORT_PAD_4
I_MON
PC131
1u/6.3V_4
PR202
*0_4
PR206
*27.4_4
+1.05V
PR210
80.6K/F_4
PR208
162K/F_4
Peak :40A ; OCP:53A (1.69K/F_4)

Peak :48A ; OCP:55A (1.74K/F_4)
PR209
69.8K/F_4
PR42
*SHORT_PAD_4
VSSSENSE <6>
VCCSENSE <6>
PR41
*SHORT_PAD_4
PR40
*27.4_4
PROJECT : ZQ9
Size
+VCC_CORE
Document Number
Rev
1A
+VCC_CORE ADP3212
Date:
+VCC_CORE
1
PC130
1000p/50V_4
PR236
H_VID6
PC122
PC124
4.7u/25V_8 100u/25V_6X5.7
PL8
0.36uH
*0_4
PC120
4.7u/25V_8
6/9 preserved
PR193
PC121
4.7u/25V_8
*0_4
PC179 PC118
*100u/25V_6X5.7
0.1u/50V_6
4
+5VPCU +3VPCU
1
2
3
PR195
H_VID5
1
2
3
H_VID4
*0_4
PR196
+3VPCU
Sheet
1
38
of
6/14 Remove JP13 ,T84,T85
[PWM]
VIN
+5V_S5
6/9 preserved
<35> HWPG_1.05V
UGATE
12
UGATE-1.05V
VOUT
PHASE
11
PHASE-1.05V
OC
10
VDD
FB
PGOOD
GND
NC
14
NC
VDDP
LGATE
PGND
TPAD
17
1
2
3
TON
PC42
1u/16V_6
13
6/14 Remove JP11 ,T83,T82

PL12
0.56uH
PR94
2.15K/F_4
PR74
*10K/F_4
16
PC54
0.1u/50V_6
BOOT
PC55
1u/16V_6
PR86
*4.7_6
LGATE-1.05V
PQ54
AOL1718
PQ52
AOL1718
1
2
3
PC48
*0.1u/50V_6
EN/DEM
560u/2.5V
PC180 PC168
PC164
100u/25V_6X5.7
PQ55 100u/25V_6X5.7 2.2n/50V_4
AOL1448
+3V
15
1
2
3
PR91
*SHORT_PAD_4
<19,35,40,43> MAINON
5/19 change location

4.7u/25V_08054.7u/25V_0805
PC144
+
PC56
4.7u/6.3V_6
+1.05V
PC163
PD2
RB500V-40
PR95
0_6
PU4
UP6111AQDD-B3
PC57
PR96
2.2/F_6
PR79
1M/F_4
PR71
10_6
OCP: 23A
19A
5/19 add
PC47
*680p/50V_6
PC146
*10u/10V_8
PC46
*1000p/50V_6
PC145
0.1u/50V_6
PC153
560u/2.5V
R1
PR75
4.02K/F_4
PC41
*33p/50V_6
1.05V_FB
R2
PR73
10K/F_4
PR237
TON=3.85p*RTON*Vout/(Vin-0.5)
Frequency=Vout/(Vin*TON)
A
TON=3.85p*1M*1/(Vin-0.5)
AO1718 Rdson=3~4.3mOhm
L(ripple current)
=(19-1.05)*1.05/(0.56u*272k*19)
~6.512A
*SHORT_PAD_4
PR222
*SHORT_PAD_6
RILIM=2.15mohm*23-3.256/20uA=2.122Kohm
I(choke)peak=29.512A
Frequency=1/(0.0036767)=272K
PROJECT : ZQ9
Size
Document Number
Rev
1A
+VTT (UP6111A)
Date:
5
Sheet
1
39
of
[PWM]
PC162
10u/10V_8
6/14 Remove JP12 , T86 and T87
PR223
*SHORT_PAD_6
PC161
0.1u/50V_6
8207A_VBST
+0.75V_DDR_VTT
VIN
8207A_DH
PC49
4.7u/25V_0805
8207A_DL
5/19 add
8207A_LX
2.25A
PC166
10u/10V_8
PC167
10u/10V_8
PC158
4.7u/25V_0805
+1.5VSUS
GND
LL
DRVH
VBST
DRVL
PGND
18
CS_GND
17
CS
16
RT8207A
PU11
MODE
V5IN
+1.5VSUS
PR99
7.15K/F_4
15
PR84
*4.7_6
V5FILT
14
NC
S5
13
PR100
5.1/F_6
PC60
1u/6.3V_4
PC45
*680p/50V_6
PC150
560u/2.5V
PC39
10u/10V_8
+3V
HWPG_1.5V <35>
PR225
620K/F_4
PR238
PC61
1u/6.3V_4
PR102
100K/F_4
12
11
S3
VDDQSET
9
FOR DDR III
PGOOD
10
COMP
NC
VDDQSNS
+5V_S5
PC62
0.033u/50V_6
0.15A
PQ51
AOL1718
VTTREF
6/14 Remove JP1 , T23 and T24
+5V_S5
+SMDDR_VREF
OCP:20A
16.84A
PC160
100u/25V_6X5.7
PL11
0.56uH
PC159
2200p/50V_6
VTTSNS
PQ53
AOL1448
1
2
3
VTTGND
VLDOIN
VTT
GND
1
2
3
19
20
21
22
23
24
25
*SHORT_PAD_4
VIN
(For RT8207A
S5_1.8V
PR230
*SHORT_PAD_4
SUSON
<35>
S3_1.8V
PR229
*SHORT_PAD_4
MAINON
<19,35,39,43>
PR228
*0_4
400KHZ ) close to pc2008
+5V_S5
PR101
*SHORT_PAD_6
PC172
*33p/50V_6
PR226
10K/F_4
Vout = (PR150/PR149) X 0.75 + 0.75
S5_1.8V
PR227
10K/F_4
PR224
*0_4
AO1718 Rdson=3.8~4.3mOhm
L(ripple current)
=(19-1.5)*1.5/(0.56u*400k*19)
~6.168A
Vtrip= (20-6.168/2)*4.3mohm=0.072739V
RILIM=Vtrip/10u=7.273K
8207A_SET
S3_1.8V
5
6
7
8
+1.5VSUS
<37,43> MAIND
MAIND
4
PQ59
AO4468
S5
+1.5VSUS
REF
ON
ON
VTT
ON
S3
ON
ON
OFF
S4/S5
OFF
OFF
OFF
3
2
1
S3
S0
+1.5V
2.03A
A

PROJECT : ZQ9
Size
Document Number
Rev
1A
DDR 1.5V(RT8207A)
Date:
5
Sheet

1
40
of
Int_VGA
[PWM]
<6> GFX_VID0
<6> GFX_VID1
+1.05V
+1.05V
<6> GFX_VID2
OCP:25A
Ri=2.49K
Change Ri can adjust OCP point
LL=7.03mv/A
Rdroop=8.87K
Change Rdroop can adjust loadline
<6> GFX_VID3
1
PR78
*IV@0_4
<6> GFX_VID4
PR76
*IV@0_4
PR70
*IV@0_4
PR69
*IV@0_4
PR67
*IV@0_4
PR65
*IV@0_4
PR64
*IV@0_4
<6> GFX_VID5
<6> GFX_VID6
PC149
2
1
62881_GND
PR215
<6>
GFX_VID6
GFX_VID5
GFX_VID4
GFX_VID3
GFX_VID2
GFX_VID1
GFX_VID0
IV@100K_4
PR217
GFX_ON
*IV@SHORT_PAD_4
PR81
<6> GFX_DPRSLPVR
6/14 Remove JP10,T80,T81
*IV@SHORT_PAD_4
VIN
IV@47K/F_4
PR87
62881RBIAS
62881VW
RBIAS
VID0
VW
VCCP
21
1
2
OCP:25A
22A
20
+VGFX_AXG
PQ50
IV@AOL1448
19
16 62881PHASE
PQ49
IV@AOL1718
15 62881UGATE
PQ10
IV@AOL1718
PR62
*[email protected]/F_4
+
BOOT
PR213
4
PR63
IV@1_6
14
IMON
13
12
VIN
VDD
ISUM+
62881VIN
PC155
11
62881RTN
62881VDD
PC157
IV@330p/50V_4
10
PC156
IV@330p/50V_4
IV@150P/50V_4
5/26 modify power budget
62881ISUM+
RTN
Rdroop
ISUM-
VSEN
UGATE
62881ISUM-
PR88
62881VSEN
2
4
VSSP
FB
1
3
PL10
[email protected]
17
IV@ISL62881HRTZ-T
62881BOOT
PC38
PR66
PR77
*IV@10K/F_4
GFX_IMON <6>
IV@11K/F_4
PC44
PC40
VSS_AXG_SENSE <6>
62881_GND
PR214
PC151
VIN
PC147
*IV@SHORT_PAD_4
PC148
62881_GND
PC36
IV@10u/6.3V_8
Close to Phase
Inductor
PR68
IV@1000P/50V_4
PC143
IV@560u/2.5V
PC35
62881_GND
PC142
IV@560u/2.5V
PR211
IV@10K_6_NTC
GFX_IMON
4
1
2
3
LGATE
PU3
COMP
PHASE
PC52
18 62881LGATE
62881COMP 5
62881FB
PC141
+5V_S5
IV@1000P/50V_4
PC51
IV@100P/50V_4
[email protected]/6.3V_6
PC50
IV@22p/50V_4
PR93
PC140
PC37
1
2
GFX_VID2
GFX_VID3
VID2
VID3
VID4
VID5
VID6
VR_ON
VID1
PC53
PR92
IV@820K/F_4
5
PGOOD
1
2
3
PR219
PC138
22
GFX_VID4
23
GFX_VID5
24
62881VR_ON
GFX_VID6
25
28
29
GND
CLK_EN#
GFX_VID0
1
2
3
62881_GND
PR218
*IV@150K/F_4
62881_GND
PC139

GFX_VID1
62881PGOOD
DPRSLPVR
*IV@SHORT_PAD_4
GND
1
PR90
<35> HWPG_GFX
GND
PR89
*IV@100K_4
2
31
30
+3V
26
62881_GND
27
*IV@SHORT_PAD_6
62881DPRSLPVR
62881_GND
PR221
62881_GND
+5V_S5
Ri
PC154
*IV@180P/50V_4
PR216
PR212
IV@10_6
PC152
IV@1u/6.3V_4
PR220
*IV@100/F_4
62881_GND
2
PR72
PC43
Close to Pin9 and Pin10
Parallel
PR82
IV@10/F_4
PR80
*IV@SHORT_PAD_4
VSS_AXG_SENSE <6>
4
PR85
IV@10/F_4
PR83
*IV@SHORT_PAD_4
VCC_AXG_SENSE <6>

PROJECT : ZQ9
Size
1.Level 1 Environment-related Substances Should NEVER be Used.
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners.
A
Document Number
Rev
1A
+VGFX_AXG (ISL62881)
Date:
Sheet
41
H
of

+5V_S5
PR18
*EV@0_4
EV@1u/10V_6
PC98
EV@1u/10V_6
2
8792VCC
13
5/12 change
14
<44> PG_1V_EN
8792EN
<11,19> dGPU_VRON
VDD
TON
8792TON
DH
8792DH
BST
8792BST
EN
PU7
8792LX
DL
8792DL
FB
EV@MAX8792ETD+T LX
PR171
*EV@0_4
8792SKIP# 12
PC100
PR16
PR170
*EV@0_4SHORT_PAD_4
PR172
EV@100K_4
SKIP#
*EV@0_4
8792REFIN 10
REFIN
PC96
PL6
EV@1uH
PR17
REF-2V
8792REF
REF
ILIM
8792ILIM
PQ36
EV@AOL1718
EP
11
R1
PR168
15
PR174
PR240
5/24 change to 73.2K
PR162
EV@332K/F_4
PC19
*EV@1000p/50V_4
*SHORT_PAD_4
PR165
PC18
EV@330u/2V_7343
PC20
*EV@4700P/25V_4
*EV@SHORT_PAD_6
R3
PC93
PC181 EV@2200p/50V_4
100u/25V_6X5.7
1
2
3
<19,21,35> +3V_D_S
PR166
EV@1_6
PGOOD
PQ35
EV@AOL1448
VCC
1
2
3
PC99
PC95
A
PR169
EV@10K_4
PC94
OCP=15A
12A
+VGPU_CORE
+
PR164
EV@200K/F_4
+3V_D_S
6/9 preserved
VIN
PC90
PC92
EV@330u/2V_7343
Place near GND pin15
PC97
EV@1000P/50V_4
PR173
EV@100K_4
Frequency(PR220=200K)
PQ34
EV@DMN601K-7
300K
VIN
PR161
EV@3K_4
R2
AMD Park VID Table

R4
PR163
EV@130K/F_4
PR13
EV@1M_6
1.12V
1.05V
0.95V
0.9V
2
8792EN
2
PQ2
EV@DMN601K-7
PR14
EV@1M_6
PQ1
EV@DTC144EU
PQ33
EV@DMN601K-7
PR160
EV@3K_4
PR15
EV@22_8
+VGPU_CORE
<17> VID2
GPU_VID2 (GPIO20)
GPU_VID1 (GPIO15)
PC91
C
+VGPU_CORE
PR167
<17> VID1
PC89

PROJECT : ZQ9
Size
Document Number
Rev
1A
GPU CORE(MAX8792)
Date:
1
Sheet
5
42
of
2.17A
+1.8V
+3VPCU
6/14 Remove JP5
PC105
0.1u/25V_4
PC104
10u/10V_8
PU8
VIN
PH
10
VIN
PH
11
VIN
PH
PR176
*SHORT_PAD_4
2
15
<19,35,39,40> MAINON
54418-1_VFB
PR177
100K/F_4
EN
PC102
1000p/50V_4
7
8
9
PWRGD
COMP
GND
RT/CLK
GND
SS
PR182
182K/F_4
PC110
*100P/50V_4
BOOT
VSNS
AGND
PL7
1uH_7X7X3

D
12
PR175
*SHORT_PAD_6
13
PC101
0.1u/50V_6
14
5/12 change
R1
4
HWPG_1.8V <35>
PR180
100K/F_4
PR178
100K/F_4
+3V_S5
22
21
20
19
18
17
PR181
15K/F_4
HPA00835RTER
16
PAD
PAD
PAD
PAD
PAD
PAD
6/9 change the P/N
PC107
10u/10V_8
PC106
0.01u/25V_4
PC109
10u/10V_8
PC108
10u/10V_8
54418-1_VFB
6/9 change the P/N
V0=0.8*(R1+R2)/R2
PC111
1200p/50V_4
R2
+1.5V_GPU
PR23
EV@1M_4
+1.5VSUS
+15V
PR24
*EV@22_8
PR25
EV@1M_4
5
6
7
8
VIN
PQ38
EV@AO4468
dGPU_D
3
PR179
78.7K/F_4
3.94A
PR26
EV@1M_4 2
+1.5V_GPU
PC21
PQ8
EV@DMN601K-7
3
2
1
<44> PG_1.5V_EN
PQ7
*EV@DMN601K-7
1
PQ6
EV@DTC144EUA
PR29
*EV@100K_4
+1.8V_GPU
PR20
EV@1M_4
+1.5V_GPU
+1.8V
+15V
PR19
EV@22_8
PR21
EV@1M_4
VIN
dGPU_D1
PR28
EV@1M_4 2
PQ37
EV@AO3404
PC103
PQ4
EV@DMN601K-7
PQ5
EV@DMN601K-7
1
PQ3
EV@PDTC143TT
1.41A
+1.8V_GPU
PR27
EV@100K_4
PR22
EV@1K_4
VIN
+3V
PR128
1M_4
+0.75V_DDR_VTT
+5V
PR118
22_8
PR119
22_8
+1.5V
PR121
22_8
+1.8V
PR120
22_8
+15V
PR122
*22_8
PR123
1M_4
<37,40>
MAIND
MAIND
3
MAINON_ON_G
PQ23
DMN601K-7
PQ22
DMN601K-7
PQ24
*DMN601K-7
PQ25
DMN601K-7
PC68
*2200p/50V_4
PR127
*100K/F_6
2
PQ21
DMN601K-7
2
PQ20
DMN601K-7
PR136
1M_4
PQ26
DTC144EU
<19,35,39,40> MAINON
7/7 modify

PROJECT : ZQ9
Size
Document Number
Rev
1A
Discharge/1.8V)
Date:
5
Sheet

1
43
of
+3V_S5
+5VPCU
PR186
10K_4
PU9
RT9018A
+1.5VSUS
VPP PGOOD
VEN
VO
3
8
9
VIN
GND
GND
NC
1.5A
PR183
9.1K/F_4
PR185
100K_4
PG_1.5V_EN <43>
+1V
<42> PG_1V_EN
ADJ
PC113
0.1u/50V_6
PC112
22u/10V_1206
0.8V
PC115
10u/10V_8
PC114
PC116
0.1u/50V_6 0.1u/50V_6
PR184
34K/F_4
6/9 change the P/N
Vout =0.8(1+R1/R2)
=1V
C
VIN
PU10B
LM393
PD8
SW1010CPT
For EC control thermal protection (output 3.3V)

1
PR205
1M_6
Thermal protection
PQ45
AO3409
S5_ON 2
<35,37> S5_ON
PR201
0_6
PQ44
DTC144EU
VL
VL
SYS_SHDN# <4,37>
Need fine tune

for thermal protect point
PR194
200K_6
2
PQ39
DMN601K-7
PU10A
LM393
PC119
0.1u/50V_6
2
PQ40
DMN601K-7
PR192
200K/F_4
S5_ON
2.469V
Note placement position
PC125
0.1u/50V_6
PR187
10K_6_NTC
PR189
200K/F_4
8
PR188
1.74K/F_4
PROJECT : ZQ9
Size
Document Number
Date:
Rev
1A
Sheet
1
44
of
MODEL
Model
REV
ZQ9
1A
CHANGE LIST
5/20 delet TP for modify Q23
T7000 TP7010 TP7011 TP7012
TP7013 TP7025 TP7022 TP7017
TP39
TP7020 TP7023 T3502
T3500 T3501
T3506
T3510
T3511 T3517
T3519
T3513
T3516 T3505
ZQ9
FRO M
TP44
TP7028
T3503
T3518
T3515
1A
1A
5/21 swap RP7000 by following layout house's ask

add HOLE18 HOLE19 HOLE20 HOLE21 HOLE22
change the LVDS connector and swap pin define
delete PC4026
1A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
5/24 delete R30019

change PR3011 to 73.2K
stuff R3624 & R3527 and unstuff other components for changing +3V_D and +3V_D_S to +3V
swap RN5 & RN10 pin defines
change footprints of HOLE2, HOLE3, HOLE5, HOLE21 and add HOLE23
change Q45 & Q46 left side pull-high voltage to +3V
5/25 reserve C1, C2, C3, C4, C507, C508, C509, C503, C511, C515, C516, C519, C520 for EMI
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
5/26 update JDIM7001 & CN14 footprint

add PQ4000 change P/N of PL4000, PR4005, PC4022, PR4026, PR4006, PC4020, PR4024, PR4007, PC4018
1A
B 2A
1A
B 2A
1A
B 2A
5/27 Delete HOLE4, HOLE22
1A
B 2A
1A
B 2A
1A
B 2A
1A
2A
B 2A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
6/14 change Q16, PC124, PC137, PC160, PC168, PC173 C572 P/N for EOD parts
6/18 unstuff U27, C423, R287 and stuff R284 for using internal ROM for LAN
change the AMP P/N and footprint
add CN19, C715, C717, Q25, R574, R573 reserve L57, C716 for adding another BT
stuff Q13, Q14, R236, R237 & unstuff R215, R216
change U11 P/N delete C489, R565, R330
reserve R575 & R576
stuff R563, R564, R571, C15, C426, C506, C479 & add C718, C719, C720 for EMI's request
B 2A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
6/18 Change to Shortpad 0603

PR231,PR104,PR222,PR223,PR101,PR221,PR165,PR175
Change to Shortpad 0402
PR149,PR4,PR154,PR124,PR115,PR114,PR232,PR133,PR108,PR110,PR112
PR117,PR30,PR59,PR31,PR37,PR53,PR42,PR41,PR91,PR230,PR229,PR217,PR81,PR90,PR214,PR80,PR83,PR170,PR176
Change to Shortpad 0805
PR203
6/18 Change PQ30 to AO4468 PN:BAM44680003
6/19 modify R90, R386, R107, R390, R109, R149, R163, R194, R233, R531, R234, R271, R556, R306, R292, R332,
R554, R562, R524 to 0402 shortpad
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
6/19 modify R142, R172,
to 0603 shortpad
R186, R168, R417, R178, R201, R113, R185, R169, R213, R174, R275, R268, R299, R557, R572, R570
6/19 modify R162, R140,
R210, R116, R124, R303, R8, R14 to 0805 shortpad
B 2A
1A
B 2A
1A
B 2A
C 3A
B 2A
C 3A
B 2A
6/19 modify R526 to 1206 shortpad
B 2A
C 3A
B 2A
C 3A
B 2A
6/20 change C474 P/N, delete R565, R330, C489 for AMP change , change U11 P/N
change U17 P/N
C 3A
B 2A
6/21 stuff R565, unstuff L50 for 3V CLK gen and change CLK gen 100MHz signals order
add PR235, PR236, PR237, PR238, PR240 shortpads
change R458, R457 back to 0 ohm
unstuff SW1
modify R443, R550 to Shortpad 0805
add PAD1, PAD2, PAD3
change U11, U20 P/N
change R315, R319 P/N
reserve C489 for EMI's request
stuff PC180, PC181
stuff C285, C284
stuff PC22, PC30 unstuff PC123, PC128
B 2A
1A
1A
1A
6/14 Remove Page37 JP2,JP15,JP16,JP14

Page38 JP7,JP8
Page39 JP13,JP11
Page40 JP12,JP1
Page41 JP10,JP9
Page42 JP3,JP4
Page43 JP5,JP6
Power parts
B 2A
1A
1A
1A
6/9 stuff PC128, unstuff PC22

change the footprints C187, C178, C74, R144 to Std.
stuff R80, R79, R53 & R77, R78, R51 for Park
stuff R132, R407, R414 for board ID
stuff R293, R288, R285, R281, R280 for debug
change PR145 P/N to 3720
preserved PC179, PC180, PC181
unstuff PD9, PD10 for cost down
change PC104, PC107, PC109 P/N
change PR184 P/N
6/11 change the P/N of Q12, Q20, Q21
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
C 3A
B 2A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
To
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
C
4A

Document Number
PROJECT MODEL :
DOC NO.
PROJECT : ZQ9
Size
Date:
Rev
1A
Change list2
Sheet
45
of
ZR7B
PART NUMBER:
45
APPROVED BY:
DATE:
DRAWING BY:
REVISON:
2009/12/24
C3A

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5

ZQ9 SYSTEM BLOCK DIAGRAM

P8, 9, 10, 11, 12, 13

for Discrete Graphic only SKU

GMT 1453L amp

for different VRAM parts

Quanta Computer Inc.

Tuesday, June 22, 2010

BOM Option Table

GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

+1V (DP PLL PWR)

G9334ADJ & MOS

GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

+1V (DP PLL PWR)

G9334ADJ & MOS

Thermal Follow Chart

CHARGE PUMP POWER

PCH/GPU/Peripheral component POWER

CPU/SODIMM CORE POWER

SODIMM Termination POWER

Internal GPU POWER

MINI CARD/NEW CARD POWER

CPU VTT POWER

PCH CORE POWER

CPU CORE POWER

SWITCHABLE PWM IC POWER

GPU CORE POWER

GPU I/O POWER

VRAM CORE POWER

Quanta Computer Inc.

PWR Status & GPU PWR CRL & THRM

Tuesday, June 22, 2010

6/21 add for 3V CLK gen

Place each 0.1uF cap as close as

5/13 add for cost down solution

6/21 change the order

Quanta Computer Inc.

Tuesday, June 22, 2010

AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI)

AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

Processor Compensation Signals

Use reverse type

1.5K/F_4 CPU_PLTRST# AL14

JTAG & BPM

PCI EXPRESS -- GRAPHICS

Layout Note: Place

5/13 follow ZR7B setting

6/14 change the P/N

STUFF -> R469, R491, R507

STUFF -> R490, R491

STUFF -> R489, R507

Use a voltage divider with VDDQ

Quanta Computer Inc.

Tuesday, June 22, 2010

AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3)

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY - B

Channel A DQ[15,32,48,54], DM[5]

Quanta Computer Inc.