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3 Bit ALU Using Schematic Capture

The document outlines objectives to design various digital logic components including: 1) 1-bit and 4-bit full adders using Verilog descriptions. 2) 1-bit comparators using schematic capture and Verilog descriptions. 3) 1-bit and 3-bit arithmetic logic units (ALUs) using schematic capture. It then provides Verilog code for the 1-bit and 4-bit full adders, schematic diagrams for the 1-bit comparator and half adder/subtractor blocks of the ALU, and block diagrams depicting the 4-to-1 multiplexer and overall ALU design.

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72 views21 pages

3 Bit ALU Using Schematic Capture

The document outlines objectives to design various digital logic components including: 1) 1-bit and 4-bit full adders using Verilog descriptions. 2) 1-bit comparators using schematic capture and Verilog descriptions. 3) 1-bit and 3-bit arithmetic logic units (ALUs) using schematic capture. It then provides Verilog code for the 1-bit and 4-bit full adders, schematic diagrams for the 1-bit comparator and half adder/subtractor blocks of the ALU, and block diagrams depicting the 4-to-1 multiplexer and overall ALU design.

Uploaded by

newaznahian
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Objective to desing :

-1 bit full adder using verilog description


-4 bit full adder using verilog description -1 bit comparator using schematic capture -1 bit comparator using verilog description -1 bit ALU using schematic capture

- 3 bit ALU using schematic capture

1 bit adder

1 bit adder: module adder(a,b,c,f,carry); input a,b,c; output f,carry; wire w1,w2,w3; xor xor1(w1,a,b); xor xor2(f,w1,c); and and1(w2,w1,c); and and2(w3,a,b); or or1(carry,w2,w3); endmodule

4 bit full adder:


module fadd1(a1,a2,a3,a4,b1,b2,b3,b4,cin,carry,f1,f2,f3,f4); input a1,a2,a3,a4,b1,b2,b3,b4,cin; output carry,f1,f2,f3,f4; wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15; xor xor1(w1,a1,b1); xor xor2(f1,w1,cin); and and1(w2,w1,cin); and and2(w3,a1,b1); or or1(w13,w2,w3); xor xor3(w4,a2,b2); xor xor4(f2,w4,w13); and and3(w5,w13,w4); and and4(w6,a2,b2); or or2(w14,w5,w6);

xor xor5(w7,a3,b3); xor xor6(f3,w14,w7); and and5(w8,w7,w14); and and6(w9,a3,b3); or or3(w15,w9,w8);

xor xor7(w10,a4,b4); xor xor8(f4,w10,w15); and and7(w11,w10,w15); and and8(w12,a4,b4); or or4(carry,w12,w11);


endmodule

4 bit full adder using function: module adder(a,b,c,f,carry); input a,b,c; output f,carry;

wire w1,w2,w3;
xor xor1(w1,a,b); xor xor2(f,w1,c); and and1(w2,w1,c); and and2(w3,a,b); or or1(carry,w2,w3);

endmodule

module add(a0,a1,a2,a3,b0,b1,b2,b3,c0,f0,f1,f2,f3,f_carry); input a0,a1,a2,a3,b0,b1,b2,b3,c0; output f0,f1,f2,f3,f_carry;

wire w1,w2,w3;
adder adder1(a0,b0,c0,f0,w1); adder adder2(a1,b1,w1,f1,w2); adder adder3(a2,b2,w2,f2,w3); adder adder4(a3,b3,w3,f3,f_carry); endmodule

1 bit comparator a 0 0 1 1 b 0 1 0 1 O1(a>b) O2(a<b) O3(a=b) 0 0 1 0 0 1 0 0 1 0 0 1

O1 = ab

O2 = ab

O3 = ab+ab

CIRCUIT DIAGRAM

1 bit comparator:
module comp(a,b,o1,o2,o3);

input a,b; output o1,o2,o3;


wire w1,w2; inv inv1(w1,a); inv inv2(w2,b);

and and1(o1,a,w2); and and2(o2,w1,b); xnor xnor1(o3,a,b); endmodule

1 bit ALU design

S0 0

S1 0

O/P add

0
1 1

1
0 1

subtract
and or

Steps: 1. design 4 to 1 mux using 3 2 to 1 mux 2. design half adder & make the block 3. design half subtractor & make the block 4. design the ALU

design 4 to 1 mux using three 2 to 1 mux

BLOCK DIAGRAM

half adder a 0 0 1 1 b 0 1 0 1 sum 0 1 1 0 carry 0 0

0
1

Sum = ab+ab carry = ab

CIRCUIT DIAGRAM

BLOCK DIAGRAM

half subtractor
a 0 0 1 1 b 0 1 0 1 diff 0 1 1 0 borrow

0
1

0
0

diff = ab+ab
borrow = ab

CIRCUIT DIAGRAM

BLOCK DIAGRAM

ALU DESIGN

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