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Lecture11 Speed Power

This document appears to be a set of lecture slides for EE241 Advanced Digital Integrated Circuits at UC Berkeley. The slides cover various topics related to logic styles for high speed or low power circuits including: sample-set differential logic, differential current switch logic, sense-amplifying logic, current-mode logic, adaptive pipelining, principles of power reduction through lowering switching activity, supply voltage, frequency and load capacitance. It also discusses tradeoffs between power, delay and energy efficiency under supply voltage scaling.

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Naveen Chaubey
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71 views

Lecture11 Speed Power

This document appears to be a set of lecture slides for EE241 Advanced Digital Integrated Circuits at UC Berkeley. The slides cover various topics related to logic styles for high speed or low power circuits including: sample-set differential logic, differential current switch logic, sense-amplifying logic, current-mode logic, adaptive pipelining, principles of power reduction through lowering switching activity, supply voltage, frequency and load capacitance. It also discusses tradeoffs between power, delay and energy efficiency under supply voltage scaling.

Uploaded by

Naveen Chaubey
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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EE241

Advanced Digital Integrated Circuits


Lecture 11 Logic Styles for High Speed or Low Power

EE241 - Spring 2000

UC Berkeley EE241

B. Nikoli c

Announcements
Homework #1 due today by 5pm l Homework #2 due Th, 3/2 by 5pm l Midterm project reports due in two weeks 3/7 by 5pm
l

UC Berkeley EE241

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EE241

Sample-Set Differential Logic

Differential Domino (DCVSL)


Grotjohn JSSC 4/86
UC Berkeley EE241

SSDL
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Differential Current Switch Logic

Somasekhar, JSSC 7/96


UC Berkeley EE241 B. Nikoli c

EE241

Dynamic DCVS-PG

UC Berkeley EE241

Lai, JSSC 4/97

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Sense-Amplifying Logic

Matsui, JSSC 12/94

UC Berkeley EE241

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EE241

SA-F/F

Falling edge

Rising edge

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Dynamic Logic with SA-F/F

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Example

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4-Bit Adder

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20-Bit Carry-Skip Adder

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GHz Logic with Sense Amplifiers

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Takahashi, JSSC 5/99

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Read-out scheme

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Implemented Macros

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Rotator (ROT)

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Incrementer (INC)

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Current-Mode Logic (CML)

UC Berkeley EE241

M. Mizuno, JSSC 6/96

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Current-Mode Logic (CML)

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EE241

CMOS CML

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Current-Mode Logic (CML)

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Adaptive Pipeline

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Adaptive Pipeline

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EE241

Low Power Low Energy Circuit Design


Architectures, Circuits and Technology

UC Berkeley EE241

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Literature
A. Chandrakasan and R. Brodersen, Low Power CMOS Design, Kluwer Academic Publishers, 1995 J. Rabaey and M. Pedram, Ed., Low Power Design Methodologies, Kluwer Academic Publishers, 1995 Proceedings of the IEEE, Special Issue on Low Power, April 1995. A. Chandrakasan and R. Brodersen, Low-Power CMOS Design, IEEE Press, 1998 (Reprint Volume)

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EE241

Principles of Power Reduction


P ~ CL Vswing + I SC t SC VDD f + (I DC + I Leak )VDD
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- switching probability CL load capacitance Vswing voltage swing f - frequency

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Isc mean value of switching transient current tsc short current time IDC static current Ileak leakage current

Dominant:

P ~ CL Vswing VDD f
Kuroda, Sakurai, IEICE 4/95
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UC Berkeley EE241

Principles of Power Reduction


P ~ CL Vswing VDD f
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E ~ CL Vswing VDD

Reducing switching probability () Architectures Power simulators/estimators (time consuming) Glitching power reduction (15-20%) Reducing load capacitance Technology scaling Gate sizing, minimization, interconnect, CAD Circuit techniques (PTL, ) Reducing supply voltage Quadratic impact on power Impact on delay how to maintain throughput? Reducing frequency
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Supply Voltage Scaling


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How to maintain throughput under reduced supply? Introducing more parallelism/pipelining


Area increase cost up Cost/power tradeoff

Multiple voltage domains


Separate supply voltages for different blocks Lower VDD for slower blocks Cost of DC-DC converters

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Dynamic voltage scaling with variable throughput Reducing VTH to improve speed
Leakage issues

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Power and Delay

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EE241

Power-Delay vs Energy-Delay Product

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Energy-Efficiency Metric: Max Throughput


Process Queue

from [Burd95] (HICSS 95)

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Delay and Power under Voltage Scaling

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Lowering Only Internal VDD

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