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LOAD A, 2:3 LOAD B, 5:2 Prod A, B STORE 2:3, A

The document discusses the differences between CISC and RISC processor architectures. CISC processors use complex instructions that can perform multiple operations like loading, computing, and storing in one clock cycle. RISC processors break these down into simpler instructions that each take one clock cycle to execute, allowing for pipelining. This requires more instructions but enables higher clock speeds and more efficient hardware design.

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Dinesh Kumar
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31 views2 pages

LOAD A, 2:3 LOAD B, 5:2 Prod A, B STORE 2:3, A

The document discusses the differences between CISC and RISC processor architectures. CISC processors use complex instructions that can perform multiple operations like loading, computing, and storing in one clock cycle. RISC processors break these down into simpler instructions that each take one clock cycle to execute, allowing for pipelining. This requires more instructions but enables higher clock speeds and more efficient hardware design.

Uploaded by

Dinesh Kumar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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When executed, this instruction loads the two values into separate registers, multiplies the operands in the

execution unit, and then stores the product in the appropriate register. a. Thus, the entire task of multiplying two numbers can be completed with one instruction: MUL 2:3, 5:2 b. MUL is what is known as a "complex instruction." c. It operates directly on the computer's memory banks and does not require the programmer to explicitly call any loading or storing functions. d. It closely resembles a command in a higher level language. Advantage: -Translation -Complexity in hardware. The RISC Approach: RISC processors only use simple instructions that can be executed within one clock cycle. Thus, the "MUL" command described above could be divided into three separate commands: LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A

Analysis. At first, this may seem like a much less efficient way of completing the operation. Because there are more lines of code, more RAM is needed to store the assembly level instructions. The compiler must also perform more work to convert a high-level language statement into code of this form. Advantage: -Since all instructions executed in 1 clock cycle, pipelining is possible. -Register Memory? CISC Emphasis on hardware Includes multi-clock complex instructions Memory-to-memory: "LOAD" and "STORE" incorporated in instructions Small code sizes, high cycles per second Transistors used for storing complex instructions RISC Emphasis on software Single-clock, reduced instruction only Register to register: "LOAD" and "STORE" are independent instructions Low cycles per second, large code sizes Spends more transistors on memory registers

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