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Test 2

The document contains questions about different Verilog modeling styles including: 1) Questions about differentiating tasks and functions with examples. 2) Designing a 4-bit binary counter and clock signal using behavioral modeling. 3) Writing Verilog code for a level sensitive latch and ripple carry adder using data flow modeling. 4) Writing Verilog code for a D flip-flop and other circuits like adders, muxes, encoders, and decoders using gate level modeling and specifying delays.

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Ali Raza Khan
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20 views4 pages

Test 2

The document contains questions about different Verilog modeling styles including: 1) Questions about differentiating tasks and functions with examples. 2) Designing a 4-bit binary counter and clock signal using behavioral modeling. 3) Writing Verilog code for a level sensitive latch and ripple carry adder using data flow modeling. 4) Writing Verilog code for a D flip-flop and other circuits like adders, muxes, encoders, and decoders using gate level modeling and specifying delays.

Uploaded by

Ali Raza Khan
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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TEST 2 Task and function Q1.how we can differentiate task and function using examples and diagrams. Q2.

write the function for parity calculation and show its invocation. Q3. efine a function to calculate the factorial of a !"#it num#er. The output is a 32 #it value .$nvoke the function #y using stimulus and check result. Q! efine a task to compute the even parity of a 1%"#it num#er. The result is a 1 #it value .that is assigned to the output after three positive edges of clock. &hint' use a repeat loop in the task(. Q). efine a task to compute the factorial of a !"#it num#er. The output is a 32 #it value .the result is assigned to the output after a delay of 1* time units. Behavioral model Q1.

Q2.design a four #it #inary counter uses #ehavioral modeling. Q3.declare a register called oscillate. $nitiali+e it to * and make it toggle every 3* time units. o not use always statement &,int ' use the forever loop( Q!.design a clock with time period -!* and a duty cycle of 2). #y using the always and initial statements. The value of clock at time -* should #e initiali+ed to *. Q)./ompare the #locking and non #locking statements with examples.

Q%.

Q0.

Q1. 2ive the significance of case x and case + with suita#le examples. Q3. 4rite a 5erilog code of level sensitive latch with asynchronous reset. $n which you have to use the event 67 control and timing delay of 8num#er9 identifier and expression:. Q1*.differentaite timing control delay and event #ased delays with examples. Q11.2ive the significance of +ero delay with examples. Q12.differentaite #etween initial and always #lock with examples. Data flow model: Q1. 5erilog code for ripple carry adder using data flow model. Q2.!"#it full adder with carry looks ahead adder using data flow model.

Q3. !' 1 and 1'1 mux using data flow model. Q!. ;ll operators name and function. Eg' <- 1**11*1* =ine all reduction operators of the a#ove data. "1*>)-? 4hich operator is used in this statement? Q).define delays' a: @et declaration #: $mplicit continuous assignment delay c: 7egular assignment delay Gate model Q1.

Q2.write 5erilog code for 9T flipflop using dealys 83'2'!92'!')91'2'3: using gate model 9also apply stimulus for the a#ove flipflops. Q3. 4rite 5erilog code for adder 9su#tractors9 mux9 demus9 encoder9 decoder etc using delays 83'2'!92'!')91'2'3: using gate model 9also apply stimulus for the a#ove circuits..

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