Quiz: Advanced Microcontroller Bus Architecture (AMBA) 1.

Please specify the interface (I/O) of the AMBA AHB Master, Split-capable Slave, and Arbiter.

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Quiz: Advanced Microcontroller Bus Architecture (AMBA) 2. Why is a burst not allowed to cross a 1 Kbyte boundary?
If an AHB slave samples HSELx at the start of a burst transaction, it knows it will be selected for the duration of the burst. Also, a slave which is not selected at the start of a burst will know that it will not become selected until a new burst is started. 1 kilobyte is the smallest area an AHB slave may occupy in the memory map. Therefore, if a burst did cross a 1 kilobyte boundary, the access could start accessing one slave at the beginning of the burst and then switch to another on the boundary, which must not happen for the above reason. The 1 kilobyte boundary has been chosen as it is large enough to allow reasonable length bursts, but small enough that peripherals can be aligned to the 1 kilobyte boundary without using up too much of the available memory map.

3. Please describe the two-cycle response and draw a simple timing diagram.
Only an OKAY response can be given in a single cycle. The ERROR, SPLIT and RETRY responses require at least two cycles. To complete with any of these responses then in the penultimate (one before last) cycle the slave drives HRESP[1:0] to indicate ERROR, RETRY or SPLIT while driving HREADY LOW to extend the transfer for an extra cycle. In the final cycle HREADY is driven HIGH to end the transfer, while HRESP[1:0] remains driven to indicate ERROR, RETRY or SPLIT. If the slave needs more than two cycles to provide the ERROR, SPLIT or RETRY response then additional wait states may be inserted at the start of the transfer. During this time the HREADY signal will be LOW and the response must be set to OKAY. The two-cycle response is required because of the pipelined nature of the bus. By the time a slave starts to issue either an ERROR, SPLIT or RETRY response then the address for the following transfer has already been broadcast onto the bus. The two cycle response allows sufficient time for the master to cancel this address and drive HTRANS[1:0] to IDLE before the start of the next transfer.

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Quiz: Advanced Microcontroller Bus Architecture (AMBA) 4. Slaves on the bus require HREADY as both an input and an output signal, why?
An AHB slave must have the HREADY signal as both an input and an output. HREADY is required as an output from a slave so that the slave can extend the data phase of a transfer. HREADY is also required as an input so that the slave can determine when the previously selected slave has completed its final transfer and the first data phase transfer for this slave is about to commence. Each AHB Slave should have an HREADY output signal (conventionally named HREADYOUT) which is connected to the Slave-to-Master Multiplexer. The output of this multiplexer is the global HREADY signal which is routed to all masters on the AHB and is also fed back to all slaves as the HREADY input. A slave must have the HREADY signal as both an input and an output. The output version of the HREADY signal is used by the slave to extended transfers and is fed via the bus multiplexer to the bus master which is performing the transfer. HREADY is also required as an input to slaves and this signal comes from the output of the bus multiplexer. When the slave is responsible for driving HREADY (when it is being accessed) then this signal will be the same as the HREADY output from the slave. However, when another slave is being accessed, the HREADY signal will indicate if that slave is inserting wait states and this is important when a master changes from one slave to another. It is suggested that the input version of this signal is called HREADY and the output is HREADYOUT.

5. On the APB, what is the different between PSELx and PENABLE signals?
PSELx (APB select) A signal from the secondary decoder, within the peripheral bus bridge unit, to each peripheral bus slave x. This signal indicates that the slave device is selected and a data transfer is required. There is a PSELx signal for each bus slave.

PENABLE (APB strobe) This strobe signal is used to time all accesses on the peripheral bus. The enable signal is used to indicate the second cycle of an APB transfer. The rising edge of PENABLE occurs in the middle of the APB transfer.

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Quiz: Advanced Microcontroller Bus Architecture (AMBA) 6. When can the HGRANT signal change?
The HGRANT signal can change in any cycle and the following cases are possible: It is possible that the HGRANT signal may be asserted and then removed before the current transfer completes. This is acceptable because the HGRANT signal is only sampled by masters when HREADY is high. A master can be granted the bus without requesting it. The above point also means that it is possible to be granted the bus in the same cycle that it is requested. This can occur if the master is coincidentally granted the bus in the same cycle that it requests it.

7. When can Early Burst Termination occur?

Bursts can be early terminated either as a result of the Arbiter removing the HGRANT to a master part way through a burst, or after a slave returns a non-OKAY response to any beat of a burst. Note however that a master cannot decide to terminate a defined length burst unless prompted to do so by the Arbiter or Slave responses. All AHB Masters, Slaves and Arbiters must be designed to support Early Burst Termination.

8. Can a master change the address/control signals during a waited transfer?

Yes. If the address/control signals are indicating an IDLE transfer then the master can change to a real transfer (NONSEQ) when HREADY is low. However, if a master is indicating a real transfer (NONSEQ or SEQ) then it cannot cancel this during a waited transfer unless it receives a SPLIT, RETRY or ERROR response.

9. How does the AHB handle LOCKed SPLITs?

When a transfer is SPLIT the arbiter degrants and removes the SPLIT master out of the arbitration until the slave indicates that the transfer can complete. When an access is LOCKed the access cannot be interrupted by an access from another master. The only possible way that an AHB system can handle these two requirements simultaneously is to grant a "dummy master" when the LOCKed access is SPLIT. The dummy master will only perform IDLE transactions, which are allowable during a locked transfer. To grant any other master would violate the LOCK protocol, for the arbiter to ignore the SPLIT would violate the SPLIT protocol - the dummy master is the only option. The dummy master is also used when all masters are have received a SPLIT response (the dummy master cannot receive a SPLIT response).

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Quiz: Advanced Microcontroller Bus Architecture (AMBA)

It is recommended that the designer of the split-capable slave(s) makes sure that the slave monitors its HMASTLOCK input so that it doesn't return a SPLIT on a LOCKed transfer, as this serves no purpose.

10. What is the difference between SPLIT and RETRY responses?

Both the Split and Retry responses are used by slaves which require a large number of cycles to complete a transfer. These responses allow a data phase transfer to appear completed to avoid stalling the bus, but at the same time indicate that the transfer should be re-attempted when the master is next granted the bus. The difference between them is that a SPLIT response tells the Arbiter to give priority to all other masters until the SPLIT transfer can be completed (effectively ignoring all further requests from this master until the SPLIT slave indicates it can complete the SPLIT transfer), whereas the RETRY response only tells the Arbiter to give priority to higher priority masters. A SPLIT response is more complicated to implement than a RETRY, but has the advantage that it allows the maximum efficiency to be made of the bus bandwidth. The master behavior is identical to both SPLIT and RETRY responses, the master has to cancel the next access and re-attempt the current failed access.

11. When will the arbiter grant another master after a locked transfer?
The arbiter will always grant the master an extra transfer at the end of a locked sequence, so the master is guaranteed to perform one transfer with the HMASTLOCK signal low at the end of the locked sequence. This coincides with the data phase of the last transfer in the locked sequence. During this time the arbiter can change the HGRANT signals to a new bus master, but if the data phase of the last locked transfer receives either a SPLIT or RETRY response then the arbiter will drive the HGRANT signals to ensure that either the master performing the locked sequence remains granted on the bus for a RETRY response, or the Dummy master is granted the bus for the SPLIT response.

12. What is the difference between a dummy bus master and a default bus master? Is a dummy master really necessary?
The term default bus master is used to describe the master that is granted when none of the masters in the system are requesting access to the bus. Usually the bus master which is most likely to request the bus is made the default master. The dummy bus master is a master which only performs IDLE transfers. It is required in a system so the arbiter can grant a master which is guaranteed not to perform any real transfers. The two cases when the arbiter would need to do this are when a Split response is given to a locked transfer and when a Split response is given and all other masters have already been split.
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Quiz: Advanced Microcontroller Bus Architecture (AMBA)

A dummy master is necessary in any system which has a slave that can give SPLIT transfer responses. The dummy master is required so that something can be granted the bus if all the other masters have received a SPLIT response. No logic is required for the dummy master and it can be implemented by simply tying off the inputs to the master address/control multiplexer for the dummy master position. The requirements for a dummy master are that HTRANS is driven to IDLE, HLOCK is driven low, and all other master outputs are driven to legal values.

13. When should a master de-assert its HBUSREQ signal?

For an undefined length burst (INCR) a master must keep its HBUSREQ signal asserted until it has started the address phase of the last transfer in the burst. This will mean that if the penultimate transfer in the burst is zero wait state then the master may be granted the bus for an additional transfer at the end of an undefined length burst. For a defined length burst the master can deassert the HBUSREQ signal once the master has been granted the bus for the first transfer. This can be done because the arbiter is able to count the transfers in the burst and keep the master granted until the burst completes. However it is not a mandatory requirement for an Arbiter to allow a burst to complete, so the master will have to re-assert HBUSREQ if the Arbiter removes HGRANT before the burst has been completed.

14. When should a master assert and de-assert the HLOCK signal for a locked transfer?
The HLOCK signal must be asserted at least one cycle before the start of the address phase of a locked transfer. This is required so that the arbiter can sample the HLOCK signal as high at the start of the address phase. The master should deassert the HLOCK signal when the address phase of the last transfer in the locked sequence has started.

15. What is the relationship between the HLOCK signal and the HMASTLOCK signal?
At the start of the address phase of every transfer the arbiter will sample the HLOCK signal of the master that is about to start driving the address bus and if HLOCK is asserted at this point then HMASTLOCK will be asserted by the arbiter for the duration of the address phase of the transfer.

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Quiz: Advanced Microcontroller Bus Architecture (AMBA)

16. What sequences of transfers types (HTRANS) can occur on the bus? (Note: We do not ask you the HBURST signal)
The following examples show some of the sequences of HTRANS that can occur on the bus: A normal burst of four transfers followed by an IDLE. N-S-S-S-I A normal burst of four transfers which includes BUSY transfers. N-S-B-S-B-S-I A burst of four transfers followed by another burst. N-S-S-S-N-S-S-S-I A single transfer followed by a burst of four transfers. N-N-S-S-S-I A single transfer followed by an IDLE N-I An undefined length burst which concludes with a BUSY transfer. N-B-S-B-S-B-I An undefined length burst which concludes with a BUSY transfer and is followed immediately by another burst. N-B-S-B-S-B-NS

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Quiz: Advanced Microcontroller Bus Architecture (AMBA) 17. Please fill out the address (HADDR) sequence.

18. Draw the timing diagram of APB back-to-back transfer. That means the transfer sequence starts with a write, which is then followed by a read, then a write, then a read.

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