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Exp 3.a Encoder

This document describes implementing an encoder circuit using three modeling approaches: dataflow modeling, structural modeling, and behavioral modeling. The dataflow and structural modeling sections provide example code for implementing the encoder using or gates. The behavioral modeling section uses a process with an if-else statement to assign the output based on the input values.

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40 views3 pages

Exp 3.a Encoder

This document describes implementing an encoder circuit using three modeling approaches: dataflow modeling, structural modeling, and behavioral modeling. The dataflow and structural modeling sections provide example code for implementing the encoder using or gates. The behavioral modeling section uses a process with an if-else statement to assign the output based on the input values.

Uploaded by

aishu3694
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Exp 3.

a Encoder
AIM:To perform encoder operation using dataflow, structure and behavioral modeling. APPARATUS REQUIRED:Xilinx ISE design suite 13. software. ALGORITHM:1.!all the librar" function ieee. .#eclare the entities$namel" input and output ports. 3.In the architectural bod",depending on the t"pe of modeling preferred,write the coding. In the half adder,the output sum is e%uivalent to a xor b while the output carr" is e%uivalent to a and b. &.End the architectural bod",save the program. '.!hec( for the s"ntax and run the simulation. ).Specif" the constant or cloc( value for the input. *.+un the simulation and verif" the output.

PROGRAM:a, Usin da!a"#o$ %ode#:


librar" IEEE use IEEE.std-logic-11)&..//0 entit" Encoder is port1#2 in std-logic-vector13 downto 3,0 x,"2 out std-logic,0 end Encoder0 architecture dataflow of encoder is begin x45# or #30 "45#1 or #30 end Encoder0

b, Usin s!r&c!&ra# %ode#: librar" IEEE use IEEE.std-logic-11)&..//0 entit" Encoder is port1#2 in std-logic-vector13 downto 3,0 x,"2 out std-logic,0 end Encoder0 architecture structural of Encoder is component or port1a,b 2 in std-logic0 c2out std-logic,0 end component0 begin a1 2 or portmap 1# ,#3,x,0 a 2 or portmap1#1,#3,",0 end structural0 librar" IEEE use IEEE.std-logic-11)&..//0 entit" or is port1 .2 in std-logic0 62 in std-logic0 !2 out std-logic,0 end or 0 architecture dataflow of or is begin c45. or 60 end dataflow0 c, Usin 'e(a)io&ra# %ode#: librar" IEEE use IEEE.std-logic-11)&..//0 entit" Encoder is port1d3,d1,d ,d32 in std-logic0 "2 out std-logic-vector11 downto 3,,0 end Encoder0 architecture behavioral of encoder is begin process 1d3,d1,d ,d3, begin if d3 5 718 then

"45 933:0 elseif d15818 then "45:31:0 elseif d 5818 then "45:13:0 elseif d35818 then "45:11:0 end if0 end process0 end behavioral0

Res&#!:Thus encoder circuit is implemented using three models.

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