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Digital System Design

This document provides an overview of the course "Digital System Design". The course covers designing digital systems using ASM charts, hardware description languages, and control sequence methods. It also covers sequential circuit design using ROMs, PLAs, CPLDs, and FPGAs. The course discusses fault modeling and testing techniques like fault diagnosis, path sensitization, Boolean difference, and Kohavi algorithms. It also covers test pattern generation techniques like D-algorithm, PODEM, random testing, and signature analysis. Fault diagnosis in sequential circuits and machine identification are also part of the course. The course teaches designing with programmable logic arrays, PLA minimization, and PLA folding. PLA testing covers fault models and test generation

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3K views1 page

Digital System Design

This document provides an overview of the course "Digital System Design". The course covers designing digital systems using ASM charts, hardware description languages, and control sequence methods. It also covers sequential circuit design using ROMs, PLAs, CPLDs, and FPGAs. The course discusses fault modeling and testing techniques like fault diagnosis, path sensitization, Boolean difference, and Kohavi algorithms. It also covers test pattern generation techniques like D-algorithm, PODEM, random testing, and signature analysis. Fault diagnosis in sequential circuits and machine identification are also part of the course. The course teaches designing with programmable logic arrays, PLA minimization, and PLA folding. PLA testing covers fault models and test generation

Uploaded by

valaravi
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DIGITAL SYSTEM DESIGN

L 3 T 0 P 0 C 3

DESIGN OF DIGITAL SYSTEMS: ASM charts, Hardware description language and control sequence method, Reduction of state tables, state assignments. SEQUENTIAL CIRCUIT DESIGN: design of Iterative circuits, design of sequential circuits using ROMs and PLAs, sequential circuit design using CPLD, FPGAs. FAULT MODELING: Fault classes and models Stuck at faults, bridging faults, transition and intermittent faults. Test generation: Fault diagnosis of Combinational circuits by conventional methods Path Sensitization technique, Boolean difference method, Kohavi algorithm. TEST PATTERN GENERATION: D algorithm, PODEM, Random testing, transition count testing, Signature analysis and testing for bridging faults. FAULT DIAGNOSIS IN SEQUENTIAL CIRCUITS: State identification and fault detection experiment. Machine identification, Design of fault detection experiment. PROGRAMMING LOGIC ARRAYS: Design using PLAs, PLA minimization and PLA folding. PLA TESTING: Fault models, Test generation and Testable PLA design. ASYNCHRONOUS SEQUENTIAL MACHINE: fundamental mode model, flow table, state reduction, minimal closed covers, races, cycles and hazards. Text books: 1. Nripendra N Biswas Logic Design Theory Prentice Hall of India,2001 2. Parag K.Lala Fault Tolerant and Fault Testable Hardware Design B S Publications,2002 Reference books: 1 2 3 4 Parag K.Lala Fault Tolerant and Fault Testable Hardware Design B S Publications,2002 Parag K.Lala Digital system Design using PLD B S Publications,2003 Charles H Roth Jr.Digital System Design using VHDL Thomson learning, 2004 M. Abramovici, M. A. Breues, A. D. Friedman Digital System Testing and Testable Design, Jaico Publications.2002

Mode of evaluation: CAT- I & II, Assignments/ other tests, Term End Examination

Proceedings of the 16th Academic Council held on 25.11.2008

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