Anna University: Chennai - 600 025 B.E/B.Tech Degree Examinations, Oct-Nov-2012
Anna University: Chennai - 600 025 B.E/B.Tech Degree Examinations, Oct-Nov-2012
.Tech Degree Examinations, Oct-Nov-2012 CS2207 DIGITAL LABORATORY (Common to CSE and IT) Regulations - 2008 Time: 3 Hours 1. Maximum Marks: 100
Design a combinational circuit for verifying Boolean theorems and implement it using digital 100 logic gates Design and implement a combinational circuit using basic gates for arbitrary function like 3 100 bit adder and subtractor. Design and implement a combinational circuit using basic gates for Gray to Binary and Excess 100 3 to BCD code convertors. Design and Implement a combinational circuit for 4 bit binary adder / subtractor using MSI 100 devices a. Design and implement a combinational circuit for 3 bit parity generator and checker using 50 basic gates. b. Design and implement a combinational circuit using basic gates for arbitrary function like 50 half adder and half subtractor.
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Design and implement a combinational circuit for parity generator and checker using MSI 100 Devices. Design and implement a combinational circuit for 2 bit magnitude comparator using basic gates. a. Design and implement a combinational circuit for data selector using basic gates. b. Design and implement a combinational circuit for 1 x 4 demux using basic gates.
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100
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50 50
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a. Design and implement a combinational circuit for 4 x 1 mux using basic gates. b. Design and implement a combinational circuit for data distributor using basic gates.
50 50 50 50 50 50
10. a. Design and implement a sequential circuit for SISO and PIPO shift register.
b. Design and implement a combinational circuit for 2 bit adder.
11. a. Design and implement a sequential circuit for 3 bit asynchronous counter.
b. Design and implement a sequential circuit for Mod 10 asynchronous counter.
12. Design and implement a sequential circuit for 3 bit Synchronous Counter for up / down 100
sequence.
13. a. Design and implement a sequential circuit for 4 bit ripple counter
b.Design and implement a sequential circuit for mod 12 Asynchronous counters.
50 50 50
b. Design and implement a combinational circuit using basic gates for Gray to Binary code 50 convertor.
50
b. Design and implement a combinational circuit using basic gates for binary to gray code 50 convertor
16. a. Design and implement a combinational circuit for 1 x 4 demux using basic gates.
b. Design and implement a sequential circuit for SIPO and SISO shift register.
50 50
17. a. Design and implement a combinational circuit for Involution theorem and implement it 50
using basic gates. b. Design and implement a sequential circuit for BCD asynchronous counter
50
18. a. Design and implement a combinational circuit using basic gates for BCD to Excess 3 code 50
convertor. b. Design and implement a combinational circuit using basic gates for binary to gray code 50 convertor.
50
b. Design and implement a combinational circuit using basic gates for arbitrary function like 50 half adder and half subtractor.
50
b. Design a combinational circuit for verifying Demorgans theorems and implement it using 50 digital logic gates.