Switching Circuits & Logic Design

Jie-Hong Roland Jiang Department of Electrical Engineering National Taiwan University Fall 2009
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14 Derivation of State Graphs and Tables

Network motifs in developmental transcription networks

Uri Alon Nature Reviews Genetics, June 2007

Outline
Design of a sequence detector More complex design problems Guidelines for construction of state graphs Serial data code conversion Alphanumeric state graph notation Conversion between Mealy and Moore State Graphs

Design of a Sequence Detector Sequential Parity Checker (recap)

A parity checker for serial data
Z = 1 the total number of 1 inputs received is odd (i.e., input parity is odd) Z = 0 initially Block diagram
Parity Checker

X (data input)

Clock X Clock Z=Q

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Design of a Sequence Detector Sequential Parity Checker (recap)

State graph
X=0 S0 Z=0 even X=1
Present Output 0 1

X=1 S1 Z=1 odd X=0

State table
Present State S0 S1 Q 0 1 Next State X=0 X=1 S0 S1 S1 S0 T X=0 X=1 0 0 1 1 0 1

Logic circuit
X T CK Q Q' Z

state encoding/assignment Q+ X=0 X=1 0 1 1 0 Z

Clock

Design of a Sequence Detector {101}-Sequence Detector

Block diagram
X (data input) Sequence Detector Z Z=1 input sequence 101 is received

Clock

Input/output sequence example

X=0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 Z=0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0
Time: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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Design of a Sequence Detector {101}-Sequence Detector

Mealy machine
State diagram
0 0 0 0

S0

1 0

S0
1 1

1 0

0 0

S0
0 0 1 1

1 0

S1
0 0

S1
0 0

1 0

S1

S2 Present Output X=0 0 0 0 X=1 0 0 1

S2 A+B+ AB 00 01 10 11 X=0 00 10 00 X=1 01 01 01 -

State table
Present State S0 S1 S2 Next State X=0 S0 S2 S0 X=1 S1 S1 S1

Z X=0 0 0 0 X=1 0 0 1 -

S0: initial state S1: sequence ending with 1 received S2: sequence ending with 10 received

Design of a Sequence Detector {101}-Sequence Detector

Mealy machine
Next-state maps X 0 AB 00 0 01 1 11 x Circuit realization A' CK Clock A D X 1 AB 0 0 00 0 0 x 01 0 11 x X 0 1 AB 1 00 0 1 x 01 0 11 x 1 0 0 x

10 0 0 A+=X'B B' CK B D

10 0 1 B+=X

10 0 1 Z=XA

Assume A,B can be reset to 0 (Need to be careful about the dont care assignment if the FFs do not have reset when powered up)

Z 000010
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X 011010

Design of a Sequence Detector {101}-Sequence Detector

Moore machine
State diagram
0 S0 0 1 S1 0 0 S3 1 1 0 S0 0 1 S1 0 0 1 S2 0 S2 0 S3 1 1 0 0 S2 0 0 S0 0 1 S1 0 0 1

State table
Present State S0 S1 S2 S3 Next State X=0 S0 S1 S2 S3 X=1 S1 S2 S0 S1 Present Output Z 0 0 0 1 A+B+ AB 00 01 11 10 X=0 00 11 00 11 X=1 01 01 10 01

Z 0 0 0 1

More Complex Design Problems {010,1001}-Sequence Detector

Block diagram
X (data input) Sequence Detector Z Z=1 input sequence 010 or 1001 is received Clock

Input/output sequence example

X=0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 1 0 Z=0 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 0
Time: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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More Complex Design Problems {010,1001}-Sequence Detector

Mealy machine implementation
(1) Partial graph for 010
S1
1 0 0 0 0 1 1 0

S0

State S0 S1 S2 S3

Sequence received reset 0 01 010

S2

S3

(2) Partial graph for 1001

S0 S1
1 0 0 0 0 1 1 0 1 0
b

(3) Complete state graph

S0
0 0
f

State
0 0

Sequence ends in reset 0 (but not 10) 01 10 1 (but not 01) 100

S4
c

S2
1 1

S3
d

S5

0 0

S0 S1 S2 S3 S4 S5

S1
1 0

0 0 1 0 0 1

1 0
g

S4
c

1 0
h

0 0

0 0

S2
e

1 1

1 0

S3
0 0 11

S5

More Complex Design Problems {010,1001}-Sequence Detector

Exercise
Moore machine implementation

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More Complex Design Problems Modified Parity Sequence Detector

Block diagram
Sequence Detector

X (data input)

Z Z=1 the total number of 1s received is odd and at least two consecutive 0s have been received

Clock

Input/output sequence example

X=

1 0 1 1 0 0 1 1
odd odd odd odd odd odd

Z = (0) 0 0 0 0 0 1 0 1
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More Complex Design Problems Modified Parity Sequence Detector

Moore machine implementation
(1) Partial graph
S0
0 1 1

S0
0 0

1 1

S1
0 0

(3) Complete state graph

S1
0

S2
0 0

S5
0 0

(2) Partial graph

S0
0 0 1 1

S3
0

1 1

S4
1

S1
0

Even 1s State S0 S1 S2 S3 S4 S5 Sequence received reset on even 1s odd 1s even 1s and ends in 0 even 1s and 00 occurred odd 1s and 00 occurred odd 1s and ends in 0

Odd 1s

S2
0 0

S3
0

1 1

S4
1

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More Complex Design Problems Modified Parity Sequence Detector

Exercise
Mealy machine implementation

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Construction of State Graphs

Guidelines
1. Construct sample input/output sequences 2. Determine under what conditions, if any, the circuit should reset to its initial state 3. If only one or two sequences lead to a nonzero output, construct a partial state graph for those sequences 4. Alternatively, determine what sequences or groups of sequences must be remembered by the circuit and set up states accordingly 5. Each time an arrow is added, determine whether it can go to one of the previously defined states or whether a new state must be added 6. Check there is only one outgoing edge leaving each state for each input value 7. Test the completed graph and make sure correct

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Construction of State Graphs Example 1

Block diagram
Sequence Detector Z=1 input sequence 0101 or 1001 occurs The circuit examines groups of 4 consecutive inputs, and resets after every 4 inputs

X (data input)

Clock

Input/output sequence example

X = 0101 0010 1001 0100 Z = 0001 0000 0001 0000

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Construction of State Graphs Example 1

Mealy machine implementation
(1) Partial graph (2) Complete state graph
S0
0 0 1 0 1 0

S1
0 0 0 0 0 0

S2
0 0 0 0 1

S5
0 1 0 1

S3
0 0 0

State S0 S1 S2 S3 S4

Sequence received reset 0 1 01 or 10 010 or 100 State S5 S6 Sequence received

S6

S4

two inputs received, no 1 output is possible three inputs received, no 1 output is possible
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Construction of State Graphs Example 2 (omitted)

Block diagram
Sequence Detector Z1 Z2 Z1 = 1: every time sequence 100 is completed and 010 has never occurred Z2 = 1: every time sequence 010 is completed

X (data input)

Clock

Input/output sequence example

X=1001100101010010110100 Z1 = 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Z2 = 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0
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Construction of State Graphs Example 2 (omitted)

Mealy machine implementation
(1) Partial graph
S0
1 00 0 00

(2) Complete state graph

S1
0 00

S3
1 00

S2
0 10

S4
0 01

State S0 S1 S2 S3 S4

Description No progress on 100 Progress of 1 on 100 Progress of 10 on 100 No progress on 100 Progress of 1 on 100 No progress on 010 No progress on 010 Progress of 0 on 010 Progress of 0 on 010 Progress of 01 on 010 Progress of 0 on 010 Progress of 01 on 010 No progress on 010 010 has never occurred

partial graph for 010

S5 S6 S7

010 has occurred

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Construction of State Graphs Example 2 (omitted)

State table
Present State Next state X=0 X=1 Output Z1Z2 X=0 X=1

S0 S1 S2 S3 S4 S5 S6 S7

S3 S2 S3 S3 S5 S5 S5 S5

S1 S1 S4 S4 S1 S6 S7 S7

00 00 10 00 01 00 01 00

00 00 00 00 00 00 00 00

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Construction of State Graphs Example 3 (omitted)

Block diagram
X1 X2 Sequence Detector Z

Clock Z remains a constant value unless one of the following input sequences occurs (a) Input sequence X1X2 = 01, 11 causes Z=0 (b) Input sequence X1X2 = 10, 11 causes Z=1 (c) Input sequence X1X2 = 10, 01 causes Z to change value (X1X2 = 01, 11 means X1 = 0, X2 = 1 followed by X1 = 1, X2 = 1)
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Construction of State Graphs Example 3 (omitted)

Moore machine implementation
Observation:
Only the previous and present inputs (input sequence of length 2) will determine the output Unnecessary to use a separate state for 00 and 11 because neither input starts a sequence which leads to an output change State designation
Previous Input (X1X2) 00 or 11 00 or 11 01 01 10 10 Output (Z) 0 1 0 1 0 1 State Designation S0 S1 S2 S3 S4 S5

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Construction of State Graphs Example 3 (omitted)

State table
Present State S0 S1 S2 S3 S4 S5 Next State Z 0 1 0 1 0 1 X1X2 = 00 S0 S1 S0 S1 S0 S1 01 S2 S3 S2 S3 S3 S2 11 S0 S1 S0 S0 S1 S1 10 S4 S5 S4 S5 S4 S5

State graph

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Serial Data Code Conversion

Transmission of serial bit streams
Two common approaches
1. Clock signal transmitted along with the data
Serial Data
Transmitter Receiver

Clock

2. Clock recovery circuit used

Serial Data
Transmitter Clock Clock Recovery Circuit Receiver

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Serial Data Code Conversion

Four typical coding schemes
NRZ (non-return-to-zero) code NRZI (non-return-to-zero-inverted) code RZ (return-to-zero) code Manchester code
Easy to recover the clock signal

Example
Bit Sequence NRZ NRZI RZ Manchester Clock
1 bit time 26

Serial Data Code Conversion NRZ-Code to Manchester-Code

Mealy machine implementation
X
Converter

Use Clock2, twice the frequency of the basic clock

NRZ data Clock2

If the NRZ bit is 0 (1), it will be 0 (1) for two Clock2 periods
Z Manchester
data

S0
1

NRZ(X) 0
0 0

0 1

1 1 1 0

1 1

1 0

1 1

0 0 1

0 0

0 1

1 1 1

0 0 1

Manchester 0 (ideal)

0 0

0 0

S2

S1

Clock2 State
S0 S1 S0 S2 S0 S2 S0 S2 S0 S1 S0 S1 S0 S2 S0 S1

Present State S0 S1 S2

Next State X=0 S1 S0 X=1 S2 S0

Output Z X=0 0 1 X=1 1 0

Z (actual)
1 clock period glitch (false output)

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Serial Data Code Conversion NRZ-Code to Manchester-Code

Moore machine implementation
S0 0 0 S1 0

X(NRZ) 0
1 1 0 0

1 1

1 1 1

00

1 1

0 0

Clock2 State Z
S0 S1 S2 S3 S0 S3 S0 S3 S0 S1 S2 S1 S2 S3 S0 S1

S3 1

S2 1

0 0

1 1

1 0 1

0 0

0 1

0 0

Present State S0 S1 S2 S3

Next State X=0 S1 S2 S1 X=1 S3 S3 S0

Present Output Z 0 0 1 1

1 clock period

Output delayed by one clock period

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Alphanumeric State Graph Notation

State graphs with variable names on arc labels (and in states for Moore machine)
Example
F R
Sequential Circuit

Z1 Z2 Z3

Completely specified state graph

F'R' S0 Z1 F F F'R F'R' S2 Z3 F'R F
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Clock
Incompletely specified state graph
S0 Z1 F R S2 Z3 R F R S1 Z2 F

F'R S1 Z2 F'R'

Alphanumeric State Graph Notation

State graph
F'R' S0 Z1 F F'R F'R' S2 Z3 F'R F F'R S1 Z2 F'R' F

State table
PS S0 S1 S2 NS FR=00 01 10 S0 S2 S1 S0 S2 S1 S1 S2 S0 11 S1 S2 S0 Output Z1Z2Z3 100 010 001

Check input signals (for every state): F + F'R + F'R' = F + F' = 1 Transition defined for every input combination FF'R = 0, FF'R' = 0, F'RF'R' = 0 At most one next state for every input combination

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Alphanumeric State Graph Notation

A completely specified state graph has the following properties
1. ORing together all input labels on arcs outgoing from a state reduces to 1 (i.e., complete transition)
For every input combination, at least one next state is defined

2. ANDing together any pair of input labels on arcs outgoing from a state reduces to 0 (i.e., deterministic transition)
For every input combination, no more than one next state is defined

If both properties are true, then exactly one next state is defined

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Alphanumeric State Graph Notation

Convention for Mealy machine
The label XiXj/ZpZq on an arc means if Xi and Xj are 1 (we dont care what the other input values are), the outputs Zp and Zq are 1 (and the other outputs are 0) E.g., for a circuit with 4 inputs (X1, X2, X3, X4) and 4 outputs (Z1, Z2, Z3, Z4) X1X4'/Z2Z3 is equivalent to 1--0/0110

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Conversion between Mealy and Moore State Graphs

Convert Mealy to Moore
1. Push the output label on an edge to its next state (so delay introduced!) 2. If a state receives different output labels, duplicate the state such that every copy has exactly one output label 3. Connect every edge properly to the state with correct output label

Convert Moore to Mealy

1. Distribute the output label of a state to its incoming edges 2. Simplify the state graph by merging equivalent states
Mealy-type implementation of a circuit can have fewer states than Moore-type implementation
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Conversion between Mealy and Moore State Graphs

Exercise
0 0 S0 0 1 S1 0 0 1 S3 1 1 0 0 S2 0

S0
0 0 1 1

1 0

0 1 0

S1
0 0

S2

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