Design Verification & Testing

Faults

CMPE 418

Fault Equivalence Review Equivalence fault collapsing is performed in a level-by-level pass from inputs to output using local (gate level) fault equivalences.

A B sa1 C sa0 sa1 D sa0 F sa1 sa0

sa1 sa0 sa1 sa0

H sa1 sa0 sa1 V sa0 sa1Z sa0

G sa1 sa0 sa1 E sa0

One of the faults in each of this equivalence remains

{A/0, B/0, H/0} {C/1, D/1, F/1, G/0} 10/20 = 0.5 remain {E/0, G/0, V/0} {H/1, V/1, Z/1} Faults with no equivalence also remain {F/0, G/1} Reduction is between 50-60% and is larger, in general, for fanout free circuits.
1

Design Verification & Testing

Faults

CMPE 418

Fault Dominance If fault detection is the objective (not diagnosis), then fault dominance can be used to further reduce the fault list. If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1. Dominance Fault Collapsing: If fault F2 dominate fault F1, then F2 is removed from the fault list. When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates. Illustrated in the next example. In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set. If two faults dominate each other then they are equivalent. For sequential circuits, it should be noted that equivalence fault-collapsing techniques are valid but dominance fault-collapsing techniques are NOT.

Design Verification & Testing

Faults All Tests of F2

CMPE 418

Dominance Example

sa1 F1

sa1 F2

110 101

001 000 100

Dominance Fault Collapsed fault set

010 011

sa1 sa1 sa1 sa0

Only Test of F1

Dominance fault collapsing is performed from outputs to inputs. 7/ 20 = 0.35 remain

A B

sa1 sa0 sa1

H sa1 sa0 sa0 V sa1 Z sa0

sa1 C sa0 D sa0

F sa1 sa0

One such fault list may be: {A/0, A/1, B/1, C/0, C/1, D/0, E/1} Or another may be: {B/0, A/1, B/1, C/0, D/1, D/0, E/1}
3

G sa1 sa0 sa1 E sa0

Design Verification & Testing

Faults

CMPE 418

Checkpoint faults Primary inputs and fanout branches of a combinational circuit are called checkpoints. Checkpoint Theorem A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit.

sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1

Total Fault Sites = 10 + 6 = 16 Total Checkpoints = 10

sa0 sa1

sa0 sa1 sa0 sa1

sa0 sa1
4

Design Verification & Testing

Faults

CMPE 418

Checkpoint Faults Therefore, it is sufficient to target faults only at the checkpoints. Structural equivalence and dominance relations can then be used to further collapse the list of faults. For example, this circuit has 24 SSFs. But it only has 14 checkpoint faults (the 5 PIs) + G and H.

A sa1 sa0 B sa1 sa0 C D sa1

F sa1
sa1 G sa0

Equivalent

Dominates

H sa0

sa1

K sa1

sa0 E sa0 sa0

This leaves 10 faults from the original list of 14 checkpoint faults.

Design Verification & Testing

Faults

CMPE 418

Classes of Stuck-At Faults Following classes of single stuck-at faults are identified by fault simulators: Potentially-detectable fault: Test produces an unknown (X) state at primary output (PO); detection is probabilistic, usually with 50% probability Initialization fault: Fault prevents initialization of fault circuit; present in circuits with memory elements; can be detected as a potentially detectable fault Hyperactive fault: Fault induces much internal signal activity without reaching PO Redundant fault: A fault that done not modify the input-output function of the circuit. A redundant fault cannot be detected using SSF tests Untestable fault: Faults for which the test generator is unable to find a test.

Design Verification & Testing

Faults

CMPE 418

Multiple Stuck-At faults A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3k-1 A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare. Statistically, single fault tests cover a very large number of multiple faults. It might be important to consider them if diagnostic or fault localization procedures don't work with multiple faults.

Design Verification & Testing

Faults

CMPE 418

Transistor (Switch) Faults MOS transistor is considered as an ideal switch and two types of faults are modeled: Stuck-open: a single transistor is permanently stuck in the open state Stuck-short: a single transistor is permanently shorted irrespective of it's gate voltage. Detection of a stuck-open fault requires a two vector sequence. Vector 1: Test for A SA0 (initialization vector) 1 0 0 0 A B C 0

Stuck-Open fault Faulty Circuit States

1 (Z) Good Circuit States

Vector 2: Test for A SA1 Two vector stuck-open test can be constructed by ordering two SA tests

Design Verification & Testing

Faults

CMPE 418

Transistor (Switch) Faults Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ).

Vector: Test for A SA0 1 0 A B

Stuck-Short fault Faulty Circuit Output C 0 (X) Good Circuit Output

IDDQ path in faulty circuit

Design Verification & Testing

Faults

CMPE 418

Bridging Faults Modeled at the gate or transistor level as a short between 2 (simple) or more of signal lines. Non-feedback versus feedback (memory) versions. Bridging fault Feedback Bridging fault

Fault is usually modeled using wired logic: AND and OR. For CMOS, it depends on the type of gates driving the shorted lines and their input values. A C RAp RAn B D Transistor modeled as a resistor RBp RBn Voltage divider

10

Design Verification & Testing

Faults

CMPE 418

Bridging Faults The transistor resistances determine the appropriate model: Input values A=B A=0, B=1 A=0, B=1 Resistance relationships Any ratio RAp > RBn RAp < RBn RAn > RBp RAn < RBp Resulting output value
C=D C=D=0 C=D=1 C=D=1 C=D=0

Wired logic model.

Bridging faults that can not be represented by a known fault model. Defect-free Z= AB + CD A B C D A B C D Defective Z= (A+B)(C+D)

Some convert combination circuits to sequential (feedback bridging).

Design Verification & Testing

Faults

CMPE 418

Delay Faults Transition Fault (gross-delay faults): Gate delay increased to point where transition does not reach output before end of clock period, even along the shortest path. Gate-delay Fault: Defect increases input to output delay of a single logic gate. Line-delay Fault: In contrast to transition fault, a test here must propagate the transition through the longest sensitizable path. Path-delay Fault: This fault causes the cumulative propagation delay of a path to increase beyond some specified time duration. Segment-delay Faults: A segment (of length L gates) delay fault increases the delay of a segment such that all paths containing the segment have a path-delay fault. Segment-delay = Path-delay if L is the maximum combinational depth of the circuit. Segment-delay = Transition fault if L is 1.

12