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Design Rules: Jan M. Rabaey

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44 views9 pages

Design Rules: Jan M. Rabaey

hi

Uploaded by

Manikandan
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Design Rules

Jan M. Rabaey

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Cross-Section of CMOS Technology

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Design Rules
Interface

between designer and pr cess

engineer !uidelines f r c nstructing pr cess "as#s $nit di"ensi n% Mini"u" line widt& ' scalable design rules% la"bda para"eter ' abs lute di"ensi ns ("icr n rules)

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

CMOS Process Layers


Layer -ell (p.n) /cti0e /rea (n1.p1) 4elect (p1.n1) P lysilic n Metal1 Metal* C ntact + P ly C ntact + Diffusi n ,ia Color 2ell w !reen !reen Red 3lue Magenta 3lac# 3lac# 3lac# Representation

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Intra-Layer Design Rules


Same Potential 0 or 6 10 3 Active 3 2 Select Contact or Via Hole 2 Metal2 3
Digital Integrated Circuits Design Rules Prentice Hall 1995

Different Potential 9 Polysilicon 2 Metal1 2 3 4 3 2

Well

Transistor Layout
Transistor

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Vias and Contacts


2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4

2 2

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Select Layer
2 3 2 1 3 3 Select

Substrate
Digital Integrated Circuits Design Rules

Well
Prentice Hall 1995

CMOS Inverter Layout


GND In VD D A A

Out (a) Layout

A p-substrate n
+

A n p
+

Field Oxide

(b) Cross-Section along A-A


Digital Integrated Circuits Design Rules Prentice Hall 1995

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