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No. Type Mnemoni C Action Op Code

This document describes the instruction set of a microprocessor. It lists 43 instructions organized into different types, including data transfer, ALU operations, unconditional branches, and conditional branches. The instructions are specified by a 3-bit operation code and optionally a 3-bit register number or 2-bit condition code. The mnemonic, operation code, and action of each instruction is provided.

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Sidhartha Sankar Rout
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78 views3 pages

No. Type Mnemoni C Action Op Code

This document describes the instruction set of a microprocessor. It lists 43 instructions organized into different types, including data transfer, ALU operations, unconditional branches, and conditional branches. The instructions are specified by a 3-bit operation code and optionally a 3-bit register number or 2-bit condition code. The mnemonic, operation code, and action of each instruction is provided.

Uploaded by

Sidhartha Sankar Rout
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Type

Mnemoni
c

Action

Op
Code

NOP

No action

00

MVD
<rn>*

[<rn>] [R0] (n = 1,
2...7)

01-07

SPC

[[R0]] [PC]

08

MVS
<rn>*

[R0] [<rn>] (n = 1,
2...7)

09-0F

MVI <rn>
xx

[<rn>] xx

10-17

LSP xx

[SP] xx

18

LDA
<rn>*

[<rn>] [[R0]] (n = 1,
2...7)

19-1F

SSP

[[R0]] [SP]

20

STA
<rn>*

[[R0]] [<rn>] (n = 1,
2...7)

21-27

10

LDI <rn>
xx

[<rn>] [xx]

28-2F

11

STI <rn>
xx

[xx] [<rn>]

30-37

12

POP <rn>

[<rn>] [[SP]], [SP]


[SP]+1

38-3F

13

PSH <rn>

[SP] [SP]1, [[SP]]


[<rn>]

48-4F

No.
1

6
7
8
9

14
15
16
17
18
19

Data
Transfer
(Register
number
<rn> given
by OC2-0)

ALU
NOT
[<rn>] [<rn>]
Operation
<rn>
(ALU
INC <rn>
[<rn>] [<rn>] + 1
Function
DCR
code <af>
[<rn>] [<rn>] 1
<rn>
given by
OC7-4; <rn>
CLR
<rn> 0, n = 07
or <n>
Rotate [R0] Left by n Bits,
given by
RLA <n>*
CY B8-n (n = 1, 2...7)
OC2-0)
ADA <rn> [R0] [R0] + [<rn>]

40-47
50-57
60-67
70
71-77
80-87

20

ADI <rn>
xx

[<rn>] [<rn>] + xx

88-8F

21

SBA <rn>

[R0] [R0] [<rn>]

90-97

22

SBI <rn>
xx

[<rn>] [<rn>] xx

98-9F

23

ACA <rn> [R0] [R0] + [<rn>] + C

A0-A7

24

ACI <rn> [<rn>] [<rn>] + xx +


xx
C

A8-AF

25

SCA <rn> [R0] [R0] [<rn>] C

B0-B7

26

SCI <rn>
[<rn>] [<rn>] xx C
xx

B8-BF

27

ANA <rn> [R0] [R0] AND [<rn>]

C0-C7

28

ORA
<rn>

[R0] [R0] OR [<rn>]

D0-D7

29

XRA <rn>

[R0] [R0] [<rn>]

E0-E7

30

XNA <rn>

[R0] [R0] [<rn>]

F0-F7

Mnemoni
c

Action

Op
Code

JUD xx

[PC] xx

58

32

CUD xx

[SP] [SP]1, [[SP]]


[PC],
[PC] xx

59

33

JUP xx

[PC] [PC] + xx

5A

34

CUP xx

[SP] [SP]1, [[SP]]


[PC],
[PC] [PC] + xx

5B

JUA

[PC] [R0]

5C

CUA

[SP] [SP]1,[[SP]]
[PC],
[PC] [R0]

5D

JUI

[PC] [[R0]]

5E

RTU

[PC][[SP]], [SP][SP]+1

5F

RTC <fl>

[PC][[SP]],
[SP][SP]+1 if <fl> = 1

68-6F

JCA <fl>

[PC] [R0] if <fl> = 1

78-7F

JCD <fl>
xx

[PC] xx if <fl> = 1

C8-CF

CCD <fl>
xx

[SP] [SP]1, [[SP]]


[PC],
[PC] xx if <fl> = 1

D8-DF

JCP <fl>
xx

[PC] [PC] + xx if <fl>


=1

No.

Type

31

Unconditio
nal Branch

35
36

37
38
39
40
41
42

Conditiona
l Branch
(Condition
code <fl>
given by
OC2-0)

E8-EF

43

[SP] [SP]1, [[SP]]


CCP <fl>
[PC],
xx
[PC] [PC] + xx if <fl>
=1

F8-FF

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