REGULATION - B

M.Tech DEGREE EXAMINATION, DEC 2012

P1VLB02

ADVANCED DIGITAL SYSTEM DESIGN

Time: Three hours

maximum: 100 marks

Part A (10 x 1 marks = 10 marks)
(5 x 2 marks = 10 marks)

Answer all Questions. First 10 questions carry one mark each and the remaining 5 questions carry 2 marks each
1. What is the size of RAM in 8051 microcontroller?
a)

256 bytes

b)128 bytes

c) 1 GB

d) 4 GB

2. How many interrupts available in 8051 microcontroller?

a) 6
c) 128

b) 256
d) 255

3. Which of the following pins are used to connect the crystal oscillator in 8051?
a) To, T1.

B) XTAL2, XTAL1

c) RXD, TXD

d) ALE, PSEN

4. Which timer of the 8051 is used to set the baud rate?

a) timer1

b)timer 2

c) timer 3

d) timer 1& timer2.

5. Which flag of the timer is used to generate the interrupt.

a) overflow

b) timer run

c) Gate bit

d) counter/timer select bit.

6. What is the hex value of hex code command for display on ,cursor on
a) B

b)A

c)10

d)1C

7.In case of sEOS, the tasks will be implemented using functions which are called from the ---a) time driven ISR

b) Interrupt driven ISR

c) PSEN

d)Interrupt register.

8. Which timer is used as auto reload function.

a) timer 1

b) timer 2

c) timer 3

d) ISR

9. In multi state timed systems, the transition between states depends on--a) passage of time

b) system input

c) system output

d) both a & b

10. In multi state (input/timed) , the transition between state depends on

a) system input

b) passage of time

c) system output

d) both a &b

11. Define Sequential Circuits

12. Design procedure for asynchronous sequential circuit
13. Draw Xilinx FPGA Structure
14. What Is a State Machine?
15. Mention VHDL operators.
Part B (5 x6 marks= 30 marks)
(Answer ALL questions. Each question carries 6 marks.)
16. Explain about ASM Chart.
17. What is Hazards and explain different types of hazards
18. Describe the design flow of Xilinx FPGA
19. write short notes on Advanced Microprocessor concepts
20. Write a short note on any two implementation of flip flops

Part C (5 x10 marks= 50 marks)

(Answer ALL questions. Each question carries 10 marks)
21. A) with an example explain the state assignment rule?
(OR)

B) Design of CSSN in detail.

22. A) Explain in detail the Analysis of Asynchronous Sequential Circuit (ASC).
(OR)
B) Design a Vending Machine Controller.
23. A) with neat diagram explain Xilinx 3000 series with FPGA.
(OR)
B) Programmable Logic Devices-detail.
24. A) write a short notes on logic design and finite state machine, programmable logic devices.
(OR)
B) Explain about High performance memory technologies
25. A) Write VHDL program for Multiplier.
(OR)
B) Explain in detail about Register and counters.

Answers:
11. Sequential Circuits: It Consist of a combinational circuit to which storage elements are connected to form a
feedback path Specified by a time sequence of inputs, outputs, and internal states
Two types of sequential circuits:
-

Synchronous

Asynchronous

12. The recommended procedural steps for the design of a complete asynchronous sequential circuit are:
1. State the design specifications.
2. Derive a Primitive Flow Table.
3. Reduce the Flow Table by merging rows.
4. Make a racefree binary state assignment.
5. Obtain the transition table and output map.
6. Obtain the logic diagram using SR latches.
13.

14. State machine :A state machine is a digital device that traverses through a predetermined sequence of states in
an orderly fashion.A state is a set of values measured at different parts of the circuit. A simple state machine can
consist of PALdevice based combinatorial logic, output registers, and buried (state) registers. The state in such a
sequencer is determined by the values stored in the buried and/or output registers.
15. VHDL operators:

Logical Operators
Numerical Operators
Relational Operators

Shift Operators
Concatenation Operator

16. Algorithmic State Machine (ASM) :

Algorithmic State Machine (ASM) Chart is a high-level flowchart-like notation to specify the hardware
algorithms in digital systems.

Major differences from flowcharts are:

uses 3 types of boxes: state box (similar to operation box), decision box and conditional box
contains exact (or precise) timing information; flowcharts impose a relative timing order for the
operations.

From the ASM chart it is possible to obtain

the control
the architecture (data processor)

ASM Charts: An Example

A is a register; Ai stands for ith bit of the A register.

A = A4A3A2A1

E and F are single-bit flip-flops.

17. Hazard : A hazard is a momentary switching transient at a logic function output. it occur due to unequal
propagation delays along different path in a combinational circuits. Hazards occur in in combinational and
asynchronous circuits:
In combination circuits, they may cause a temporarily false output value.
In asynchronous circuits, they may result in a transition to a wrong stable state.
Types of hazards.

The first implementation may cause the output to go to 0 when it should remain at 1 (Static 1
hazard), while the second implementation may cause the output to go to 1 when it should remain
at 0 (Static 0hazard).
The dynamic hazard causes the output to change three or four times when it should change from 1
to 0 or from 0 to 1.

18.

19. Computer architecture is central to the design of digital systems, because most digital systems are, at their core,
computers surrounded by varying mixes of interfaces to the outside world. Many technologies that were originally
developed for high-end supercomputers and mainframes eventually found their way into consumer electronics and
other less-expensive digital systems.

It is wide range of technologies that are alluded to in many technical specifications but are often not
understood sufficiently to take full advantage of their potential. What is a 200-MHz superscalar RISC processor with
a four-way set associative cache. Some people hear the term RISC and conjure up thoughts of high-performance
computing. Such imagery is not incorrect, but RISC technology can also be purchased for less than one dollar.
Caching is another big computer term that is more common than many people think.
The architecture of one directly influences the capabilities of the other. For this reason, the two
need to be considered simultaneously during the design process. Among many other factors, this
makes computer design an iterative process. One may begin with an assumption of the type of microprocessor
required and then use this information to influence the broader system architecture. When system-level constraints
and capabilities begin to come into focus, they feed back to the microprocessor requirements, possibly altering them
somewhat. This cycle can continue for several iterations until a design is realized in which the microprocessor and
its supporting peripherals are well matched for the application.
20. Implementation of JK flip flop:

If JK = 00, SR = 00 because of AND so SR wont change state when clocked

If JK = 10, R must be 0:

if Q=0, Q=1, so SR=10, the set condition: flip flop will change state (to Q=1)

if Q=1, Q=0, SR=00 (stable condition) so flip flop stays in Q=1

If JK = 01, final state is Q=0 (analogous to JK=10)

If JK=11, Q connects directly to R, Q to S

so if Q=0, SR=10, so Q=1

if Q=1, SR=01, so Q=0

Implementation of D flip flop :

D: data; one input + CP

Q(t+1) independent of Q(t) depends only on value of D at time t

D flip flop holds data until next pulse

21. A)

State Assignment
Each state must be assigned a unique code
Minimum number of bits required for m states in the state diagram is n such that n log2 m , where x is the
smallest integer x
There are useful state assignments that use more than the minimum number of bits
If n bits are used, there are 2n m unused state
State Assignment Example
Present
State
A
B
C
D

Next State
x=0 x=1
A
B
A
C
D
C
A
B

Output
x=0 x=1
0
0
0
0
0
0
0
1

21. B)
-

Clocked (synchronous) sequential circuits

Synchronous sequential circuits have the concept of memory and use a clock to determine when things
happen in a circuit.
inputs outputs combinatorial circuit flip-flops current state clock next state function
When the clock signal changes, the current state will change to the next state depending on the next
state function.
The next state function may be a function of the current state and the inputs (the current state is like
memory and determines what will happen next).

22. A)
Asynchronous sequential circuits
Asynchronous circuits: within large synchronous systems, it is often desirable to allow certain subsystems to operate
asynchronously to reduce delay and power consumption
Total state: combination of signals that appear at the primary input and delay outputs
Input state: combination of input signals x1, x2, , xl
Secondary or internal state: combination of signals at the delay outputs y1, y2, , yk
Secondary or internal variables: y1, y2, , yk
Excitation variables: Y1, Y2, , Yk

Stable state: for a given input state, the circuit is said to be in a stable state if and only if yi = Yi for i = 1, 2, , k

In response to a change in the input state: the combinational logic produces a new set of values for
the excitation variables, entering an unstable state

When the secondary variables assume their new values (when ys become equal to the
corresponding Ys): the circuit enters its next stable state

Thus, a transition from one stable state to another occurs only in response to a
change in the input state

Fundamental mode: when a change in input values has occurred, no other change in any input value occurs until the
circuit enters a stable state

Single-input change (SIC) fundamental mode: a single input value is allowed to change at
a time

(OR)
22.

B)

23. A)

XC3000-Series Field Programmable Gate Arrays (FPGAs) provide a group of high-performance, highdensity, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture
is composed of a configuration program store plus three types of configurable elements: a perimeter of I/O
Blocks (IOBs), a core array of Configurable Logic Bocks (CLBs) and resources for interconnection.

The FPGA user logic functions and interconnections are determined by the configuration program data
stored in internal static memory cells. The program can be loaded in any of several modes to accommodate
various system requirements.

The program data resides externally in an EEPROM, EPROM or ROM on the application circuit board, or
on a floppy disk or hard disk. On-chip initialization logic provides for optional automatic loading of
program data at power-up.

(OR)
B). Realization State machine using PLD
24. A)

State Machine
A state machine is a digital device that traverses through a predetermined sequence of states in an orderly
fashion. A state is a set of values measured at different parts of the circuit. A simple state machine can consist of
PAL device based combinatorial logic, output registers, and buried (state) registers. The state in such a sequencer is
determined by the values stored in the buried and/or output registers.

i.Block Diagram of a Simple State Machine

Next State Decoders

ii.State Machine, with Separate Output and

Programmable logic devices

An IC that contains large numbers of gates, flip-flops, etc. that can be configured by the user to perform different
functions is called a Programmable Logic Device (PLD).
The internal logic gates and/or connections of PLDs can be changed/configured by a programming process.

Three Fundamental Types of PLDs:

The three fundamental types of PLDs differ in the placement of programmable connections in the AND-OR arrays.
Figure shows the locations of the programmable connections for the three types.

The PROM (Programmable Read Only Memory) has a fixed AND array (constructed as a decoder) and
programmable connections for the output OR gates array. The PROM implements Boolean functions in
sum-of-minterms form.
The PAL (Programmable Array Logic) device has a programmable AND array and fixed connections
for the OR array.
The PLA (Programmable Logic Array) has programmable connections for both AND and OR arrays.
So it is the most flexible type of PLD.
(OR)

24.B)
25. A)
(OR)
25. B)