PS2 Verilog
PS2 Verilog
PS2_DAT,
PS2_CLK2,
PS2_DAT2,
//////// SDCARD //////////
SD_CLK,
SD_CMD,
SD_DAT,
SD_WP_N,
//////// VGA //////////
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS,
//////// Audio //////////
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
//////// I2C for EEPROM //////////
EEP_I2C_SCLK,
EEP_I2C_SDAT,
//////// I2C for Audio and Tv-Decode //////////
I2C_SCLK,
I2C_SDAT,
//////// Ethernet 0 //////////
ENET0_GTX_CLK,
ENET0_INT_N,
ENET0_MDC,
ENET0_MDIO,
ENET0_RST_N,
ENET0_RX_CLK,
ENET0_RX_COL,
ENET0_RX_CRS,
ENET0_RX_DATA,
ENET0_RX_DV,
ENET0_RX_ER,
ENET0_TX_CLK,
ENET0_TX_DATA,
ENET0_TX_EN,
ENET0_TX_ER,
ENET0_LINK100,
//////// Ethernet 1 //////////
ENET1_GTX_CLK,
ENET1_INT_N,
ENET1_MDC,
ENET1_MDIO,
ENET1_RST_N,
ENET1_RX_CLK,
ENET1_RX_COL,
ENET1_RX_CRS,
ENET1_RX_DATA,
ENET1_RX_DV,
ENET1_RX_ER,
ENET1_TX_CLK,
ENET1_TX_DATA,
ENET1_TX_EN,
ENET1_TX_ER,
ENET1_LINK100,
//////// TV Decoder //////////
TD_CLK27,
TD_DATA,
TD_HS,
TD_RESET_N,
TD_VS,
/////// USB OTG controller
OTG_DATA,
OTG_ADDR,
OTG_CS_N,
OTG_WR_N,
OTG_RD_N,
OTG_INT,
OTG_RST_N,
OTG_DREQ,
OTG_DACK_N,
OTG_FSPEED,
OTG_LSPEED,
//////// IR Receiver //////////
IRDA_RXD,
//////// SDRAM //////////
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
//////// SRAM //////////
SRAM_ADDR,
SRAM_CE_N,
SRAM_DQ,
SRAM_LB_N,
SRAM_OE_N,
SRAM_UB_N,
SRAM_WE_N,
//////// Flash //////////
FL_ADDR,
FL_CE_N,
FL_DQ,
FL_OE_N,
FL_RST_N,
FL_RY,
FL_WE_N,
FL_WP_N,
//////// GPIO //////////
GPIO,
//////// HSMC (LVDS) //////////
// HSMC_CLKIN_N1,
// HSMC_CLKIN_N2,
HSMC_CLKIN_P1,
HSMC_CLKIN_P2,
HSMC_CLKIN0,
// HSMC_CLKOUT_N1,
// HSMC_CLKOUT_N2,
HSMC_CLKOUT_P1,
HSMC_CLKOUT_P2,
HSMC_CLKOUT0,
HSMC_D,
// HSMC_RX_D_N,
HSMC_RX_D_P,
// HSMC_TX_D_N,
HSMC_TX_D_P,
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input
input
input
input
CLOCK_50;
CLOCK2_50;
CLOCK3_50;
ENETCLK_25;
SMA_CLKIN;
SMA_CLKOUT;
LEDG;
LEDR;
KEY;
//////////// SW //////////
input
[17:0]
SW;
HEX0;
HEX1;
HEX2;
HEX3;
HEX4;
HEX5;
HEX6;
HEX7;
LCD_BLON;
LCD_DATA;
LCD_EN;
LCD_ON;
output
output
LCD_RS;
LCD_RW;
UART_CTS;
UART_RTS;
UART_RXD;
UART_TXD;
PS2_CLK;
PS2_DAT;
PS2_CLK2;
PS2_DAT2;
SD_CLK;
SD_CMD;
SD_DAT;
SD_WP_N;
VGA_B;
VGA_BLANK_N;
VGA_CLK;
VGA_G;
VGA_HS;
VGA_R;
VGA_SYNC_N;
VGA_VS;
AUD_ADCDAT;
AUD_ADCLRCK;
AUD_BCLK;
AUD_DACDAT;
AUD_DACLRCK;
AUD_XCK;
output
input
output
input
output
input
input
input
input
input
input
input
output
output
output
input
[3:0]
[3:0]
ENET0_GTX_CLK;
ENET0_INT_N;
ENET0_MDC;
ENET0_MDIO;
ENET0_RST_N;
ENET0_RX_CLK;
ENET0_RX_COL;
ENET0_RX_CRS;
ENET0_RX_DATA;
ENET0_RX_DV;
ENET0_RX_ER;
ENET0_TX_CLK;
ENET0_TX_DATA;
ENET0_TX_EN;
ENET0_TX_ER;
ENET0_LINK100;
ENET1_GTX_CLK;
ENET1_INT_N;
ENET1_MDC;
ENET1_MDIO;
ENET1_RST_N;
ENET1_RX_CLK;
ENET1_RX_COL;
ENET1_RX_CRS;
ENET1_RX_DATA;
ENET1_RX_DV;
ENET1_RX_ER;
ENET1_TX_CLK;
ENET1_TX_DATA;
ENET1_TX_EN;
ENET1_TX_ER;
ENET1_LINK100;
TD_CLK27;
TD_DATA;
TD_HS;
TD_RESET_N;
TD_VS;
output
input
output
input
output
inout
inout
OTG_RD_N;
OTG_INT;
OTG_RST_N;
[1:0] OTG_DREQ;
[1:0] OTG_DACK_N;
OTG_FSPEED;
OTG_LSPEED;
[1:0]
IRDA_RXD;
DRAM_ADDR;
DRAM_BA;
DRAM_CAS_N;
DRAM_CKE;
DRAM_CLK;
DRAM_CS_N;
DRAM_DQ;
DRAM_DQM;
DRAM_RAS_N;
DRAM_WE_N;
SRAM_ADDR;
SRAM_CE_N;
SRAM_DQ;
SRAM_LB_N;
SRAM_OE_N;
SRAM_UB_N;
SRAM_WE_N;
FL_ADDR;
FL_CE_N;
FL_DQ;
FL_OE_N;
FL_RST_N;
FL_RY;
FL_WE_N;
FL_WP_N;
GPIO;
HSMC_CLKIN_N1;
//input
input
input
input
//output
//output
output
output
output
inout
//input
input
//output
output
[3:0]
[16:0]
[16:0]
[16:0]
[16:0]
HSMC_CLKIN_N2;
HSMC_CLKIN_P1;
HSMC_CLKIN_P2;
HSMC_CLKIN0;
HSMC_CLKOUT_N1;
HSMC_CLKOUT_N2;
HSMC_CLKOUT_P1;
HSMC_CLKOUT_P2;
HSMC_CLKOUT0;
HSMC_D;
HSMC_RX_D_N;
HSMC_RX_D_P;
HSMC_TX_D_N;
HSMC_TX_D_P;
EX_IO;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire HEX0P;
wire HEX1P;
wire HEX2P;
wire HEX3P;
wire HEX4P;
wire HEX5P;
wire HEX6P;
wire HEX7P;
//=======================================================
// Structural coding
//=======================================================
// Flash Config
//assign
FL_RST_N = reset_n;
assign
FL_WP_N = 1'b1;
// FL_RY,
///////////////////////////////////////////
// LCD config
assign LCD_BLON = 0; // not supported
assign LCD_ON = 1'b1; // alwasy on
/*wire io_dir;
wire action;
assign io_dir = KEY[3] & action;
*/
///////////////////////////////////////////
// GPIO
//assign GPIO[17:0] = (io_dir)?GPIO[35:18]:18'hz;
//assign GPIO[35:18] = (io_dir)?GPIO[17:0]:18'hz;
///////////////////////////////////////////
// HSMC
//assign HSMC_D[1:0] = (io_dir)?HSMC_D[3:2]:2'hz;
//assign HSMC_D[3:2] = (io_dir)?HSMC_D[1:0]:2'hz;
assign HSMC_TX_D_P = HSMC_RX_D_P;
//assign HSMC_TX_D_N = HSMC_RX_D_N;
//assign HSMC_CLKOUT_N1 = HSMC_CLKIN_N1;
//assign HSMC_CLKOUT_N2 = HSMC_CLKIN_N2;
assign HSMC_CLKOUT_P1 = HSMC_CLKIN_P1;
assign HSMC_CLKOUT_P2 = HSMC_CLKIN_P2;
assign HSMC_CLKOUT0 = HSMC_CLKIN0;
///////////////////////////////////////////
// VGA
assign VGA_BLANK_N = 1'b1;
assign VGA_SYNC_N = 1'b1;
///////////////////////////////////////////
// NET
assign ENET0_GTX_CLK = ENET0_INT_N;
//assign ENET0_GTX_CLK = ENET0_MDIO;
assign ENET0_MDC = ENET0_RX_COL;
assign ENET0_RST_N = ENET0_RX_CRS;
//assign ENET0_RX_CLK = ENET0_RX_DV;
assign ENET0_TX_DATA = ENET0_RX_DATA;
assign ENET0_TX_EN = ENET0_RX_ER;
assign ENET0_TX_ER = ENET0_TX_CLK;
assign ENET1_GTX_CLK = ENET1_INT_N;