EE413 Tutorials

Sample Verilog HDL Codes

Sample Verilog HDL Codes

The HDL (Hardware Description Language) is used or descri!ing the circuit !" codes instead o circuit elements# $ore speci icall"% the HDL codes ta&e place o 'schematics( in the cadence li!raries# )or instance% in order to descri!e a D))% one should insert the su!*elements li&e in+erters% ,-,D gates% etc# in the schematics# ." using HDL% it is possi!le to descri!e the same circuit !" t"ping a num!er o lines o HDL code# There are mainl" / hardware description language generations0 HDL% and Verilog*HDL# -lthough !oth o them are used hea+il"% we will wor& on Verilog*HDL% since it is easier% and it is closer to engineering concepts# The Verilog*HDL +ersion em!edded in the cadence design en+ironment is called as Verilog* 1L# There are / wa"s o writing Verilog*1L codes% one is gate*le+el% and the other is !eha+ioral#

A master-slave D-type Flip Flop

This will !e a sample or gate*le+el Verilog*1L code# 2ate*le+el Verilog*1L code is not much di erent than drawing schematics# The ollowing igure shows the schematics o the D))% and the Verilog*1L code !elow that descri!es this circuit#

1# /# 3# 4# 3# 4# 5# 6# 7# 18# 11# 1/# 13# 14# 13# 14#

99 - master*sla+e t"pe D*)lip )lop module lop (data% cloc&% clear% :% :!); input data% cloc&% clear; output :% :!; 99 primiti+e <dela" instance*name (output% input1% input/% #####)% nand <18 nd1 (a% data% cloc&% clear)% nd/ (!% ndata% cloc&)% nd4 (d% c% !% clear)% nd3 (e% c% ncloc&)% nd4 ( % d% ncloc&)% nd6 (:!% :% % clear); nand <7 nd3 (c% a% d)% nd5 (:% e% :!); not <18 in+1 (ndata% data)% in+/ (ncloc&% cloc&); endmodule

,ote that% each node and each component in the schematics ha+e a uni:ue name# The inputs and output o the components are important# )or instance the inputs o 'nd3( are a and d% and the output is c# ,ow let=s see the code in detail# 1# The irst line is the comment line# /# This line descri!es the name o the circuit# The ormat is as !elow0 module >circuit?name@ ( >pin1@%>pin/@%###%>pin n@); module is the &e"word#
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The name o the circuit here is lop% and there are 3 pins with
1 Last updated on 1/91/9/883

EE413 Tutorials

Sample Verilog HDL Codes

corresponding names# descri!ed "et#

,ote that the direction o the pins (either input or output) are not

3# This line descri!es the input pins% and its ormat is as !elow0 input >pin 1@% >pin /@%###% >pin &@; -ccording to the ormat a!o+e% data% clock% and clear pins are input pins# 4# Similar to line 3% this line descri!es the output pins# So q and qb are the output pins# 4# ,ow the description o the circuit starts# )or the lines rom 4 to 13% the ollowing ormat is +alid0 >primiti+e?gate@ >dela"?time@ >name@ (>out@% >in1@%>in/@###); This line inserts a component with t"pe o primitive_gate ha+ing a transition time o delay_time# The name o the component is name% and the output and inputs are out and in1% in2%### Eriting this line is same as inserting the component in the schematics% !ecause this line sa"s that there is a gate o t"pe primitive_gate% and its pre erences are li&e this# )or instance see the line 4# Bt sa"s that there is a nand gate with 18ns transition time# Bts name is nd1% its output is a% and its inputs are data% cloc&% and clear# ,ote that this is eFactl" one o the nand gates in the schematics (chec& itG)# Each line !etween 4 and 13 descri!e one component# So as "ou can see% gate*le+el Verilog*1L code is not +er" much di erent than drawing schematics# -ctuall" B usuall" pre er drawing schematics instead o this method 0) Hne point here is important# Lines 5 to 11 ha+e a slightl" di erent ormat# Bt has onl" the name and input9output pins o the component# This is a shortcut or descri!ing man" components in a shorter orm# This means that nd/% nd4% nd3% nd4% and nd6 ha+e the same transition time o 18ns# .e care ul a!out the punctuations at the ends o the lines# Line 4 has '%(% and line 11 has ';( as the last character# 14#States the end o the circuits code with endmodule &e"word# 2ate*le+el HDL representation o the circuit is not much di erent than drawing the schematics# )urthermore% "ou need the schematics o the circuit !e ore t"ping gate*le+el code# So% this method is not pre erred much# Howe+er% it is a good starting point to learn Verilog# The neFt eFample will !e !eha+ioral and it is much more important#

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EE413 Tutorials

Sample Verilog HDL Codes

- 1*!it s"nchronous counter with parallel load and reeIe modes% and with as"nchronous reset option
Bn this part% Verilog*1L code o a 1*!it s"nchronous counter with parallel load and reeIe modes% and with as"nchronous reset option will !e descri!ed# The ollowing code is the inal code% and it will !e descri!ed in detail#

99 Verilog HDL or JEE413J% JC,T1J J unctionalJ 99 Verilog HDL model o a 1*!it parallel loada!le s"nchronous counter with 99 as"nchronous reset and reeIe eatures module C,T1(D% L% Ti% C.% CLK% L% L!% Tout); input D% L% Ti% C.% CLK; output L% L!% Tout; reg :% tout; 99 De ine a 4*to*1 multipleFer unction function muF; input M308N in; input M108N s; case (s) /=!880 muF O inM8N; /=!810 muF O inM1N; /=!180 muF O inM/N; /=!110 muF O inM3N; endcase endfunction 99 $odel the as"nc reset always @(C.) begin if (GC.) assign : O 1=!8; else deassign :; end 99 $odel the pos edge !eha+iour always @(posedge CLK) : O muF(PD% D% Q:% :R% PL% TiR); 99 $odel the Tout always @(Ti or :) tout O Ti & :; 99 )inal output pin assignments assign Tout O tout; assign L O :; assign L! O Q:; endmodule To start with% 99 indicates a single comment line (as in the CSS)# The C,T module is de ined at the +er" !eginning !" &e"word module# module C,T1(D% L% Ti% C.% CLK% L% L!% Tout); ,ote that% at this point% we do not &now which pins are input and which are output# To de ine these we should write0 input D% L% Ti% C.% CLK; output L% L!% Tout; Eith the a!o+e / lines% we descri!ed the input9output pins o the circuit#

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Last updated on 1/91/9/883

EE413 Tutorials

Sample Verilog HDL Codes

Bn addition to this% we should also de ine internal +aria!les% to store results !e ore assigning them to the output pins# Bn other words% the output pins cannot !e changed directl" in the code# Bnstead% an internal +aria!le will !e used and it will !e assigned (or let=s sa" attached) to the output pin# Ehen this internal +aria!le changes% the output pin which is assigned to it will change also# Bn this eFample% there are 3 outputs# Howe+er% since L! is logical in+erse o L% we need onl" / internal +aria!les# : and tout are the internal +aria!les (registers) in our eFample# -t the end o the code% tout is assigned to Tout% : is assigned to L% and Q: (logical in+erse o :) is assigned to L!# The ollowing line de ines the registers to !e used in the code# reg :% tout; The neFt lines de ine a unction# Such unctions ma&e codes much simpler and shorter# )re:uentl" used architectures can !e de ined as a unction% and then the" can !e in+o&ed rom the main !loc& as man" times as desired# -s "ou all &now% we need a 4*to*1 multipleFer to per orm% !oth load% toggle% and reeIe operations# )or this purpose we ha+e to de ine a 4*to*1 multipleFer unction% which can !e done as ollows0 (Ee ha+e a 4*!it input M308N in% and a two !it selection !its M108N s)# function muF; input M308N in; input M108N s; case (s) /=!880 muF /=!810 muF /=!180 muF /=!110 muF endcase endfunction

O O O O

inM8N; inM1N; inM/N; inM3N;

The de inition o a unction is made !etween unction and end unction &e"words# The multipleFing de inition is !est descri!ed using case# Tou should re er to the Verilog Tutorial or urther in ormation% i re:uired# Here note that% /=!88 represents a /*!it num!er o 88# The de inition 'input M308N in;( states that the input in is a 4*!it num!er# inM8N corresponds to the 8th !it% and so on# Bs it possi!le to write this code without using unctionU ,ow% we will de ine how the registers (and so outputs) will change according to the inputs# )or this% always statement will !e used# There are a num!er o wa"s to use it# always @(posedge CLK) : O muF(PD% D% Q:% :R% PL% TiR); The line a!o+e descri!es the s"nchronous operation o the circuit# ,ote that% the de initions starting with always indicates the unction dependenc" o certain signals# Here% the statement in the alwa"s !loc& will !e done when positi+e edge o CLK is sensed (,ote that V and posedge are also &e"words)# The statement in the alwa"s !loc& is changing the +alue o : register# ,ote the use o unction muF# PD%D%Q:%:R is the 4*!it input with : is the least signi icant !it# So inM8N corresponds to :% and so on# PL% TiR is the /*!it output o the unction# So% when a positi+e edge (low*to*high) transition is sensed% the register q will !e changed !" the results o mux unction# always @(C.) begin if (GC.) assign : O 1=!8; else deassign :; end This alwa"s statement models the as"nchronous reset operation# Here% we de ine that : +aria!le should !e changed whene+er there is a change in C.# Bnside the alwa"s !loc& (!egin*end is re:uired or multi commands)% we chec& the +alue o C.# B its Iero (8)% then we assign 8 to :% i not we deassign :# ,ow% one important point should !e clear# Two alwa"s statements descri!ed a!o+e changes the +alue o :# Howe+er% we want to iF the +alue o : to 8 when C. is low (wh"U)# This is done !" using assign* deassign statement pair# This statement pair is used to iF the +alue o a register until it is released !"
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EE413 Tutorials

Sample Verilog HDL Codes

deassign# So% when the +alue o : is iFed when C! is low% the other alwa"s statements a ecting the +alue o : are ignored# Ehen C! !ecomes high again% : register is released !" deassign statement# Tou ma" understand this !etter !" simulating the circuit without deassign statement# always @(Ti or :) tout O Ti & :; The last alwa"s statement is generating the Tout signal# This time% the module or the lines inside that !loc& should !e eFecuted whene+er there is a change in Ti or :# There ore @(Ti or :) is written a ter the alwa"s !loc&# Since it is again a single assignment no !egin*end are used# ,ote that & is used or logical and operation# So% we used 3 alwa"s statements# This is o!+ious actuall"% !ecause we should model the s"nchronous operation o the circuit% as"nchronous reset operation% and the toggle output# This is it# B am sure that "ou will !e a Verilog eFpert a ter a ew trials#

- Wossi!le $A14 Verilog*1L Code

module $A14 (L% B% S); input M308N B; input M108N S; output L; wire <(3% 18) :; function muF; input M308N in; input M108N s; case (s) /=!880 muF O inM8N; /=!810 muF O inM1N; /=!180 muF O inM/N; /=!110 muF O inM3N; endcase endfunction always V(B or S) : O muF(B% S); assign L O :; endmodule The a!o+e code is supplied without an" warrant"# That is it ma" unction or not# Bt is gi+en Xust to gi+e an idea# .ut +er ication is le t to "ou#

How to Realize the

ircuits Described by !erilog"

There are so tware tools called s"nthesis tools% that s"nthesiIes the descri!ed circuit rom a set o user de ined !loc&s# The li!rar" which includes these !loc&s are called s"nthesis li!rar"# $ost o the digital -SBC chips are designed using this methodolog"# That is% the digital -SBC designer irst descri!es the circuit using !eha+ioral Verilog HDL# Then he9she uses s"snthesis tools (usuall" ST,HWSTS) to generate the netlist o the re:uired circuit# The generated netlist contains reguired !loc&s% and their connecti+it" in ormation# - s"nthesis operation can !e optimiIed with respect to timing% area% or with some other cost parameters de ined !" the designer# - ter o!taining the re:uired netlist% the netlist is ed into WL-CE and CHATE (WC) tools# The" !asicall" ta&e the s"nthesiIed netlist% and according to the user supplied speci ications (num!er o cell rows% routing channel spacings% pin locations% signal priorities% etc)% it irst places the cells instanced in the s"nthesiIed netlist and per orms routing o the signals# Asuall"% routing is also per ormed in more than one step# )or eFample power% cloc&% and ordinar" signal routing is per ormed in di erent steps# Especiall" the irst two steps are gi+en highest priorit"# That is% the computer consumes more CWA power% or per orms more detailed anal"sis while connecting power rails and cloc& lines# Toda" Verilog is used eFtensi+el" in digital -SBC or )W2- designs# )or eFample% compleF )W2- designs also start with the Verilog codes (sometimes re erred as s"nthesiIea!le codes)# Depending on the inal product% the s"nthesis li!rar" can !e either a VLSB standard cell s"nthesis li!rar" or a certain t"pe o )W2- amil"#

$ETA $E$S*VLSB Cesearch 2roup D /883

Last updated on 1/91/9/883