SerialCommunications

(Chapter10) RS232,SPI,I2C

Communications
Thesimplestisparallel
Oneway
Theremaybemechanismfor peripheraltogetattentionof C (i.e.,interrupt,orpoll)
C Multiple(8 typically)data lines

L t h Latch CS

Peripheral

Twoway
Data lines C

Latch CS R/~W

Peripheral

Thisisresourceexpensive(pins, (pins realestate) estate )interms ofhardware,buteasytoimplement

SerialCommunications
Manyfewerlinesarerequiredtotransmitdata.Thisisrequires fewerpins pins,butaddscomplexity. complexity
Data
C

Clock CS

Peripheral

Synchronouscommunicationsrequiresclock.Whoevercontrols theclockcontrolscommunicationspeed. Asynchronoushasnoclock,butspeedmustbeagreedupon beforehand(baudrate).

AsynchronousSerial(RS232)
Commonlyusedforonetoonecommunication. communication Therearemanyvariants,thesimplestusesjusttwolines,TX (transmit)andRX(receive). Transmissionprocess(9600baud,1bit=1/9600=0.104mS)
Transmitidleshigh(whennocommunication). Itgoesl lowf for1bit(0 (0.104 104mS) S) Itsendsoutdata,LSBfirst(7or8bits) Theremaybeaparitybit(evenorodd errordetection) Theremaybeastopbit(ortwo)

RS232Voltagelevels
Fromprocessorside,0V=logic0,3.3V=logic1 serial cable+12+3V=logic0 0, 312V=logic1 Inaserial

OnExperimentersboard Physicalconnector

RS232 Handshaking
SomeRS232connectionsusinghandshakinglinesbetween DCE( (DataCommunicationsEquipment) q p )andDTE( (Data TerminalEquipment).
RTS(ReadyToSend)
SentbytheDTEtosignaltheDCEitisReadyToSend.

CTS(ClearToSend)
SentbytheDCEtosignaltheDTEthatitisReadytoReceive.

DTR(DataTerminalReady)
SenttoDTEtosignaltheDCEthatitisreadytoconnect

DSR(DataSetRead)
SenttoDCtosignaltheDTEthatitisreadytoconnect

I Inpractice ti ifthese th handshaking h d h ki lines li areused ditcanbe b difficulttosetuptheserialcommunications,butitisquite robustonceworking. Thereisalsosoftwarehandshaking(XON/XOFF) DTEandDCEhavedifferentconnectorpinouts.

MSP430USCIinUARTmode
(alsoUSARTperipheral)
UARTmodefeaturesinclude: 7 or8bitdata;odd,even,ornonparity Independenttransmitandreceive LSBfirstorMSBfirstdata Receiverstartedge d d detectionf forauto wakeupfromLPMx modes Independentinterruptcapabilityfor receiveandtransmit Statusflagsforerrordetectionand suppression Builtinidlelineandaddressbit communicationprotocolsfor p systems y multiprocessor Statusflagsforaddressdetection

UARTcode
#include "msp430xG46x.h" void main(void) { volatile unsigned int i; P4SEL |= 0x0C0; UCA0CTL1 |= UCSSEL_1; UCA0BR0 = 0x03; UCA0BR1 = 0x00; UCA0MCTL = 0x06; UCA0CTL1 &= ~UCSWRST; IE2 |= UCA0RXIE; _BIS_SR(LPM0_bits + GIE); }

// // // // // // // // // // //

Echo a received character, RX ISR used. Normal mode is LPM3, USCI_A0 RX interrupt triggers TX Echo. ACLK = BRCLK = LFXT1 = 32768, MCLK = SMCLK = DCO~1048k Baud divider, 32768hz XTAL @9600= 32768/9600= 3.41(0003h 03h ) ----------------/|\| MSP430xG461x || | XIN|- 32kHz --|RST XOUT|| P4.7/UCA0RXD|------------> | | 9600 - 8N1 | P4 P4.6/UCA0TXD|<-----------6/UCA0TXD|<

// // // // // // //

P4.7,6 = USCI_A0 RXD/TXD CLK = ACLK 32k/9600 - 3.41 Users manual has formulas for these Modulation **Initialize USCI state machine** Enable USCI_A0 RX interrupt

// Enter LPM0, interrupts enabled

// Echo back RXed character, confirm TX buffer is ready first #pragma vector=USCIAB0RX_VECTOR __interrupt p void USCIA0RX_ISR ( (void) ) { while(!(IFG2&UCA0TXIFG)); // Make sure last character went out. UCA0TXBUF = UCA0RXBUF; // TX -> RXed character }

SPI
(SerialPeripheralInterface Motorola)

Twotypesofdevices,mastersandslaves. Well consideronlyonemaster,but multipleslaves. Signals

SPIandtheclock
(intro) Pullslaveselectlinelowtoselectdevice. First i bi bitof fd datagetsputonMISO SOand dMOSI OS (soabytegoesbothways) Data D t gets t shifted hift dout t(typically ( i ll 8bits, bi but b notnecessarily) il )
Thedatagetsputonbusonfallingedgeofclock. Thedatagetsreadontherisingedgeofclock. clock

SPIandtheclock
(thehardtruth)
Unfortunately,clockcanbesetmanywaysasdeterminedbyclockpolarityandphase.

CPOL=0:Basevalueoftheclockis0
CPHA=0:Datareadonrisingedge,putonbusonfallingedgeofSCLK.(i.e.,clockislow). (Casefrompreviousslide) CPHA=1:Datareadonfallingedge,putonbusonrisingedge(i.e.,clockishigh).

CPOL=1:Basevalueoftheclockis1
CPHA=0:Datareadonfallingedge,putonbusonrisingedge(i.e.,clockishigh). CPHA=1:Datareadonrising gedge, g ,put p onbusonfalling gedge g (i.e., ( ,clockislow). )

SPIandSCI
SPImodefeaturesinclude: 7 or8bitdatalength LSBfirstorMSBfirstdata Masterorslavemodes Selectableclockpolarity and dphase h control t l Programmableclock frequencyinmastermode Independenttransmitand receive Continuoustransmitand receive Independentinterrupt capability p yforreceiveand transmit SlaveoperationinLPM4

SPICode
#include "msp430xG46x.h" void main(void) { volatile unsigned int i; char data; P5DIR |= 0x02; P3SEL |= 0x0C; P3DIR |= 0x01; UCB0CTL0 |= UCMST+UCSYNC+UCMSB; UCB0CTL1 |= UCSSEL_2; UCB0BR0 = 0x02; UCB0BR1 = 0; UCB0CTL1 0 1 &= ~UCSWRST; while(1) { P3OUT &= ~0x01; UCB0TXBUF = 0x00; while (!(IFG2 & UCB0RXIFG)); data = UCB0RXBUF; P3OUT |= 0x01; if(data>=0x7F) P5OUT |= 0x02; else P5OUT &= ~0x02; } }

// MCLK = SMCLK = default DCO ~1048k, BRCLK = SMCLK/2 // ---------------------// /|\| MSP430xG461x | // TLC549 | | XIN |32kHz // --------------|RST XOUT|// | CS|<---|P3.0 | // | DATAOUT|--->|P3.2/UCB0SOMI | // ~>| IN+ I/O CLK|<---|P3.3/UCB0CLK P5.1|--> LED

// // // // // //

P5.1 output P3.3,2 option p select P3.0 output direction 8-bit SPI mstr, MSb 1st, CPOL=0, CPHS=0 SMCLK Set Frequency

// ** **Initialize i i li USCI state machine** hi **

// Enable TLC549 (A/D) , ~CS (~SS) reset // Dummy write to start SPI // USCI_B0 RX buffer ready? // data = 00|DATA // Disable TLC549, ~CS (~SS) set // data = AIN > 0.5(REF+ - REF-)? // LED off LED On

I2CorI2C
(InterIntegrated ( g Circuit Philips) p)
AswithSPIamaster slavesystem. y Alsocalleda2wirebus. ItHasonly yclockanddata, ,withpull p up presistors(Rp ( p in diagram). Linescanbepulledlowbyanydevice,andarehigh whenalldevicesreleasethem. Therearenoslaveselectlines insteadthedevices haveaddressesthataresentaspartofthe transmissionprotocol. Fourmaxspeeds(100kbS (standard),400kbS (fast),1 MbS (fastplus),and3.4MbS (highspeed)

I2CWriteaSingleByte

1. 2 2. 3. 4. 5. 6. 7.

All: allowSDA,SCLstarthigh M Master: SDAlow l tosignal i lstart Master:SendoutSCL,and7bitaddressfollowedby0(~W)onSDA Slave:PullSDAlowtosignifyACKnowledge Master:Sendout8databitsonSDA Slave:Ack All: allowSDAtogohighwhenSCLishigh(stop) ForRead, 3 3. M t Address Master: Add following f ll i by b 1(R)onSDA 5. Slave:Sendout8databitsonSDA 6. Master:Ack

OtherFeatures
Youcantransfermultiplebytesinarow

Atendoftransfer, transfer slavecanholdSCLlowtoslow transferdown(calledclockstretching)

Anydevicethatmalfunctionscandisablebus.

I2CandSCI
TheI2Cfeaturesinclude:
CompliancetoPhilipsI2Cspecification Slave Sl receiver/transmitter i /t itt mode d Standardmodeupto100kbpsand fastmodeupto400kbpssupport ProgrammableUCxCLK frequencyin mastermode Designedforlowpower SlavereceiverSTARTdetectionfor autowakeupfromLPMx modes SlaveoperationinLPM4

I2CCode

// // // // // // // // // // // //

MSP430xG461x Demo - USCI_B0 I2C Master Interface to DAC8571, Write Description: Using UCB0TXIE, a continuous sine wave is output to external DAC using a 16-point look-up table. Only one start is executed. Data is handled by the ISR and the CPU is in LPM0. MCLK = SMCLK = TACLK = BRCLK = 1MHz DAC8571 I2C address = 0x4C (A0 = GND) MSP430xG461x DAC8571 -----------------------------|XIN P3.1/UCB0SDA|<--------------->|SDA | 32kHz | P3.2/UCB0SCL|---------------->|SCL I2C | -|XOUT |XOUT | | SLAVE | | I2C MASTER | GND|A0 |

void main(void) { WDTCTL = WDTPW + WDTHOLD; P3SEL |= 0x06; UCB0CTL1 |= UCSWRST; UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; UCB0CTL1 = UCSSEL_2 + UCSWRST; UCB0BR0 = 11; UCB0BR1 = 0; UCB0I2CSA = 0x4c; UCB0CTL1 &= ~UCSWRST; IE2 |= UCB0TXIE; UCB0CTL1 |= UCTR + UCTXSTT; UCB0TXBUF = 0x010; __bis_SR_register(CPUOFF g ( + GIE); ); } // USCI_B0 Data ISR #pragma vector = USCIAB0TX_VECTOR __interrupt void USCIAB0TX_ISR(void) { static unsigned char ByteCtr; UCB0TXBUF = Sine_Tab[ByteCtr++]; ByteCtr &= 0x1f; }

// // // // // // // // // // // //

Stop Watchdog Timer Assign I2C pins to USCI_B0 Enable SW reset I2C Master, synchronous mode Use SMCLK, keep SW reset fSCL = SMCLK/11 = 95.3kHz Set slave address Clear SW reset, resume operation Enable TX ready interrupt I2C TX, start condition Write DAC control byte Enter LPM0 w/ / interrupts p

// Transmit data byte // Do not exceed table

Wireless
Order:Increasing gcomplexity, p y,power p andbandwidth
SimpliciTI:<200kbS Zigbee (IEEE802.15.4):250kbS Bluetooth(IEEE802.15.1): 802 15 1):1MbS 24MbS WiFi (IEEE802.11):b11MbS;g54MbS;n150MbS

Dataratesneeded
Voice:4kbS Music:700kbS Video:3.5MbS Standard;40MbS Bluray

References
MSP430x4xxFamilyUsersGuidehttp://focus.ti.com/lit/ug/slau056j/slau056j.pdf MSP430FG4618/F2013Experimenters E i Board B dUsers U Guide G id http://focus.ti.com/lit/ug/slau213a/slau213a.pdf h //f i /li / / l 213 / l 213 df SerialComm imagehttp://www.ee.nmt.edu/~rison/ee308_spr99/supp/990406/sync_serial.gif RS232byteimagehttp://www.eeherald.com/images/rs2323.jpg RS232ConnectorImagehttp://www.bisque.com/tom/bluetooth/Images/db9.jpg SPIhttp://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus I2C:http://en.wikipedia.org/wiki/I%C2%B2C I2C:http://www.bestmicrocontrollerprojects.com/i2ctutorial.html I2C:http://www.eetimes.com/design/analogdesign/4010395/SIGNALCHAINBASICSPart32Digital interfacescontTheI2CBus