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ER T 02 Practice Test

The document is an ARM architecture and programming practice test containing multiple choice and true/false questions about ARM architecture topics including operating modes, instruction set, pipeline stages, and register functions.

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Rohit Kshirsagar
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© Attribution Non-Commercial (BY-NC)
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Download as DOC, PDF, TXT or read online on Scribd
59 views2 pages

ER T 02 Practice Test

The document is an ARM architecture and programming practice test containing multiple choice and true/false questions about ARM architecture topics including operating modes, instruction set, pipeline stages, and register functions.

Uploaded by

Rohit Kshirsagar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Embedded Robotics Practice Test ER T 02: - ARM Architecture & Programming Batch: - ER/AUG !2 "ate: !#-!!20!

$ote: - All Questions are mandatory %&!' (e)ect a**ro*riate ans+er&


1.

,2 Mar-s'

Execution of instruction is suspended and processor is applied with clock in which of the following power control mode. a) Power Down b) Data Abort c) !" d' .d)e A$% stands for a) b' c) d) Ad&anced $igh Peripheral %us Ad/anced 0igh Per1ormance Bus Ad&anced $igh %arrel hifter Ad&ance $igh %us Architecture

#.

'.

$ow many operating modes are present in A()*+D)", e' f) g) h) 2 1 .

..

$ighest priority is gi&en to which slot/ a' b) c) d) 0 1'1 1

%&2' 3i)) .n the B)an-s&


1. #. '. .. -.

,4 Mar-s'

A() instruction set uses 00000000'# bit00000000 address architecture. A() * has 0000'00000 stage pipeline. +imer 1ontrol (egister 2+3+1() is 000'#bit000 bits wide/ 24bit) "n A()*+D)", 56 6 stands for 0000synthesi7able 000000. Assembly instruction +( means 000000 tore register0000000.

%&5' (tate True/3a)se&


1. #. '. .. -.

,4 Mar-s'

"nterrupt er&ice (outine cannot be passed parameters but they return &alue. f "n 8P1#1.x +")E(3 9 +")E(1 cannot work simultaneously. f +he A()*+D)", processor has :on,;eumann architecture.2+rue) +he most recent con&ersion result of AD1 is stored in AD< (. 2=alse,AD< ( A>D <loble tarter (egister>ADD( ,A>D data register) A()* has - mode bits in 1P ( that will decide operating modes of arm. t

%&6' E7*)ain 8P(R +ith diagram& ,8urrent *rogram status Register'

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Embedded Robotics Practice Test ER T 02: - ARM Architecture & Programming Batch: - ER/AUG !2 "ate: !#-!!20!2

***************************************************************************** *

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