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Pipelined ADC Algorithm

Pipelined ADC Algorithm

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shashankif
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38 views12 pages

Pipelined ADC Algorithm

Pipelined ADC Algorithm

Uploaded by

shashankif
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Pipelined ADC

Algorithm of Pipelined ADC

By Shashank Karkare
28 Oct. 2013 1

Analog to Digital Converters


Nyquist-Rate ADCs
Flash ADCs
Sub-Ranging ADCs Folding ADCs

Pipelined ADCs
Successive Approximation (Algorithmic) ADCs Integrating (serial) ADCs

Oversampling ADCs
Delta-Sigma based ADCs

Conversion Principles

Principle
Serial Conversion Successive Approximation Parallel Conversion Delta Sigma

Resolution
High >12 Bit Medium 8-14 Bit Low 6-10 Bit High >12 Bit

Speed
Low <1kHz Medium <10MHz High <100MHz Low-Medium <1MHz

Cost
Low Medium High Low (analog only)
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ADC Architectures
Flash ADCs: High speed, but large area and high power dissipation.
Suitable for low-medium resolution (6-10 bit). Sub-Ranging ADCs: Require exponentially fewer comparators than Flash ADCs. Hence, they consume less silicon area and less power. Pipelined ADCs: Medium-high resolution with good speed. The tradeoffs are latency and power. Successive Approximation ADCs: Moderate speed with mediumhigh resolution (8-14 bit). Compact implementation. Integrating ADCs or Ramp ADCs: Low speed but high resolution. Simple circuitry. Delta-Sigma based ADCs: Moderate bandwidth due to oversampling, but very high resolution thanks to oversampling and noise shaping.

Resolution vs. Speed of commercially available ADCs

ADCs : Tomorrow?

Block Diagram of a Pipelined ADC

Overview of Pipelined ADC


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After the input signal has been sampled, compare it to VREF/2. The output of each comparator is the bit conversion for that stage. If vIN > VREF/2 (comparator output is 1), VREF/2 is subtracted from the held signal and pass the result to the amplifier. If VIN < VREF/2 (comparator output is 0), then pass the original input signal to the amplifier. The output of each stage in the converter is referred to as the residue. Multiply the result of the summation by 2 and pass the result to the sample and- hold of the next stage.

Example

Fischer 08

Fischer 08

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Reference

CMOS Circuit Design, Layout, and Simulation 2nd Edition - R. Jacob Baker ADC Pipeline Lecture - Texas A&M University

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Thank You !!

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