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Ece 195 Lab 1

Ace Virgil D. Villaruz submitted a report on the layout of a CMOS inverter circuit. The report included the schematic, layout parameters, individual PMOS and NMOS layouts, metal routing, DRC and LVS checks, SPICE files, pre-simulation and post-simulation results. The post-simulation results from the layout showed improvements over the pre-simulation schematic results in offset voltage, rise time, fall time and slew rate. The layout simulation also had fewer glitches. The conclusion was that the CMOS inverter layout performed better than the schematic.

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103 views11 pages

Ece 195 Lab 1

Ace Virgil D. Villaruz submitted a report on the layout of a CMOS inverter circuit. The report included the schematic, layout parameters, individual PMOS and NMOS layouts, metal routing, DRC and LVS checks, SPICE files, pre-simulation and post-simulation results. The post-simulation results from the layout showed improvements over the pre-simulation schematic results in offset voltage, rise time, fall time and slew rate. The layout simulation also had fewer glitches. The conclusion was that the CMOS inverter layout performed better than the schematic.

Uploaded by

Donna Ambalong
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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ECE 195

MICROELECTRONICS
LABORATORY 1

CMOS INVERTER LAYOUT

Submitted by: Ace Virgil D. Villaruz BSECE 5

Submitted to: Prof. Jefferson A. Hora

July 16, 2013

SCHEMATIC

Inverter testbench

Inverter CMOS circuit schematic

LAYOUT PARAMETERS

WP = 6.6 m;

LP = 0.8 m;

MP = 3 m;

WN = 8 m;

LN = 0.8 m;

MN = 3 m

INVERTER LAYOUT

PMOS

NMOS

METAL ROUTING

DRC

LVS

LPE

SP FILES (FRAGMENT)

input.spi

inverter.sp (edited)

RESULTS

Pre-simulation (schematic)

Post simulation (layout)

Comparison (red: schematic; blue: layout)

OFFSET VOLTAGE

PRESIM

POSTSIM

Layout simulation has less offset voltage.

RISE TIME

PRESIM

POSTSIM

Layout simulation has less rise time then the schematic simulation which means bigger slew rate. Slew rate SCHEMATIC_RISE = Slew rate LAYOUT_RISE = = = 316.90 V/s = 381.36 V/S

FALL TIME

PRESIM

POSTSIM

Layout simulation has less fall time then the schematic simulation which means bigger slew rate. Slew rate SCHEMATIC_FALL = Slew rate LAYOUT_FALL = = GLITCHES = 622.84 V/s = 684.41 V/S

PRESIM POSTSIM

Post simulation has less glitch.

CONCLUSION Post simulations show that the CMOS inverter layout is better in performance than the schematic. The waveforms in both post- and pre-simulations are of many glitches due to parameters in rise time and fall time of 10 ns both---considering that the period is 100 ns---and also in the sizes of the CMOS. However, post simulation still proves better response in rise and fall time, including slew rate. It also has less glitch. Layout of the CMOS inverter used two metals, metal 1 and metal 2.

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