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U - Submacro - Eth - 1g10g - L U - 5 - 2 Top - Mac - Ffmgmii - Ahb - Inst Top - Mac - Ffmgmii RX - CLK - Ena - Reg

This document describes the configuration of clock gating logic and status registers for an Ethernet MAC module. It mentions logic units for clock gating, status values, and signal enables for an Rx clock.

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amitwangoo
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20 views1 page

U - Submacro - Eth - 1g10g - L U - 5 - 2 Top - Mac - Ffmgmii - Ahb - Inst Top - Mac - Ffmgmii RX - CLK - Ena - Reg

This document describes the configuration of clock gating logic and status registers for an Ethernet MAC module. It mentions logic units for clock gating, status values, and signal enables for an Rx clock.

Uploaded by

amitwangoo
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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u_submacro_eth_1g10g_l u_5_2 top_mac_ffmgmii_ahb_inst top_mac_ffmgmii

rx_clk_ena_reg SDN

u_refclk_gate u_5
u_ckgate E SE GCP ckout ckout[5] ref_clk A U16 Z rx_clk rx_clk

D Q rx_clk_ena rx_clk CP DFPSQX1MV0SI35D

U_MACH U_MAC U_MAC U_RX clk_gate_match_ctl_32_reg


latch E SE GCP ENCLK A CP CLKSGLLX2BV0SI35D BUFX1BV0SI35D CDN DFPRQX1MV0SI35D U224 Z CP A rsv_stat_val_int_reg D Q A U204 Z A B INVX1RV0SI35D U202 Z CDN SDFPRQX1MV0SI35D U242 Z rsv_stat_val rsv_stat_val rsv_stat_val rxclk_ena

U_CTL U_STAT U_COLRX U_MAPC


rsv_stat_val rsv_stat_val rsv_stat_val stat_val_d_reg D SE Q SI CP CDN SDFPRQX1MV0SI35D stat_val_o_int_reg D SE Q SI CP

BUFX1BV0SI35D CP CLKSGLLX4BV0SI35D

rsv_stat_val

stat_val_o

submacro_eth_1g10g_ethmon_clk_switchon_4 submacro_eth_1g10g_ethmon_clk_switchon_vect_size10_0

NOR2X1MV0SI35D

INVX1RV0SI35D xgmii_rxclk_ena xgmii_rxclk_ena xgmii_rxclk_ena

submacro_eth_1g10g_SNPS_CLOCK_GATE_HIGH_m4_cont_10g_rxc_0_4 submacro_eth_1g10g_m4_cont_10g_rxc_4 submacro_eth_1g10g_m4_top_10g_contc_4 submacro_eth_1g10g_m4_top_10g_contc_mgmii_4 submacro_eth_1g10g_m4_mac32_host_mgmii_gen_EG_FIFO32_EG_ADDR5_ING_FIFO32_ING_ADDR5_4 submacro_eth_1g10g_m4_top_mac_ffmgmii_4 submacro_eth_1g10g_m4_top_mac_ffmgmii_ahb_4 eth_1g_10g_mac_pcs_4 submacro_eth_1g10g

submacro_eth_1g10g_m4_stats_maprxcnts_4 submacro_eth_1g10g_m4_stats_collect_vrx_CNTWIDTH64_CNTSATURATEOPT1_4 submacro_eth_1g10g_m4_stats_topn_CNTWIDTH64_CNTSATURATEOPT1_4 submacro_eth_1g10g_m4_mac_control_mgmii_gen_EG_FIFO32_EG_ADDR5_ING_FIFO32_ING_ADDR5_4

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