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Materials For Performance Improvements Seminar Report

This seminar report discusses materials for performance improvements in digital CMOS design. It covers topics such as differential amplifier circuits, Cascode Voltage Switch Logic, Differential Split Level Logic, Cascode Nonthreshold Logic, sense amplifier circuits, dual rail Domino Logic, Sample Set Differential Logic, and Enable/Disable CMOS Differential Logic. It was submitted by Himani Kishor Borse, a student in the Department of Electronics & Telecommunication Engineering at G.H.Raisoni College of Engineering and Management in Pune, India.

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38 views2 pages

Materials For Performance Improvements Seminar Report

This seminar report discusses materials for performance improvements in digital CMOS design. It covers topics such as differential amplifier circuits, Cascode Voltage Switch Logic, Differential Split Level Logic, Cascode Nonthreshold Logic, sense amplifier circuits, dual rail Domino Logic, Sample Set Differential Logic, and Enable/Disable CMOS Differential Logic. It was submitted by Himani Kishor Borse, a student in the Department of Electronics & Telecommunication Engineering at G.H.Raisoni College of Engineering and Management in Pune, India.

Uploaded by

sgdhruv
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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G.H.

RAISONI COLLEGE OF ENGINEERING AND MANAGEMENT, WAGHOLI, PUNE DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION ENGINEERING
CLASS: M.E. (Sem I) SUBJECT:DIGITAL CMOS DESIGN

SEMINAR REPORT ON Materials for performance Improvements Seminar Report


Submitted by Name:- Mr. Borse Himani Kishor Roll No.:- 31

CONTENT

Topic

Page no

1. Differential amplifier circuit 2. CVSL(Cascode Voltage Switch Logic) 3. DSL(Differential Split Level) Logic 4. Cascode Nonthreshold Logic (CNTL) 5. Sense amplifier ckt 6. Generic sense amplifier ckt 7. Dual rail Domino Logic 8. Sample Set Differential Logic (SSDL) 9. Enable/Disable CMOS Differential Logic (ECDL) 10. Refernces

1 1 3 4 5 6 7 8 9 10

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