Scribd
Upload
32 views0 pages

Lecture27 - Flip Flops: Jagannadha Naidu K

This document discusses sequencing elements like latches and flip-flops. It explains that latches are level sensitive while flip-flops are edge triggered. Various latch designs are described like pass transistor latches, transmission gates, inverting buffers, and tristate feedback. Flip-flops are built from pairs of back-to-back latches. Additional features like enables, resets, and set/reset are also covered.

Uploaded by

him92
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
32 views0 pages

Lecture27 - Flip Flops: Jagannadha Naidu K

This document discusses sequencing elements like latches and flip-flops. It explains that latches are level sensitive while flip-flops are edge triggered. Various latch designs are described like pass transistor latches, transmission gates, inverting buffers, and tristate feedback. Flip-flops are built from pairs of back-to-back latches. Additional features like enables, resets, and set/reset are also covered.

Uploaded by

him92
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 0

Lecture27 Flip flops

Jagannadha Naidu K
Outline
Sequencing
Sequencing Element Design
Latches
Flip-flops
Sequencing
Combinational logic
output depends on current inputs
Sequential logic
output depends on current and previous inputs
Requires separating previous, current, future
Called state or tokens
Ex: FSM, pipeline
CL
clk
in out
clk clk clk
CL CL
Pipeline Finite State Machine
Sequencing Overhead
Use flip-flops to delay fast tokens so they
move through exactly one stage each cycle.
Inevitably adds some delay to the slow
tokens
Makes circuit slower than just the logic delay
Called sequencing overhead
Some people call this clocking overhead
But it applies to asynchronous circuits too
Inevitable side effect of maintaining sequence
Sequencing Elements
Latch: Level sensitive
a.k.a. transparent latch, D latch
Flip-flop: edge triggered
A.k.a. master-slave flip-flop, D flip-flop, D register
Timing Diagrams
Transparent
Opaque
Edge-trigger
D
F
l
o
p
L
a
t
c
h
Q
clk clk
D Q
clk
D
Q (latch)
Q (flop)
D
F
l
o
p
L
a
t
c
h
Q
clk clk
D Q
clk
D
Q (latch)
Q (flop)
Latch Design
Pass Transistor Latch
Pros
+ Tiny
+ Low clock load
Cons
V
t
drop
nonrestoring
backdriving
output noise sensitivity
dynamic
diffusion input
D Q

Used in 1970s
Latch Design
Transmission gate
+ No V
t
drop
- Requires inverted clock
D Q

Latch Design
Inverting buffer
+ Restoring
+ No backdriving
+ Fixes either
Output noise sensitivity
Or diffusion input
Inverted output
D

X
Q
D Q

Latch Design
Tristate feedback
+ Static
Backdriving risk
Static latches are now essential
because of leakage

Q D
X
Latch Design
Buffered input
+ Fixes diffusion input
+ Noninverting

Q D
X

Latch Design
Buffered output
+ No backdriving
Widely used in standard cells
+ Very robust (most important)
- Rather large
- Rather slow (1.5 2 FO4 delays)
- High clock loading

Q
D
X

Latch Design
Datapath latch
+ smaller
+ faster
- unbuffered input

Q
D
X
Flip-Flop Design
Flip-flop is built as pair of back-to-back
latches
D Q

X
D

X
Q
Q

Enable
Enable: ignore clock when en = 0
Mux: increase latch D-Q delay
Clock Gating: increase en setup time, skew
D Q
L
a
t
c
h
D Q
en
en

L
a
t
c
h
D
Q

0
1
en
L
a
t
c
h
D Q
en
D
Q

0
1
en
D Q
en
F
l
o
p
F
l
o
p
F
l
o
p
Symbol Multiplexer Design Clock Gating Design
Reset
Force output low when reset asserted
Synchronous vs. asynchronous
D

Q
Q

reset
D

D
reset

D
reset
reset

reset
S
y
n
c
h
r
o
n
o
u
s

R
e
s
e
t
A
s
y
n
c
h
r
o
n
o
u
s

R
e
s
e
t
S
y
m
b
o
lF
l
o
p
D Q
L
a
t
c
h
D Q
reset reset

Q
reset
Set / Reset
Set forces output high when enabled
Flip-flop with asynchronous set and reset
D

reset
set
reset
set

You might also like