A Designers Guide to

Instrumentation Amplifiers
2
ND
Edition

i
A DESIGNERS GUIDE TO
INSTRUMENTATION AMPLIFIERS
by
Charles Kitchin and Lew Counts
2
ND
Edition
ii
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Specifcations and prices are subject to change without notice.
2004 Analog Devices, Inc. Printed in U.S.A.
G02678159/04(A)
iii
TABLE OF CONTENTS
CHAPTER IIN-AMP BASICS ................................................................................................... 1-1
INTRODUCTION ........................................................................................................................... 1-1
IN-AMPS vs. OP AMPS: WHAT ARE THE DIFFERENCES? ........................................................... 1-1
Signal Amplifcation and Common-Mode Rejection ........................................................................ 1-1
Common-Mode Rejection: Op Amp vs. In-Amp .............................................................................. 1-3
DIFFERENCE AMPLIFIERS ............................................................................................................ 1-5
WHERE ARE IN-AMPS AND DIFFERENCE AMPS USED? .......................................................... 1-5
Data Acquisition ............................................................................................................................ 1-5
Medical Instrumentation ................................................................................................................ 1-6
Monitor and Control Electronics .................................................................................................... 1-6
Software Programmable Applications .............................................................................................. 1-6
Audio Applications ......................................................................................................................... 1-6
High Speed Signal Conditioning ..................................................................................................... 1-6
Video Applications ......................................................................................................................... 1-6
Power Control Applications ............................................................................................................ 1-6
IN-AMPS: AN EXTERNAL VIEW ................................................................................................... 1-6
WHAT OTHER PROPERTIES DEFINE A HIGH QUALITY IN-AMP? .......................................... 1-7
High AC (and DC) Common-Mode Rejection ................................................................................ 1-7
Low Offset Voltage and Offset Voltage Drift ..................................................................................... 1-7
A Matched, High Input Impedance ................................................................................................. 1-8
Low Input Bias and Offset Current Errors ....................................................................................... 1-8
Low Noise ..................................................................................................................................... 1-8
Low Nonlinearity ........................................................................................................................... 1-8
Simple Gain Selection .................................................................................................................... 1-8
Adequate Bandwidth ...................................................................................................................... 1-8
Differential to Single-Ended Conversion ......................................................................................... 1-9
Rail-to-Rail Input and Output Swing .............................................................................................. 1-9
Power vs. Bandwidth, Slew Rate, and Noise .................................................................................... 1-9
CHAPTER IIINSIDE AN INSTRUMENTATION AMPLIFIER ............................................... 2-1
A Simple Op Amp Subtractor Provides an In-Amp Function ........................................................... 2-1
Improving the Simple Subtractor with Input Buffering .................................................................... 2-1
The 3-Op Amp In-Amp .................................................................................................................. 2-2
3-Op Amp In-Amp Design Considerations ...................................................................................... 2-3
The Basic 2-Op Amp Instrumentation Amplifer .............................................................................. 2-4
2-Op Amp In-AmpsCommon-Mode Design Considerations for Single-Supply Operation .................... 2-5
Auto-Zeroing Instrumentation Amplifers ........................................................................................ 2-6
CHAPTER IIIMONOLITHIC INSTRUMENTATION AMPLIFIERS ..................................... 3-1
Advantages Over Op Amp In-Amps ................................................................................................ 3-1
Which to Usean In-Amp or a Diff Amp? ...................................................................................... 3-1
MONOLITHIC IN-AMP DESIGNTHE INSIDE STORY ............................................................ 3-2
High Performance In-Amps ............................................................................................................ 3-2
Fixed Gain In-Amps ...................................................................................................................... 3-7
Low Cost In-Amps ........................................................................................................................ 3-8
Monolithic In-Amps Optimized for Single-Supply Operation ........................................................... 3-8
Low Power, Single-Supply In-Amps .............................................................................................. 3-11
iv
CHAPTER IVMONOLITHIC DIFFERENCE AMPLIFIERS .................................................. 4-1
Difference (Subtractor) Amplifer Products ..................................................................................... 4-1
High Frequency Differential Receiver/Amplifers ............................................................................. 4-6
CHAPTER VAPPLYING IN-AMPS EFFECTIVELY ................................................................ 5-1
Dual-Supply Operation .................................................................................................................. 5-1
Single-Supply Operation ................................................................................................................ 5-1
Power Supply Bypassing, Decoupling, and Stability Issues ............................................................... 5-1
The Importance of an Input Ground Return ................................................................................... 5-1
AC Input Coupling ........................................................................................................................ 5-2
RC Component Matching .............................................................................................................. 5-2
CABLE TERMINATION ................................................................................................................. 5-3
INPUT PROTECTION BASICS FOR ADI IN-AMPS ..................................................................... 5-3
Input Protection from ESD and DC Overload ................................................................................. 5-3
Adding External Protection Diodes ................................................................................................. 5-5
ESD and Transient Overload Protection .......................................................................................... 5-5
DESIGN ISSUES AFFECTING DC ACCURACY .......................................................................... 5-6
Designing for the Lowest Possible Offset Voltage Drift ..................................................................... 5-6
Designing for the Lowest Possible Gain Drift .................................................................................. 5-6
Practical Solutions ......................................................................................................................... 5-7
Option 1: Use a Better Quality Gain Resistor .................................................................................. 5-7
Option 2: Use a Fixed-Gain In-Amp ............................................................................................... 5-7
RTI AND RTO ERRORS ................................................................................................................. 5-7
Offset Error ................................................................................................................................... 5-8
Noise Errors .................................................................................................................................. 5-8
REDUCING RFI RECTIFICATION ERRORS IN IN-AMP CIRCUITS .......................................... 5-8
Designing Practical RFI Filters ....................................................................................................... 5-8
Selecting RFI Input Filter Component Values Using a Cookbook Approach ................................... 5-10
Specifc Design Examples ............................................................................................................. 5-10
An RFI Circuit for AD620 Series In-Amps .................................................................................... 5-10
An RFI Circuit for Micropower In-Amps ....................................................................................... 5-11
An RFI Filter for the AD623 In-Amp ............................................................................................ 5-12
AD8225 RFI Filter Circuit ........................................................................................................... 5-12
Common-Mode Filters Using X2Y Capacitors .............................................................................. 5-13
Using Common-Mode RF Chokes for In-Amp RFI Filters ............................................................ 5-14
RFI TESTING ............................................................................................................................... 5-15
USING LOW-PASS FILTERING TO IMPROVE SIGNAL-TO-NOISE RATIO ............................. 5-15
EXTERNAL CMR AND SETTLING TIME ADJUSTMENTS ...................................................... 5-17
CHAPTER VIIN-AMP AND DIFF AMP APPLICATIONS CIRCUITS .................................. 6-1
Composite In-Amp Circuit Has Excellent High Frequency CMR .................................................... 6-1
STRAIN GAGE MEASUREMENT USING AN AC EXCITATION ................................................ 6-2
APPLICATIONS OF THE AD628 PRECISION GAIN BLOCK ...................................................... 6-3
Why Use a Gain Block IC? .............................................................................................................. 6-3
Standard Differential Input ADC Buffer Circuit with Single-Pole LP Filter ...................................... 6-4
Changing the Output Scale Factor .................................................................................................. 6-4
Using an External Resistor to Operate the AD628 at Gains Below 0.1 .............................................. 6-4
Differential Input Circuit with Two-Pole Low-Pass Filtering ............................................................ 6-5
Using the AD628 to Create Precision Gain Blocks .......................................................................... 6-6
Operating the AD628 as a +10 or 10 Precision Gain Block ............................................................ 6-6
Operating the AD628 at a Precision Gain of +11 ............................................................................. 6-7
Operating the AD628 at a Precision Gain of +1 ............................................................................... 6-8
Increased BW Gain Block of 9.91 Using Feedforward .................................................................... 6-8
v
CURRENT TRANSMITTER REJECTS GROUND NOISE ............................................................ 6-9
HIGH LEVEL ADC INTERFACE ................................................................................................. 6-10
A HIGH SPEED NONINVERTING SUMMING AMPLIFIER ..................................................... 6-11
HIGH VOLTAGE MONITOR ........................................................................................................ 6-13
HIGH COMMON-MODE REJECTION SINGLE- SUPPLY CIRCUIT ........................................ 6-13
PRECISION 48 V BUS MONITOR ................................................................................................ 6-15
HIGH-SIDE CURRENT SENSE WITH A LOW-SIDE SWITCH .................................................. 6-16
HIGH-SIDE CURRENT SENSE WITH A HIGH-SIDE SWITCH ................................................ 6-17
BRIDGE APPLICATIONS ............................................................................................................. 6-17
A Classic Bridge Circuit ............................................................................................................... 6-17
A Single-Supply Data Acquisition System...................................................................................... 6-18
A Low Dropout Bipolar Bridge Driver ........................................................................................... 6-18
TRANSDUCER INTERFACE APPLICATIONS ............................................................................ 6-19
MEDICAL EKG APPLICATIONS ................................................................................................. 6-19
REMOTE LOAD-SENSING TECHNIQUE ................................................................................... 6-21
A PRECISION VOLTAGE-TO-CURRENT CONVERTER............................................................. 6-22
A CURRENT SENSOR INTERFACE ........................................................................................... 6-22
OUTPUT BUFFERING LOW POWER IN-AMPS ......................................................................... 6-23
A 4 mA TO 20 mA SINGLE-SUPPLY RECEIVER.......................................................................... 6-23
A SINGLE-SUPPLY THERMOCOUPLE AMPLIFIER .................................................................. 6-24
SPECIALTY PRODUCTS.............................................................................................................. 6-24
CHAPTER VIIMATCHING IN-AMP CIRCUITS TO MODERN ADCs .................................. 7-1
Calculating ADC Requirements ...................................................................................................... 7-1
Matching ADI In-Amps with Some Popular ADCs .......................................................................... 7-2
High Speed Data Acquisition .......................................................................................................... 7-4
A High Speed In-Amp Circuit for Data Acquisition ......................................................................... 7-6
APPENDIX AINSTRUMENTATION AMPLIFIER SPECIFICATIONS ................................ A-1
(A) Specifcations (Conditions)...................................................................................................... A-3
(B) Common-Mode Rejection ...................................................................................................... A-3
(C) AC Common-Mode Rejection ................................................................................................ A-3
(D) Voltage Offset.......................................................................................................................... A-3
(E) Input Bias and Offset Currents ................................................................................................ A-4
(F) Operating Voltage Range ......................................................................................................... A-4
(G) Quiescent Supply Current ....................................................................................................... A-4
(H) Settling Time .......................................................................................................................... A-5
(I) Gain ...................................................................................................................................... A-5
(J) Gain Range ............................................................................................................................ A-5
(K) Gain Error .............................................................................................................................. A-5
(L) Nonlinearity............................................................................................................................ A-6
(M) Gain vs. Temperature............................................................................................................... A-6
(N) Key Specifcations for Single-Supply In-Amps .......................................................................... A-6
Input and Output Voltage Swing..................................................................................................... A-6
APPENDIX BDIFFERENCE AND INSTRUMENTATION AMPLIFIERS
SELECTION TABLE .................................................................................................................... B-1
Index .............................................................................................................................................. C-1
Device Index................................................................................................................................... D-1
vi
BIBLIOGRAPHY/FURTHER READING
Brokaw, Paul. An IC Amplifer Users Guide to Decoupling, Grounding, and Making Things Go Right for
a Change. Application Note AN-202. Analog Devices, Inc., 1990.
Jung, Walter. IC Op Amp Cookbook. 3rd ed. Prentice-Hall PTR, 1986, 1997, ISBN: 0-13-889601-1. This can
also be purchased on the Web at http://dogbert.abebooks.com.
Jung, Walter. Op Amp Applications Book. Analog Devices Amplifer Seminar. Code: OP-AMP-APPLIC-BOOK.
Call: (800) 262-5643 (US and Canadian customers only).
Kester, Walt. Practical Design Techniques for Sensor Signal Conditioning. Analog Devices, Inc., 1999, Section 10.
ISBN-0-916550-20-6. Available for download on the ADI website at www.analog.com.
Nash, Eamon. Errors and Error Budget Analysis in Instrumentation Amplifer Applications. Application
Note AN-539. Analog Devices, Inc.
Nash, Eamon. A Practical Review of Common-Mode and Instrumentation Amplifers. Sensors Magazine,
July 1998.
Sheingold, Dan, ed. Transducer Interface Handbook. Analog Devices, Inc. 1980, pp. 28-30.
Wurcer, Scott and Jung, Walter. Instrumentation Amplifers Solve Unusual Design Problems. Application
Note AN-245. Applications Reference Manual. Analog Devices, Inc.
ACKNOWLEDGMENTS
We gratefully acknowledge the support and assistance of the following: Moshe Gerstenhaber, Scott Wurcer,
Stephen Lee, Alasdair Alexander, Chau Tran, Chuck Whiting, Eamon Nash, Walt Kester, Alain Guery,
Nicola OByrne, James Staley, Bill Riedel, Scott Pavlik, Matt Gaug, David Kruh, Cheryl OConnor, and
Lynne Hulme of Analog Devices. Also to David Anthony of X2Y Technology and Steven Weir of Weir Design
Engineering, for the detailed applications information on applying X2Y products for RFI suppression.
And fnally, a special thank you to Analog Devices Communications Services team, including John Galgay,
Alex Wong, Deb Schopperle, and Paul Wasserboehr.
All brand or product names mentioned are trademarks or registered trademarks of their respective owners.
Purchase of licensed I
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I
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1-1
INTRODUCTION
Instrumentation amplifers (in-amps) are sometimes
misunderstood. Not all amplifers used in instrumenta-
tion applications are instrumentation amplifers, and by
no means are all in-amps used only in instrumentation
applications. In-amps are used in many applications,
from motor control to data acquisition to automotive.
The intent of this guide is to explain the fundamentals
of what an instrumentation amplifer is, how it operates,
and how and where to use it. In addition, several dif-
ferent categories of instrumentation amplifiers are
addressed in this guide.
IN-AMPS vs. OP AMPS: WHAT ARE THE
DIFFERENCES?
An instrumentation amplifer is a closed-loop gain
block that has a differential input and an output that
is single-ended with respect to a reference terminal.
Most commonly, the impedances of the two input
terminals are balanced and have high values, typically
10
9
U, or greater. The input bias currents should also
be low, typically 1 nA to 50 nA. As with op amps, output
impedance is very low, nominally only a few milliohms,
at low frequencies.
Unlike an op amp, for which closed-loop gain is de-
termined by external resistors connected between its
inverting input and its output, an in-amp employs an
internal feedback resistor network that is isolated from its
signal input terminals. With the input signal applied across
the two differential inputs, gain is either preset internally
or is user set (via pins) by an internal or external gain
resistor, which is also isolated from the signal inputs.
Figure 1-1 shows a bridge preamp circuit, a typical in-amp
application. When sensing a signal, the bridge resistor values
change, unbalancing the bridge and causing a change in
differential voltage across the bridge. The signal output
of the bridge is this differential voltage, which connects
directly to the in-amps inputs. In addition, a constant dc
voltage is also present on both lines. This dc voltage will
normally be equal or common mode on both input lines. In
its primary function, the in-amp will normally reject the
common-mode dc voltage, or any other voltage common
to both lines, while amplifying the differential signal voltage,
the difference in voltage between the two lines.
Chapter I
IN-AMP BASICS

Figure 1-1. AD8221 Bridge Circuit
In contrast, if a standard op amp amplifer circuit were
used in this application, it would simply amplify both the
signal voltage and any dc, noise, or other common-mode
voltages. As a result, the signal would remain buried
under the dc offset and noise. Because of this, even the
best op amps are far less effective in extracting weak
signals. Figure 1-2 contrasts the differences between op
amp and in-amp input characteristics.
Signal Amplifcation and Common-Mode Rejection
An instrumentation amplifer is a device that amplifes
the difference between two input signal voltages while
rejecting any signals that are common to both inputs. The
in-amp, therefore, provides the very important function
of extracting small signals from transducers and other
signal sources.
Common-mode rejection (CMR), the property of
canceling out any signals that are common (the same
potential on both inputs), while amplifying any signals
that are differential (a potential difference between the
inputs), is the most important function an instrumenta-
tion amplifer provides. Both dc and ac common-mode
rejection are important in-amp specifcations. Any errors
due to dc common-mode voltage (i.e., dc voltage present
at both inputs) will be reduced 80 dB to 120 dB by any
modern in-amp of decent quality.
However, inadequate ac CMR causes a large, time-
varying error that often changes greatly with frequency,
and therefore, is diffcult to remove at the IAs output.
Fortunately, most modern monolithic IC in-amps provide
excellent ac and dc common-mode rejection.
1-2
Common-mode gain (A
CM
), the ratio of change in
output voltage to change in common-mode input volt-
age, is related to common-mode rejection. It is the net
gain (or attenuation) from input to output for voltages
common to both inputs. For example, an in-amp with
a common-mode gain of 1/1,000 and a 10 V common-
mode voltage at its inputs will exhibit a 10 mV output
change. The differential or normal mode gain (A
D
) is
the gain between input and output for voltages applied
differentially (or across) the two inputs. The common-
mode rejection ratio (CMRR) is simply the ratio of
the differential gain, A
D
, to the common-mode gain.
Note that in an ideal in-amp, CMRR will increase in
proportion to gain.
Common-mode rejection is usually specifed for full
range common-mode voltage (CMV) change at a given
frequency and a specifed imbalance of source impedance
(e.g., 1 kU source imbalance, at 60 Hz).

Figure 1-2. Op Amp vs. In-Amp Input Characteristics
Mathematically, common-mode rejection can be rep-
resented as
CMRR A
V
V
D
CM
OUT
=

where
A
D
is the differential gain of the amplifer.
V
CM
is the common-mode voltage present at the
amplifer inputs.
V
OUT
is the output voltage present when a common-mode
input signal is applied to the amplifer.
The term CMR is a logarithmic expression of the com-
mon-mode rejection ratio (CMRR). That is, CMR =
20 Log
10
CMRR.
To be effective, an in-amp needs to be able to amplify
microvolt-level signals while rejecting common-mode
voltage at its inputs. It is particularly important for the
in-amp to be able to reject common-mode signals over the
bandwidth of interest. This requires that instrumenta-
tion amplifers have very high common-mode rejection
over the main frequency of interest and its harmonics.
1-3
For techniques on reducing errors due to out-of-band
signals that may appear as a dc output offset, please refer
to the RFI section of this guide.
At unity gain, typical dc values of CMR are 70 dB to more
than 100 dB, with CMR usually improving at higher gains.
While it is true that operational amplifers connected as
subtractors also provide common-mode rejection, the
user must provide closely matched external resistors
(to provide adequate CMRR). On the other hand,
monolithic in-amps, with their pretrimmed resistor
networks, are far easier to apply.
Common-Mode Rejection: Op Amp vs. In-Amp
Op amps, in-amps, and difference amps all provide
common-mode rejection. However, in-amps and diff
amps are designed to reject common-mode signals so that
they do not appear at the amplifers output. In contrast,
an op amp operated in the typical inverting or noninvert-
ing amplifer confguration will process common-mode
signals, passing them through to the output, but will not
normally reject them.
Figure 1-3a shows an op amp connected to an input
source that is riding on a common-mode voltage. Because
of feedback applied externally between the output and
the summing junction, the voltage on the input is
forced to be the same as that on the + input voltage.
Therefore, the op amp ideally will have zero volts across
its input terminals. As a result, the voltage at the op amp
output must equal V
CM
, for zero volts differential input.
Even though the op amp has common-mode rejection, the
common-mode voltage is transferred to the output along
with the signal. In practice, the signal is amplifed by
the op amps closed-loop gain while the common-mode
voltage receives only unity gain. This difference in gain
does provide some reduction in common-mode voltage
as a percentage of signal voltage. However, the common-
mode voltage still appears at the output and its presence
reduces the amplifers available output swing. For many
reasons, any common-mode signal (dc or ac) appearing
at the op amps output is highly undesirable.
V
OUT
V = V
CM
V+ = V
CM
V
CM
R2
R1
ZEROV V
IN
V
CM
V
OUT
= (V
IN
GAIN) V
CM
GAIN = R2/R1
CM GAIN = 1
Figure 1-3a. In a typical inverting or noninverting amplifer circuit using an op amp,
both the signal voltage and the common-mode voltage appear at the amplifer output.
1-4
Figure 1-3b shows a 3-op amp in-amp operating under
the same conditions. Note that, just like the op amp
circuit, the input buffer amplifers of the in-amp pass the
common-mode signal through at unity gain. In contrast,
the signal is amplifed by both buffers. The output signals
from the two buffers connect to the subtractor section of
the IA. Here the differential signal is amplifed (typically
at low gain or unity) while the common-mode voltage is
attenuated (typically by 10,000:1 or more). Contrasting
the two circuits, both provide signal amplifcation (and
buffering), but because of its subtractor section, the in-
amp rejects the common-mode voltage.
Figure 1-3c is an in-amp bridge circuit. The in-amp
effectively rejects the dc common-mode voltage
appearing at the two bridge outputs, while amplifying
the very weak bridge signal voltage. In addition, many
modern in-amps provide a common-mode rejection
approaching 80 dB, which allows powering the bridge
from an inexpensive, nonregulated dc power supply. In
contrast, a self constructed in-amp, using op amps and
0.1% resistors, typically only achieves 48 dB CMR, thus
requiring a regulated dc supply for bridge power.
V
OUT
V
CM
= 0
SUBTRACTOR
V
OUT
= V
IN
(GAIN)
V
CM
V
CM
V
CM
V
CM
V
IN
TIMES
GAIN
R
G
BUFFER
BUFFER
3-OP AMP
IN-AMP
V
IN
V
CM
Figure 1-3b. As with the op amp circuit above, the input buffers of an in-amp circuit
amplify the signal voltage while the common-mode voltage receives unity gain. How-
ever, the common-mode voltage is then rejected by the in-amps subtractor section.
V
OUT
V
CM
V
CM
V
IN
BRIDGE
SENSOR
V
SUPPLY
INTERNAL OR EXTERNAL
GAIN RESISTOR
IN-AMP
Figure 1-3c. An in-amp used in a bridge circuit. Here the dc common-mode
voltage can easily be a large percentage of the supply voltage.
1-5
Figure 1-3d shows a difference (subtractor) amplifer
being used to monitor the voltage of an individual cell
which is part of a battery bank. Here the common-mode
dc voltage can easily be much higher than the amplifers
supply voltage. Some monolithic difference amplifers,
such as the AD629, can operate with common-mode
voltages as high as 270 V.
DIFFERENCE AMPLIFIERS
Figure 1-4 is a block diagram of a difference amplifer.
This type of IC is a special purpose in-amp that normally
consists of a subtractor amplifer followed by an output
buffer, which may also be a gain stage. The four resistors
used in the subtractor are normally internal to the IC,
and therefore, are closely matched for high CMR.
Many difference amplifers are designed to be used in
applications where the common-mode and signal voltages
may easily exceed the supply voltage. These diff amps
typically use very high value input resistors to attenuate
both signal and common-mode input voltages.
WHERE ARE IN-AMPS AND DIFFERENCE
AMPS USED?
Data Acquisition
In-amps fnd their primary use amplifying signals from
low level output transducers in noisy environments. The
amplifcation of pressure or temperature transducer
signals is a common in-amp application. Common bridge
applications include strain and weight measurement using
load cells and temperature measurement using resistive
temperature detectors, or RTDs.
V
OUT
380k
380k
380k
380k
V
CM
V
CM
DIFFERENCE AMPLIFIER
V
IN
Figure 1-3d. A difference amp is especially useful in applications such as battery
cell measurement where the dc (or ac) common-mode voltage may be greater
than the supply voltage.

Figure 1-4. A Difference Amplifer IC

1-6
Medical Instrumentation
In-amps are widely used in medical equipment such as
EKG and EEG monitors, blood pressure monitors, and
defbrillators.
Monitor and Control Electronics
Diff amps may be used to monitor voltage or current in
a system and then trigger alarm systems when nominal
operating levels are exceeded. Because of their ability to
reject high common-mode voltages, diff amps are often
used in these applications.
Software Programmable Applications
An in-amp may be used with a software programmable
resistor chip to allow software control of hardware
systems.
Audio Applications
Because of their high common-mode rejection,
instrumentation amplifers are sometimes used for audio
applications (as microphone preamps, for example), to
extract a weak signal from a noisy environment, and to
minimize offsets and noise due to ground loops. Refer
to Table 6-4, (page 6-24) Specialty Products Available
from Analog Devices.
High Speed Signal Conditioning
Because the speed and accuracy of modern video data
acquisition systems have improved, there is now a
growing need for high bandwidth instrumentation ampli-
fers, particularly in the feld of CCD imaging equipment
where offset correction and input buffering are required.
Double-correlated sampling techniques are often used
in this area for offset correction of the CCD image. Two
sample-and-hold amplifers monitor the pixel and reference
levels, and a dc-corrected output is provided by feeding
their signals into an instrumentation amplifer.
Video Applications
High speed in-amps may be used in many video and cable
RF systems to amplify or process high frequency signals.
Power Control Applications
In-amps can also be used for motor monitoring (to
monitor and control motor speed, torque, etc.) by mea-
suring the voltages, currents, and phase relationships
of a 3-phase ac-phase motor. Diff amps are used in
applications where the input signal exceeds the
supply voltages.
IN-AMPS: AN EXTERNAL VIEW
Figure 1-5 provides a functional block diagram of an
instrumentation amplifer.

Figure 1-5. Differential vs. Common-Mode Input Signals

1-7
Since an ideal instrumentation amplifer detects only the
difference in voltage between its inputs, any common-
mode signals (equal potentials for both inputs), such as
noise or voltage drops in ground lines, are rejected at the
input stage without being amplifed.
Either internal or external resistors may be used to set
the gain. Internal resistors are the most accurate and
provide the lowest gain drift over temperature.
One common approach is to use a single external resistor,
working with two internal resistors, to set the gain. The
user can calculate the required value of resistance for a
given gain, using the gain equation listed in the in-amps
spec sheet. This permits gain to be set anywhere within a
very large range. However, the external resistor can seldom
be exactly the correct value for the desired gain, and it
will always be at a slightly different temperature than the
ICs internal resistors. These practical limitations always
contribute additional gain error and gain drift.
Sometimes two external resistors are employed. In general,
a 2-resistor solution will have lower drift than a single
resistor as the ratio of the two resistors sets the gain, and
these resistors can be within a single IC array for close
matching and very similar temperature coeffcient (TC).
Conversely, a single external resistor will always be a TC
mismatch for an on-chip resistor.
The output of an instrumentation amplifer often has
its own reference terminal, which, among other uses,
allows the in-amp to drive a load that may be at a
distant location.
Figure 1-5 shows the input and output commons being
returned to the same potential, in this case to power
supply ground. This star ground connection is a very ef-
fective means of minimizing ground loops in the circuit;
however, some residual common-mode ground currents
will still remain. These currents fowing through R
CM

will develop a common-mode voltage error, V
CM
. The
in-amp, by virtue of its high common-mode rejection,
will amplify the differential signal while rejecting V
CM

and any common-mode noise.
Of course, power must be supplied to the in-amp. As
with op amps, the power would normally be provided
by a dual-supply voltage that operates the in-amp over
a specifed range. Alternatively, an in-amp specifed for
single-supply (rail-to-rail) operation may be used.
An instrumentation amplifer may be assembled using one
or more operational amplifers, or it may be of monolithic
construction. Both technologies have their advantages
and limitations.
In general, discrete (op amp) in-amps offer design fex-
ibility at low cost and can sometimes provide performance
unattainable with monolithic designs, such as very high
bandwidth. In contrast, monolithic designs provide
complete in-amp functionality and are fully specifed
and usually factory trimmed, often to higher dc precision
than discrete designs. Monolithic in-amps are also much
smaller, lower in cost, and easier to apply.
WHAT OTHER PROPERTIES DEFINE A HIGH
QUALITY IN-AMP?
Possessing a high common-mode rejection ratio, an
instrumentation amplifer requires the properties
described below.
High AC (and DC) Common-Mode Rejection
At a minimum, an in-amps CMR should be high over
the range of input frequencies that need to be rejected.
This includes high CMR at power line frequencies and
at the second harmonic of the power line frequency.
Low Offset Voltage and Offset Voltage Drift
As with an operational amplifer, an in-amp must have
low offset voltage. Since an instrumentation amplifer
consists of two independent sections, an input stage and
an output amplifer, total output offset will equal the sum
of the gain times the input offset plus the offset of the
output amplifer (within the in-amp). Typical values for
input and output offset drift are 1 V/`C and 10 V/`C,
respectively. Although the initial offset voltage may be
nulled with external trimming, offset voltage drift cannot
be adjusted out. As with initial offset, offset drift has two
components, with the input and output section of the
in-amp each contributing its portion of error to the total.
As gain is increased, the offset drift of the input stage
becomes the dominant source of offset error.
1-8
A Matched, High Input Impedance
The impedances of the inverting and noninverting input
terminals of an in-amp must be high and closely matched
to one another. High input impedance is necessary to
avoid loading down the input signal source, which could
also lower the input signal voltage.
Values of input impedance from 10
9
U to 10
12
U are
typical. Difference amplifers, such as the AD629, have
lower input impedances but can be very effective in high
common-mode voltage applications.
Low Input Bias and Offset Current Errors
Again, as with an op amp, an instrumentation ampli-
fer has bias currents that fow into, or out of, its input
terminals; bipolar in-amps have base currents and FET
amplifers have gate leakage currents. This bias current
fowing through an imbalance in the signal source
resistance will create an offset error. Note that if the
input source resistance becomes infnite, as with ac
(capacitive) input coupling without a resistive return to
power supply ground, the input common-mode voltage
will climb until the amplifer saturates. A high value
resistor connected between each input and ground is
normally used to prevent this problem. Typically, the
input bias current multiplied by the resistors value in
ohms should be less than 10 mV (see Chapter V). Input
offset current errors are defned as the mismatch between
the bias currents fowing into the two inputs. Typical
values of input bias current for a bipolar in-amp range
from 1 nA to 50 nA; for a FET input device, values of
1 pA to 50 pA are typical at room temperature.
Low Noise
Because it must be able to handle very low level input
voltages, an in-amp must not add its own noise to that of
the signal. A minimum input noise level of 10 nV/Hz @
1 kHz and (Gain > 100) referred to input (RTI) is desir-
able. Micropower in-amps are optimized for the lowest
possible input stage current and, therefore, typically have
higher noise levels than their higher current cousins.
Low Nonlinearity
Input offset and scale factor errors can be corrected by
external trimming, but nonlinearity is an inherent perfor-
mance limitation of the device and cannot be removed by
external adjustment. Low nonlinearity must be designed
in by the manufacturer. Nonlinearity is normally specifed
as a percentage of full scale, whereas the manufacturer
measures the in-amps error at the plus and minus full-
scale voltage and at zero. A nonlinearity error of 0.01%
is typical for a high quality in-amp; some devices have
levels as low as 0.0001%.
Simple Gain Selection
Gain selection should be easy. The use of a single external
gain resistor is common, but an external resistor will
affect the circuits accuracy and gain drift with tempera-
ture. In-amps, such as the AD621, provide a choice of
internally preset gains that are pin selectable, with very
low gain TC.
Adequate Bandwidth
An instrumentation amplifer must provide bandwidth
suffcient for the particular application. Since typical unity
gain small-signal bandwidths fall between 500 kHz and
4 MHz, performance at low gains is easily achieved, but at
higher gains bandwidth becomes much more of an issue.
Micropower in-amps typically have lower bandwidth than
comparable standard in-amps, as micropower input stages
are operated at much lower current levels.
1-9
Differential to Single-Ended Conversion
Differential to single-ended conversion is, of course, an
integral part of an in-amps function: a differential input
voltage is amplifed and a buffered, single-ended output
voltage is provided. There are many in-amp applications
which require amplifying a differential voltage that is
riding on top of a much larger common-mode voltage.
This common-mode voltage may be noise, or ADC offset,
or both. The use of an op amp rather than an in-amp
would simply amplify both the common mode and the
signal by equal amounts. The great beneft provided by
an in-amp is that it selectively amplifes the (differential)
signal while rejecting the common-mode signal.
Rail-to-Rail Input and Output Swing
Modern in-amps often need to operate on single-supply
voltages of 5 V or less. In many of these applications, a
rail-to-rail input ADC is often used. So called rail-to-rail
operation means that an amplifers maximum input or
output swing is essentially equal to the power supply
voltage. In fact, the input swing can sometimes exceed
the supply voltage slightly, while the output swing is often
within 100 mV of the supply voltage or ground. Careful
attention to the data sheet specifcations is advised.
Power vs. Bandwidth, Slew Rate, and Noise
As a general rule, the higher the operating current of
the in-amps input section, the greater the bandwidth
and slew rate and the lower the noise. But higher operating
current means higher power dissipation and heat. Battery-
operated equipment needs to use low power devices,
and densely packed printed circuit boards must be
able to dissipate the collective heat of all their active
components. Device heating also increases offset drift
and other temperature-related errors. IC designers of-
ten must trade off some specifcations to keep power
dissipation and drift to acceptable levels.
2-1
Chapter II
INSIDE AN INSTRUMENTATION AMPLIFIER
A Simple Op Amp Subtractor Provides an
In-Amp Function
The simplest (but still very useful) method of implement-
ing a differential gain block is shown in Figure 2-1.

Figure 2-1. A 1-Op Amp In-Amp Difference
Amplifer Circuit Functional Block Diagram
If R1 = R3 and R2 = R4, then
V V V R2 R1
OUT IN2 IN1
=
( )( )
Although this circuit provides an in-amp function, am-
plifying differential signals while rejecting those that are
common mode, it also has some limitations. First, the
impedances of the inverting and noninverting inputs are
relatively low and unequal. In this example, the input im-
pedance to V
IN1
equals 100 kU, while the impedance of
V
IN2
is twice that, at 200 kU. Therefore, when voltage is
applied to one input while grounding the other, different
currents will fow depending on which input receives
the applied voltage. (This unbalance in the sources
resistances will degrade the circuits CMRR.)
Furthermore, this circuit requires a very close ratio match
between resistor pairs R1/R2 and R3/R4; otherwise, the
gain from each input would be differentdirectly affect-
ing common-mode rejection. For example, at a gain of
1, with all resistors of equal value, a 0.1% mismatch in
just one of the resistors will degrade the CMR to a level
of 66 dB (1 part in 2,000). Similarly, a source resistance
imbalance of 100 U will degrade CMR by 6 dB.
In spite of these problems, this type of bare bones in-amp
circuit, often called a difference amplifer or subtractor,
is useful as a building block within higher performance
in-amps. It is also very practical as a standalone func-
tional circuit in video and other high speed uses, or in
low frequency, high common-mode voltage (CMV)
applications, where the input resistors divide down the
input voltage as well as provide input protection for the
amplifer. Some monolithic difference amplifers such
as Analog Devices AD629 employ a variation of the
simple subtractor in their design. This allows the IC to
handle common-mode input voltages higher than its
own supply voltage. For example, when powered from
a 15 V supply, the AD629 can amplify signals with
common-mode voltages as high as 270 V.
Improving the Simple Subtractor with
Input Buffering
An obvious way to signifcantly improve performance is
to add high input impedance buffer amplifers ahead of
the simple subtractor circuit, as shown in the 3-op amp
instrumentation amplifer circuit of Figure 2-2.

Figure 2-2. A Subtractor Circuit with Input Buffering
2-2
This circuit provides matched, high impedance inputs
so that the impedances of the input sources will have a
minimal effect on the circuits common-mode rejection.
The use of a dual op amp for the 2-input buffer amplif-
ers is preferred because they will better track each other
over temperature and save board space. Although the
resistance values are different, this circuit has the same
transfer function as the circuit of Figure 2-3.
Figure 2-3 shows further improvement: now the input
buffers are operating with gain, which provides a circuit
with more fexibility. If the value of R5 = R8 and R6 =
R7 and, as before, R1 = R3 and R2 = R4, then
V
OUT
= (V
IN2
V
IN1
) (1 + R5/R6) (R2/R1)
While the circuit of Figure 2-3 does increase the gain (of
A
1
and A
2
) equally for differential signals, it also increases
the gain for common-mode signals.
The 3-Op Amp In-Amp
The circuit of Figure 2-4 provides further refnement
and has become the most popular confguration for
instrumentation amplifer design. The classic 3-op amp
in-amp circuit is a clever modifcation of the buffered
subtractor circuit of Figure 2-3. As with the previous
circuit, op amps A1 and A2 of Figure 2-4 buffer the
input voltage. However, in this confguration, a single
gain resistor, R
G
, is connected between the summing
junctions of the two input buffers, replacing R6 and R7.
The full differential input voltage will now appear across
R
G
(because the voltage at the summing junction of each
amplifer is equal to the voltage applied to its positive
input). Since the amplifed input voltage (at the outputs
of A1 and A2) appears differentially across the three
resistors R5, R
G
, and R6, the differential gain may be
varied by just changing R
G
.

Figure 2-3. A Buffered Subtractor Circuit with Buffer Amplifers Operating with Gain

Figure 2-4. The Classic 3-Op Amp In-Amp Circuit
2-3
There is another advantage of this connection: once the
subtractor circuit has been set up with its ratio-matched
resistors, no further resistor matching is required when
changing gains. If the value of R5 = R6, R1 = R3, and
R2 = R4, then
V
OUT
= (V
IN2
V
IN1
) (1 + 2R5/R
G
)(R2/R1)
Since the voltage across R
G
equals V
IN
, the current
through R
G
will equal (V
IN
/R
G
). Amplifers A1 and A2,
therefore, will operate with gain and amplify the input
signal. Note, however, that if a common-mode voltage
is applied to the amplifer inputs, the voltages on each
side of R
G
will be equal and no current will fow through
this resistor. Since no current fows through R
G
(nor,
therefore, through R5 and R6), amplifers A1 and A2
will operate as unity gain followers. Therefore, common-
mode signals will be passed through the input buffers at
unity gain, but differential voltages will be amplifed by
the factor (1 + (2 R
F
/R
G
)).
In theory, this means that the user may take as much
gain in the front end as desired (as determined by R
G
)
without increasing the common-mode gain and error.
That is, the differential signal will be increased by
gain, but the common-mode error will not, so the ratio
(Gain (V
DIFF
)/(V
ERROR CM
)) will increase. Thus, CMRR
will theoretically increase in direct proportion to gaina
very useful property.
Finally, because of the symmetry of this confguration,
common-mode errors in the input amplifers, if they track,
tend to be canceled out by the output stage subtractor.
This includes such errors as common-mode rejection
vs. frequency. These features explain the popularity of
this confguration.
3-Op Amp In-Amp Design Considerations
Two alternatives are available for constructing 3-op amp
instrumentation amplifers: using FET or bipolar input
operational amplifers. FET input op amps have very low
bias currents and are generally well suited for use with
very high (>10
6
U) source impedances. FET amplifers
usually have lower CMR, higher offset voltage, and higher
offset drift than bipolar amplifers. They also may provide
a higher slew rate for a given amount of power.
The sense and reference terminals (Figure 2-4) permit
the user to change A3s feedback and ground connec-
tions. The sense pin may be externally driven for servo
applications and others for which the gain of A3 needs
to be varied. Likewise, the reference terminal allows an
external offset voltage to be applied to A3. For normal
operation, the sense and output terminals are tied
together, as are reference and ground.
Amplifers with bipolar input stages tend to achieve both
higher CMR and lower input offset voltage drift than FET
input amplifers. Super beta bipolar input stages combine
many of the benefts of FET and bipolar processes, with
even lower IB drift than FET devices.
A common (but frequently overlooked) pitfall for the
unwary designer using a 3-op amp in-amp design is the
reduction of common-mode voltage range that occurs
when the in-amp is operating at high gain. Figure 2-5
is a schematic of a 3-op amp in-amp operating at a gain
of 1,000.
In this example the input amplifers, A1 and A2, are
operating at a gain of 1,000, while the output amplifer
is providing unity gain. This means that the voltage at
the output of each input amplifer will equal one-half

Figure 2-5. A 3-Op Amp In-Amp Showing Reduced CMV Range
2-4
the peak-to-peak input voltage 1,000, plus any
common-mode voltage that is present on the inputs
(the common-mode voltage will pass through at unity
gain regardless of the differential gain). Therefore, if
a 10 mV differential signal is applied to the amplifer
inputs, amplifer A1s output will equal +5 V, plus the
common-mode voltage, and A2s output will be 5 V,
plus the common-mode voltage. If the amplifers are
operating from 15 V supplies, they will usually have
7 V or so of headroom left, thus permitting an 8 V
common-mode voltagebut not the full 12 V of CMV
which, typically, would be available at unity gain (for a
10 mV input). Higher gains or lower supply voltages will
further reduce the common-mode voltage range.
The Basic 2-Op Amp Instrumentation Amplifer
Figure 2-6 is a schematic of a typical 2-op amp in-amp
circuit. It has the obvious advantage of requiring only two,
rather than three, operational amplifers and providing
savings in cost and power consumption. However, the
nonsymmetrical topology of the 2-op amp in-amp circuit
can lead to several disadvantages, most notably lower ac
CMRR, compared to the 3-op amp design, limiting the
circuits usefulness.
The transfer function of this circuit is
V
OUT
= (V
IN2
V
IN1
) (1 + R4/R3)
for R1 = R4 and R2 = R3
Input resistance is high and balanced, thus permitting the
signal source to have an unbalanced output impedance.
The circuits input bias currents are set by the input
current requirements of the noninverting input of the
two op amps, which typically are very low.
Disadvantages of this circuit include the inability to oper-
ate at unity gain, a decreased common-mode voltage range
as circuit gain is lowered, and poor ac common-mode
rejection. The poor CMR is due to the unequal phase
shift occurring in the two inputs, V
IN1
and V
IN2
. That is,
the signal must travel through amplifer A1 before it is
subtracted from V
IN2
by amplifer A2. Thus, the voltage
at the output of A1 is slightly delayed or phase-shifted
with respect to V
IN1
.
Minimum circuit gains of 5 are commonly used with
the 2-op amp in-amp circuit because this permits an ad-
equate dc common-mode input range, as well as suffcient
bandwidth for most applications. The use of rail-to-rail
(single-supply) amplifers will provide a common-mode
voltage range that extends down to V
S
(or ground in
single-supply operation), plus true rail-to-rail output volt-
age range (i.e., an output swing from +V
S
to V
S
).
Table 2-1 shows amplifer gain vs. circuit gain for the
circuit of Figure 2-6 and gives practical 1% resistor values
for several common circuit gains.
Table 2-1. Operating Gains of Amplifers A1
and A2 and Practical 1% Resistor Values for the
Circuit of Figure 2-6
Circuit Gain Gain
Gain of A1 of A2 R2, R3 R1, R4
1.10 11.00 1.10 499 kU 49.9 kU
1.33 4.01 1.33 150 kU 49.9 kU
1.50 3.00 1.50 100 kU 49.9 kU
2.00 2.00 2.00 49.9 kU 49.9 kU
10.1 1.11 10.10 5.49 kU 49.9 kU
101.0 1.01 101.0 499 U 49.9 kU
1001 1.001 1001 49.9 U 49.9 kU

Figure 2-6. A 2-Op Amp In-Amp Circuit
2-5
2-Op Amp In-AmpsCommon-Mode Design
Considerations for Single-Supply Operation
When the 2-op amp in-amp circuit of Figure 2-7 is
examined from the reference input, it is apparent that it
is simply a cascade of two inverters.
Assuming that the voltage at both of the signal inputs,
V
IN1
and V
IN2
, is 0, the output of A1 will equal
V
O1
= V
REF
(R2/R1)
A positive voltage applied to V
REF
will tend to drive the
output voltage of A1 negative, which is clearly not possible
if the amplifer is operating from a single power supply
voltage (+V
S
and 0 V).
The gain from the output of amplifer A1 to the circuits
output, V
OUT
, at A2, is equal to
V
OUT
= V
O1
(R4/R3)
The gain from V
REF
to V
OUT
is the product of these two
gains and equals
V
OUT
= (V
REF
(R2/R3))(R4/R3)
In this case, R1 = R4 and R2 = R3. Therefore, the
reference gain is +1, as expected. Note that this is the
result of two inversions, in contrast to the noninverting
signal path of the reference input in a typical 3-op amp
in-amp circuit.
Just as with the 3-op amp in-amp, the common-mode
voltage range of the 2-op amp in-amp can be limited
by single-supply operation and by the choice of
reference voltage.
Figure 2-8 is a schematic of a 2-op amp in-amp operating
from a single 5 V power supply. The reference input is
tied to V
S
/2 which, in this case, is 2.5 V. The output
voltage should ideally be 2.5 V for a differential input
voltage of 0 V and for any common-mode voltage within
the power supply voltage range (0 V to 5 V).
As the common-mode voltage is increased from 2.5 V
toward 5 V, the output voltage of A1 (V
O1
) will equal
V
O1
= V
CM
+ ((V
CM
V
REF
) (R2/R1))
In this case, V
REF
= 2.5 V and R2/R1 = 1/4. The output
voltage of A1 will reach 5 V when V
CM
= 4.5 V. Further
increases in common-mode voltage obviously cannot be
rejected. In practice, the input voltage range limitations
of amplifers A1 and A2 may limit the in-amps common-
mode voltage range to less than 4.5 V.
Similarly, as the common-mode voltage is reduced from
2.5 V toward 0 V, the output voltage of A1 will hit zero
for a V
CM
of 0.5 V. Clearly, the output of A1 cannot go
more negative than the negative supply line (assuming
no charge pump), which, for a single-supply connection,
equals 0 V. This negative or zero-in common-mode
range limitation can be overcome by proper design of the
in-amps internal level shifting, as in the AD627 mono-
lithic 2-op amp instrumentation amplifer. However,
even with good design, some positive common-mode
voltage range will be traded off to achieve operation at
zero common-mode voltage.

Figure 2-7. The 2-Op Amp In-Amp Architecture

Figure 2-8. Output Swing Limitations of 2-Op Amp In-Amp Using a 2.5 V Reference
2-6
Another, and perhaps more serious, limitation of the
standard 2-amplifer instrumentation amplifer circuit
compared to 3-amplifer designs, is the intrinsic diffculty
of achieving high ac common-mode rejection. This
limitation stems from the inherent imbalance in the
common-mode signal path of the 2-amplifer circuit.
Assume that a sinusoidal common-mode voltage, V
CM
,
at a frequency F
CM
, is applied (common mode) to inputs
V
IN1
and V
IN2
(Figure 2-8). Ideally, the amplitude of the
resulting ac output voltage (the common-mode error)
should be 0 V, independent of frequency, F
CM
, at least over
the range of normal ac power line (mains) frequencies:
50 Hz to 400 Hz. Power lines tend to be the source of
much common-mode interference.
If the ac common-mode error is zero, amplifer A2
and gain network R3, R4 must see zero instantaneous
difference between the common-mode voltage, applied
directly to V
IN2
, and the version of the common-mode
voltage that is amplifed by A1 and its associated gain
network R1, R2. Any dc common-mode error (assuming
negligible error from the amplifers own CMRR) can
be nulled by trimming the ratios of R1, R2, R3, and R4
to achieve the balance
R1 R4 and R2 R3
However, any phase shift (delay) introduced by amplifer
A1 will cause the phase of V
O1
to slightly lag behind
the phase of the directly applied common-mode
voltage of V
IN2
. This difference in phase will result in
an instantaneous (vector) difference in V
O1
and V
IN2
,
even if the amplitudes of both voltages are at their
ideal levels. This will cause a frequency dependent
common-mode error voltage at the circuits output,
V
OUT
. Further, this ac common-mode error will increase
linearly with common-mode frequency, because the phase
shift through A1 (assuming a single-pole roll-off) will
increase directly with frequency. In fact, for frequencies
less than 1/10th the closed-loop bandwidth (f
T1
) of A1,
the common-mode error (referred to the input of the
in-amp) can be approximated by
% % % CMError
V G
V
f
f
E
CM
CM
TI
= ( ) = ( ) 100 100
where V
E
is the common-mode error voltage at V
OUT
,
and G is the differential gainin this case 5.

Figure 2-9. CMR vs. Frequency of AD627
In-Amp Circuit
For example, if A1 has a closed-loop bandwidth of
100 kHz (a typical value for a micropower op amp),
when operating at the gain set by R1 and R2, and the
common-mode frequency is 100 Hz, then
% % . % CMError = ( ) =
100
100
100 0 1
Hz
kHz
A common-mode error of 0.1% is equivalent to 60 dB
of common-mode rejection. So, in this example, even if
this circuit were trimmed to achieve 100 dB CMR at dc,
this would be valid only for frequencies less than 1 Hz. At
100 Hz, the CMR could never be better than 60 dB.
The AD627 monolithic in-amp embodies an advanced
version of the 2-op amp instrumentation amplifier
circuit that overcomes these ac common-mode rejection
limitations. As illustrated in Figure 2-9, the AD627
maintains over 80 dB of CMR out to 8 kHz (gain of
1,000), even though the bandwidth of amplifers A1
and A2 is only 150 kHz.
The four resistors used in the subtractor are normally
internal to the IC and are usually of very high resistance.
High common-mode voltage difference amps (diff amps)
typically use input resistors selected to provide voltage
attenuation. Therefore, both the differential signal
voltage and the common-mode voltage are attenuated,
the common mode is rejected, and then the signal
voltage is amplified.
Auto-Zeroing Instrumentation Amplifers
Auto-zeroing is a dynamic offset and drift cancellation
technique that reduces input referred voltage offset to
the V level, and voltage offset drift to the nV/`C level.
2-7
A further advantage of dynamic offset cancellation is
the reduction of low frequency noise, in particular the
1/f component.
The AD8230 is an instrumentation amplifer which
utilizes an auto-zeroing topology and combines it with
high common-mode signal rejection. The internal signal
path consists of an active differential sample-and-hold
stage (preamp), followed by a differential amplifer
(gain amp). Both amplifers implement auto-zeroing to
minimize offset and drift. A fully differential topology
increases the immunity of the signals to parasitic noise
and temperature effects. Amplifer gain is set by two
external resistors for convenient TC matching. The
AD8230 can accept input common-mode voltages
within and including the supply voltages (5 V).
The signal sampling rate is controlled by an on-chip,
10 kHz oscillator and logic to derive the required nonover-
lapping clock phases. For simplifcation of the functional
description, two sequential clock phases, A and B, will
be used to distinguish the order of internal operation as
depicted in Figures 2-10 and 2-11, respectively.
During Phase A, the sampling capacitors are connected
to the input signals at the common-mode potential. The
input signals difference voltage, V
DIFF
, is stored across
the sampling capacitors, C
SAMPLE
. The common-mode
potential of the input affects C
SAMPLE
insofar as the
sampling capacitors are at a different common-mode
potential than the preamp. During this period, the gain
amp is disconnected from the preamp so its output re-
mains at the level set by the previously sampled input
signal, held on C
HOLD
in Figure 2-10.
In Phase B, upon sampling the analog input signals, the
input common-mode component is removed. The com-
mon-mode output of the preamp is held at the reference
potential, V
REF
. When the bottom plates of the sampling
capacitors connect to the output of the preamp, the input
signal common-mode voltage is pulled to the amplifers
common-mode voltage, V
REF
. In this manner, the sampling
capacitors are brought to the same common-mode volt-
age as the preamp. The remaining differential signal is
presented to the gain amp, refreshing the hold capacitors
signal potentials as shown in Figure 2-11.
C
HOLD
C
HOLD
+
+
C
SAMPLE
V
OUT
V
REF
V
+IN
V
DIFF
+V
CM
V
IN
R
F
R
G
PREAMP GAIN AMP
Figure 2-10. The AD8230 in Phase A sampling phase. The differential component of the input signal is
stored on sampling capacitors, C
SAMPLE
. The gain amp conditions the signal stored on the hold capaci-
tors, C
HOLD
. Gain is set with the R
G
and R
F
resistors.
C
HOLD
C
HOLD
+
+
C
SAMPLE
V
OUT
V
REF
V
+IN
V
DIFF
+V
CM
V
IN
R
F
R
G
PREAMP GAIN AMP
Figure 2-11. In Phase B, the differential signal is transferred to the hold capacitors, refreshing the value
stored on C
HOLD
. The gain amp continues to condition the signal stored on the hold capacitors, C
HOLD
.
2-8
C
HOLD
C
HOLD
+
+
C
SAMPLE V
OUT
V
REF
A
A
A
A
B
B
B
B
A
V
+IN
V
DIFF
+V
CM
V
IN
R
F
R
G
PREAMP GAIN AMP
A
C
P_HOLD
B
B
Figure 2-12. Detailed schematic of the preamp during Phase A. The differential signal is
stored on the sampling capacitors. Concurrently, the preamp nulls its own offset and
stores the correction voltage on its hold capacitors, C
P_HOLD
.
C
HOLD
C
HOLD
V
NULL

+
+
V
REF
PREAMP
MAIN
AMP
NULLING AMP
GAIN AMP
s
f
V
OUT
S
n
f
n
C
N_HOLD
C
M_HOLD
R
F
R
G
B
B
A A
A
B
B
B
Figure 2-13. Detailed schematic of the gain amp during Phase A. The main amp conditions
the signal held on the hold capacitors, C
HOLD
. The nulling amplifer forces the inputs of the
main amp to be equal by injecting a correction voltage into the V
NULL
port, removing the
offset of the main amp. The correction voltage is stored on C
M_HOLD
.
Figures 2-12 through 2-15 show the internal workings
of the AD8230 in depth. As noted, both the preamp
and gain amp auto-zero. The preamp auto-zeroes during
phase A, shown in Figure 2-12, while the sampling caps
are connected to the signal source. By connecting the
preamp differential inputs together, the resulting output
referred offset is connected to an auxiliary input port to the
preamp. Negative feedback operation forces a canceling
potential at the auxiliary port, which is subsequently
held on a storage capacitor, C
P_HOLD
.
While in Phase A, the gain amp shown in Figure 2-13
reads the previously sampled signal held on the holding
capacitors, C
HOLD
. The gain amp implements feedforward
offset compensation to allow for transparent nulling of
the main amp and a continuous output signal. A differential
signal regimen is maintained throughout the main amp and
feedforward nulling amp by utilizing a double differential
input topology. The nulling amp compares the input of
the two differential signals. As a result, the offset error
is fed into the null port of the main amp, V
NULL
, and
2-9
C
HOLD
C
HOLD
+
+
C
SAMPLE V
OUT
V
REF
A
A
A
A
B
B
B
B
A
V
+IN
V
DIFF
+V
CM
V
IN
R
F
R
G
PREAMP GAIN AMP
A
C
P_HOLD
B
B
Figure 2-14. Detailed schematic of the preamp during Phase B. The preamps offset
remains low because it was corrected in the previous phase. The sampling capacitors con-
nect to the input and output of the preamp and the difference voltage is passed onto the
holding capacitors, C
HOLD
.
stored on C
M_HOLD
. This operation effectively forces
the differential input potentials at both the signal and
feedback ports of the main amp to be equal. This is the
requirement for zero offset.
During Phase B, the inputs of the preamp are no longer
shorted and the sampling capacitors are connected to the
input and output of the preamp as shown in Figure 2-14.
The preamp, having been auto-zeroed in Phase A, has
minimal offset. When the sampling capacitors are con-
nected to the preamp, the common mode of the sampling
capacitors is brought to V
REF
. The preamp outputs the
difference signal onto the hold capacitors, C
HOLD
.
The main amp continues to output the gained differ-
ence signal, shown in Figure 2-15. Its offset is kept to a
minimum by using the nulling amps correction potential
stored on C
M_HOLD
from the previous phase. During this
phase, the nulling amp compares its two differential inputs
and corrects its own offset by driving a correction voltage
into its nulling port and, ultimately, onto C
N_HOLD
. In
this fashion, the nulling amp reduces its own offset in
Phase B before it corrects for the main amps offset in
the next phase, Phase A.
A related product, the AD8555, is a zero-drift, single-
supply, sensor amplifer with digitally programmable
gain. Details on this product can be found on the Analog
Devices website at www.analog.com.
2-10
C
HOLD
C
HOLD
V
NULL

+
+
V
REF
PREAMP
MAIN
AMP
NULLING AMP
GAIN AMP
s
f
V
OUT
S
n
f
n
C
N_HOLD
C
M_HOLD
R
F
R
G
B
B
A A
A
B
B
B
Figure 2-15. Detailed schematic of the gain amp during Phase B. The nulling amplifer nulls
its own offset by injecting a correction voltage into its own auxiliary port and storing it on
C
N_HOLD
. The main amplifer continues to condition the differential signal held on C
HOLD
, yet
maintains minimal offset because its offset was corrected in the previous phase.
3-1
Chapter III
MONOLITHIC INSTRUMENTATION AMPLIFIERS
ADVANTAGES OVER OP AMP IN-AMPS
To satisfy the demand for in-amps that would be easier
to apply, monolithic IC instrumentation amplifiers
were developed. These circuits incorporate variations in
the 3-op amp and 2-op amp in-amp circuits previously
described, while providing laser-trimmed resistors and
other benefts of monolithic IC technology. Since both
active and passive components are now within the
same die, they can be closely matchedthis will
ensure that the device provides a high CMR. In
addition, these components will stay matched over
temperature, ensuring excellent performance over
a wide temperature range. IC technologies such as
laser wafer trimming allow monolithic integrated
circuits to be tuned up to very high accuracy and
provide low cost, high volume manufacturing. An
additional advantage of monolithic devices is that
they are available in very small, very low cost SOIC
or MSOP packages designed for use in high volume
production. Table 3-1 provides a quick performance
summary of Analog Devices in-amps.
Which to Usean In-Amp or a Diff Amp?
Although instrumentation amplifers and difference
amplifers share many properties, the frst step in the
design process should be which type of amplifier
to use.
A difference amplifer is basically an op amp subtractor,
typically using large value input resistors. The resistors
provide protection by limiting the amplifers input
current. They also reduce the input common-mode
and differential voltage to a range that can be handled
by the internal subtractor amplifer. In general, differ-
ence amplifers should be used in applications where the
common-mode voltage or voltage transients may exceed
the supply voltage.
In contrast, an instrumentation amplifer is most commonly
an op amp subtractor with two input buffer amplifers.
An in-amp should be used when the total input common-
mode voltage plus the input differential voltage, including
transients, is less than the supply voltage. In-amps are
also needed in applications where the highest accuracy,
best signal-to-noise ratio, and lowest input bias current
are essential.
Table 3-1. Latest Generation Analog Devices In-Amps Summarized
1
Power 3 dB CMR Input V
OS
RTI Input
Supply BW G = 10 Offset Drift Noise
2
Bias
Current (kHz) (dB) Voltage (V/C) (nV/Hz) Current (nA)
Product Features (Typ) (Typ G = 10) (Min) (Max) (Max) (G = 10) (Max)
AD8221 Precision, High BW 0.9 mA 560 100
3
60 V 0.4 11 (Max) 1.5
AD620 General Purpose 0. 9 mA 800 95
3
125 V 1 16 (Max) 2
AD8225 Precision Gain = 5 1.1 mA 900
4
83
4, 5
150 V 0.3 45 (Typ)
4
1.2
AD622 Low Cost 0.9 mA 800 86
3
125 V 1 14 (Typ) 5
AD621 Precise Gain 0.9 mA 800 93
3
250 V
6
2.5
6
17 (Max)
6
2
AD623 Low Cost, S.S. 375 A 800 90
3
200 V 2 35 (Typ) 25
AD627 Micropower, S.S. 60 A 80 100 250 V 3 42 (Typ) 10
NOTES
S.S. = Single Supply.
1
Refer to ADI website at www.analog.com for latest products and specifcations.
2
At 1 kHz. RTI noise = ((e
ni
)
2
+ (e
no/G
)
2
).
3
For dc to 60 Hz, 1 kU source imbalance.
4
Operating at a gain of 5.
5
For 10 kHz, 1 kU source imbalance.
6
Referred to input, RTI.
3-2
MONOLITHIC IN-AMP DESIGNTHE
INSIDE STORY
High Performance In-Amps
Analog Devices introduced the first high performance
monolithic instrumentation amplifier, the AD520,
in 1971.
In 2003, the AD8221 was introduced. This in-amp is
in a tiny MSOP package and offers increased CMR at
higher bandwidths than other competing in-amps. It
also has many key performance improvements over the
industry-standard AD620 series in-amps.
The AD8221 is a monolithic instrumentation amplifer
based on the classic 3-op amp topology (Figure 3-1).
Input transistors Q1 and Q2 are biased at a constant
current so that any differential input signal will force
the output voltages of A1 and A2 to be equal. A signal
applied to the input creates a current through R
G
, R1,
and R2 such that the outputs of A1 and A2 deliver the
correct voltage. Topologically, Q1, A1, R1, and Q2, A2,
R2 can be viewed as precision current feedback ampli-
fers. The amplifed differential and common-mode
signals are applied to a difference amplifer, A3, which
rejects the common-mode voltage, but processes the
differential voltage. The difference amplifer has a low
output offset voltage as well as low output offset volt-
age drift. Laser-trimmed resistors allow for a highly
accurate in-amp with gain error typically less than
20 ppm and CMRR that exceeds 90 dB (G = 1).
Using superbeta input transistors and an I
B
compensa-
tion scheme, the AD8221 offers extremely high input
impedance, low I
B
, low I
OS
, low I
B
drift, low input bias cur-
rent noise, and extremely low voltage noise of 8 nV/Hz.
The transfer function of the AD8221 is
G
R
R
G
G
G
= +
=

49 4
1
49 4
1
.
.
k
k

Care was taken to ensure that a user could easily and

accurately set the gain using a single external standard
value resistor.
Since the input amplifers employ a current feedback
architecture, the AD8221s gain bandwidth product
increases with gain, resulting in a system that does not
suffer from the expected bandwidth loss of voltage feed-
back architectures at higher gains.
In order to maintain precision even at low input levels,
special care was taken with the AD8221s design and
layout, resulting in an in-amp whose performance satis-
fes even the most demanding applications (see Figures
3-3 and 3-4).
A unique pinout enables the AD8221 to meet an
unparalleled CMRR specifcation of 80 dB at 10 kHz
(G = 1) and 110 dB at 1 kHz (G = 1000). The balanced
pinout, shown in Figure 3-2, reduces the parasitics that
had in the past adversely affected CMRR performance.
In addition, the new pinout simplifes board layout
because associated traces are grouped. For example,
the gain setting resistor pins are adjacent to the inputs,
and the reference pin is next to the output.

Figure 3-1. AD8221 Simplifed Schematic

3-3

Figure 3-2. AD8221 Pinout

Figure 3-3. CMR vs. Frequency of the AD8221

Figure 3-4. AD8221 Closed-Loop Gain vs.
Frequency
For many years, the AD620 has been the industry-
standard, high performance, low cost in-amp. The
AD620 is a complete monolithic instrumentation
amplifer offered in both 8-lead DIP and SOIC packages.
The user can program any desired gain from 1 to
1,000 using a single external resistor. By design, the
required resistor values for gains of 10 and 100 are
standard 1% metal film resistor values.
The AD620 (see Figure 3-5) is a second-generation
version of the classic AD524 in-amp and embodies a
modifcation of the classic 3-op amp circuit. Laser trimming
of on-chip thin flm resistors, R1 and R2, allows the
user to accurately set the gain to 100 within 0.3%
max error, using only one external resistor. Monolithic
construction and laser wafer trimming allow the tight
matching and tracking of circuit components.

Figure 3-5. A Simplifed Schematic of the AD620

3-4
A preamp section comprised of Q1 and Q2 provides
additional gain up front. Feedback through the Q1-A1-
R1 loop and the Q2-A2-R2 loop maintains a constant
collector current through the input devices Q1 and Q2,
thereby impressing the input voltage across the external
gain setting resistor, R
G
. This creates a differential
gain from the inputs to the A1/A2 outputs given by
G = (R1 + R2)/R
G
+ 1. The unity gain subtractor, A3,
removes any common-mode signal, yielding a single-
ended output referred to the REF pin potential.
The value of R
G
also determines the transconductance
of the preamp stage. As R
G
is reduced for larger gains,
the transconductance increases asymptotically to that
of the input transistors. This has three important advan-
tages. First, the open-loop gain is boosted for increasing
programmed gain, thus reducing gain related errors.
Second, the gain bandwidth product (determined by
C1, C2, and the preamp transconductance) increases
with programmed gain, thus optimizing the amplifers
frequency response. Figure 3-6 shows the AD620s
closed-loop gain vs. frequency.

Figure 3-6. AD620 Closed-Loop Gain vs.

Frequency
The AD620 also has superior CMR over a wide frequency
range, as shown in Figure 3-7.

Figure 3-7. AD620 CMR vs. Frequency

Figures 3-8 and 3-9 show the AD620s gain nonlinearity
and small signal pulse response.

Figure 3-8. AD620 Gain Nonlinearity

(G = 100, R
L
= 10 kU, Vertical Scale: 100 V =
10 ppm, Horizontal Scale 2 V/div)

Figure 3-9. Small Signal Pulse Response of

the AD620 (G = 10, R
L
= 2 kU, C
L
= 100 pF)
3-5
Finally, the input voltage noise is reduced to a value of
9 nV/Hz, determined mainly by the collector current
and base resistance of the input devices.
The internal gain resistors, R1 and R2, are trimmed to
an absolute value of 24.7 kU, allowing the gain to be
programmed accurately with a single external resistor.
The gain equation is then
G
R
G
=
49 4 . k
So that
R
G
G
=

49 4
1
. k
Where resistor R
G
is in kU.
The value of 24.7 kU was chosen so that standard
1% resistor values could be used to set the most
popular gains.
The AD621 is similar to the AD620, except that for
gains of 10 and 100 the gain setting resistors are on the
dieno external resistors are used. A single external
jumper (between Pins 1 and 8) is all that is needed to
select a gain of 100. For a gain of 10, leave Pin 1 and
Pin 8 open. This provides excellent gain stability over
temperature, as the on-chip gain resistor tracks the TC
of the feedback resistor. Figure 3-10 is a simplifed
schematic of the AD621. With a max total gain error of
0.15% and 5 ppm/`C gain drift, the AD621 has much
greater built-in accuracy than the AD620.
The AD621 may also be operated at gains between 10
and 100 by using an external gain resistor, although gain
error and gain drift over temperature will be degraded.
Using external resistors, device gain is equal to
G = (R1 + R2)/R
G
+ 1

Figure 3-10. A Simplifed Schematic of the AD621

3-6
Figures 3-11 and 3-12 show the AD621s CMR vs.
frequency and closed-loop gain vs. frequency.

Figure 3-11. AD621 CMR vs. Frequency

Figure 3-12. AD621 Closed-Loop Gain vs.

Frequency
Figures 3-13 and 3-14 show the AD621s gain nonlinear-
ity and small signal pulse response.

Figure 3-13. AD621 Gain Nonlinearity
(G = 10, R
L
= 10 kU, Vertical Scale: 100 V/div
= 100 ppm/div, Horizontal Scale 2 V/div)

Figure 3-14. Small Signal Pulse Response of
the AD621 (G = 10, R
L
= 2 kU, C
L
= 100 pF)
3-7
Fixed Gain In-Amps
The AD8225 is a precision, gain-of-5, monolithic
in-amp. Figure 3-15 shows that it is a 3-op amp in-
strumentation amplifer. The unity gain input buffers
consist of superbeta NPN transistors Q1 and Q2 and
op amps A1 and A2. These transistors are compensated
so that their input bias currents are extremely low,
typically 100 pA or less. As a result, current noise is
also low, only 50 fA/Hz. The input buffers drive a
gain-of-5 difference amplifer. Because the 3 kU and
15 kU resistors are ratio matched, gain stability is better
than 5 ppm/ `C over the rated temperature range.
The AD8225 has a wide gain bandwidth product,
resulting from its being compensated for a fixed gain
of 5, as opposed to the usual unity gain compensation
of variable gain in-amps. High frequency perfor-
mance is also enhanced by the innovative pinout of
the AD8225. Since Pins 1 and 8 are uncommitted,
Pin 1 may be connected to Pin 4. Since Pin 4 is also
ac common, the stray capacitance at Pins 2 and 3
is balanced.
Figure 3-16 shows the AD8225s CMR vs. frequency
while Figure 3-17 shows its gain nonlinearity.

Figure 3-16. AD8225 CMR vs. Frequency

Figure 3-17. AD8225 Gain Nonlinearity
Q1
A1
C2
V
S
+V
S
+V
S
IN
400U 400U
UNITY
GAIN
BUFFERS R2
Q2
A2
C1
+IN
R1
V
S
+V
S
V
S
+V
S
V
S
+V
S
A3 V
OUT
V
REF
V
B
3k
3k
15k
15k
GAIN-OF-5
DIFFERENCE AMPLIFIER
Figure 3-15. AD8225 Simplifed Schematic
3-8
Low Cost In-Amps
The AD622 is a low cost version of the AD620 (see
Figure 3-5). The AD622 uses streamlined production
methods to provide most of the performance of the
AD620 at lower cost.
Figures 3-18, 3-19, and 3-20 show the AD622s CMR
vs. frequency and gain nonlinearity and closed-loop
gain vs. frequency.

Figure 3-18. AD622 CMR vs. Frequency

((RTI) 0 to 1 kU Source Imbalance)

Figure 3-19. AD622 Gain Nonlinearity
(G = 1, R
L
= 10 kU, Vertical Scale: 20 V = 2 ppm)

Figure 3-20. AD622 Closed-Loop

Gain vs. Frequency
Monolithic In-Amps Optimized for
Single-Supply Operation
Single-supply in-amps have special design problems that
need to be addressed. The input stage must be able to
amplify signals that are at ground potential (or very close
to ground), and the output stage needs to be able to swing
to within a few millivolts of ground or the supply
rail. Low power supply current is also important.
And, when operating from low power supply voltages,
the in-amp needs to have an adequate gain bandwidth
product, low offset voltage drift, and good CMR vs. gain
and frequency.
The AD623 is an instrumentation amplifer based
on the 3-op amp in-amp circuit, modifed to ensure
operation on either single- or dual-power supplies, even
at common-mode voltages at, or even below, the negative
supply rail (or below ground in single-supply operation).
Other features include rail-to-rail output voltage swing,
low supply current, microsmall outline packaging, low
input and output voltage offset, microvolt/dc offset level
drift, high common-mode rejection, and only one external
resistor to set the gain.
3-9
As shown in Figure 3-21, the input signal is applied to
PNP transistors acting as voltage buffers and dc level
shifters. A resistor trimmed to within 0.1% of 50 kU
in each amplifers (A1 and A2) feedback path ensures
accurate gain programmability.
The differential output is
V
R
V
O
G
C
= +

1
100k
where R
G
is in kU.
The differential voltage is then converted to a single-ended
voltage using the output difference amplifer, which also
rejects any common-mode signal at the output of the
input amplifers.
Since all the amplifers can swing to either supply rail,
as well as have their common-mode range extended to
below the negative supply rail, the range over which the
AD623 can operate is further enhanced.
Note that the base currents of Q1 and Q2 fow directly out
of the input terminals, unlike dual-supply input-
current compensated in-amps such as the AD620. Since
the inputs (i.e., the bases of Q1 and Q2) can operate at
ground (i.e., 0 V or, more correctly, at 200 mV below
ground), it is not possible to provide input current com-
pensation for the AD623. However, the input bias current
of the AD623 is still very small: only 25 nA max.
The output voltage at Pin 6 is measured with respect
to the reference potential at Pin 5. The impedance of the
reference pin is 100 kU. Internal ESD clamping diodes
allow the input, reference, output, and gain terminals of
the AD623 to safely withstand overvoltages of 0.3 V above
or below the supplies. This is true for all gains, and with
power on or off. This last case is particularly important
since the signal source and the in-amp may be powered
separately. If the overvoltage is expected to exceed this
value, the current through these diodes should be limited
to 10 mA, using external current limiting resistors (see
Input Protection section). The value of these resistors is
defned by the in-amps noise level, the supply voltage,
and the required overvoltage protection needed.
The bandwidth of the AD623 is reduced as the gain
is increased since A1 and A2 are voltage feedback op
amps. However, even at higher gains the AD623 still
has enough bandwidth for many applications.

Figure 3-21. AD623 Simplifed Schematic

The AD623s gain is resistor programmed by R
G

or more precisely by whatever impedance appears
between Pins 1 and 8. Figure 3-22 shows the gain vs.
frequency of the AD623. The AD623 is laser-trimmed
to achieve accurate gains using 0.1% to 1% tolerance
resistors.

Figure 3-22. AD623 Closed-Loop Gain
vs. Frequency
3-10
Table 3-2. Required Value of Gain Resistor
Desired 1% Std. Calculated Gain
Gain Value of R
G
, Using 1% Resistors
2 100 k 2
5 24.9 k 5.02
10 11 k 10.09
20 5.23 k 20.12
33 3.09 k 33.36
40 2.55 k 40.21
50 2.05 k 49.78
65 1.58 k 64.29
100 1.02 k 99.04
200 499 201.4
500 200 501
1000 100 1001
Table 3-2 shows required values of R
G
for various gains.
Note that for G = 1, the R
G
terminals are unconnected
(R
G
= ). For any arbitrary gain, R
G
can be calculated
using the formula
R
G
= 100 kU/(G 1)
Figure 3-23 shows the AD623s CMR vs. frequency.
Note that the CMR increases with gain up to a gain of
100 and that CMR also remains high over frequency, up
to 200 Hz. This ensures the attenuation of power line
common-mode signals (and their harmonics).

Figure 3-23. AD623 CMR vs. Frequency (V
S
= 5 V)
Figure 3-24 shows the gain nonlinearity of the AD623.
Figure 3-24. AD623 Gain Nonlinearity
(G = 10, 50 ppm/div)
Figure 3-25 shows the small signal pulse response of
the AD623.
Figure 3-25. AD623 Small Signal Pulse Response
(G = 10, R
L
= 10 kU, C
L
= 100 pF)
3-11
Low Power, Single-Supply In-Amps
The AD627 is a single-supply, micropower instrumenta-
tion amplifer that can be confgured for gains between 5
and 1,000 using just a single external resistor. It provides
a rail-to-rail output voltage swing using a single 3 V to
30 V power supply. With a quiescent supply current of
only 60 A (typical), its total power consumption is less
than 180 W, operating from a 3 V supply.
Figure 3-26 is a simplifed schematic of the AD627. The
AD627 is a true instrumentation amplifer built using
two feedback loops. Its general properties are similar to
those of the classic 2-op amp instrumentation amplifer
confguration, and can be regarded as such, but internally
the details are somewhat different. The AD627 uses a
modifed current feedback scheme which, coupled with
interstage feedforward frequency compensation, results
in a much better CMRR (common-mode rejection ratio)
at frequencies above dc (notably the line frequency of
50 Hz to 60 Hz) than might otherwise be expected of a
low power instrumentation amplifer.
As shown in Figure 3-26, A1 completes a feedback loop
which, in conjunction with V1 and R5, forces a constant
collector current in Q1. Assume for the moment that
the gain-setting resistor (R
G
) is not present. Resistors
R2 and R1 complete the loop and force the output of
A1 to be equal to the voltage on the inverting terminal
with a gain of (almost exactly) 1.25. A nearly identical
feedback loop completed by A2 forces a current in Q2,
which is substantially identical to that in Q1, and A2 also
provides the output voltage. When both loops are bal-
anced, the gain from the noninverting terminal to V
OUT

is equal to 5, whereas the gain from the output of A1 to
V
OUT
is equal to 4. The inverting terminal gain of A1,
(1.25) times the gain of A2, (4) makes the gain from
the inverting and noninverting terminals equal.
The differential mode gain is equal to 1 + R4/R3, nomi-
nally 5, and is factory trimmed to 0.01% fnal accuracy
(AD627B typ). Adding an external gain setting resis-
tor (R
G
) increases the gain by an amount equal to
(R4 + R1)/R
G
. The gain of the AD627 is given by the
following equation:
G
R
G
= +

5
200k

Figure 3-26. AD627 Simplifed Schematic

3-12
Laser trims are performed on resistors R1 through R4
to ensure that their values are as close as possible to
the absolute values in the gain equation. This ensures
low gain error and high common-mode rejection at all
practical gains.
Figure 3-27 shows the AD627s CMR vs. frequency.

Figure 3-27. AD627 CMR vs. Frequency
Figures 3-28 and 3-29 show the AD627s gain vs.
frequency and gain nonlinearity.

Figure 3-28. AD627 Closed-Loop Gain
vs. Frequency

Figure 3-29. AD627 Gain Nonlinearity

(V
S
= 2.5 V, G = 5, 4 ppm/Vert Division)
The AD627 also has excellent dynamic response, as
shown in Figure 3-30.
Figure 3-30. Small Signal Pulse Response of the
AD627 (V
S
= 5 V, G = +10, R
L
= 20 kU, C
L
= 50 pF,
20 s/Horizontal Division, 20 mV/Vertical Division)
4-1
Chapter IV
MONOLITHIC DIFFERENCE AMPLIFIERS
Difference (Subtractor) Amplifer Products
Monolithic difference amplifers are a special category of
in-amps that are usually designed to be used in applica-
tions in which large dc or ac common-mode voltages are
present. This includes automotive applications, such as
current sensing, battery cell voltage monitors, and motor
control. For this reason, difference amplifers usually
include very large value, on-chip resistor networks.
+
A2

+
A1

G = 2
G = 10
AD8202
R
F
R
F
100k
COMM
+IN
IN
A2
R
G
R
C
R
B
R
A
R
A
R
B
R
C
R
G
5
4
A1
3
+V
S
6
8
1
2
Figure 4-1. AD8202 Connection Diagram
Table 4-1. Latest Generation of Analog Devices Difference Amps Summarized
1
Power 3 dB CMR Input V
OS
RTI
Supply BW G = 10 Offset Drift Noise
2
Current (kHz) (typ) (dB) Voltage (V/`C) (nV/Hz)
Product Features (typ) (G = 10) (min) (max) (max) (G = 10)
AD8202 S.S. G = 20 250 A 50 80
3, 4, 12
1 mV
5
10 300 (typ)
3
AD8205 S.S. G = 50 1 mA 50
6
80
4, 6, 12
2 mV
5
15 (typ) 500 (typ)
6
AD8130 270 MHz Receiver 12 mA 270 MHz 83
7, 8
1.8 mV 3.5 mV 12.5 (typ)
7, 9
AD628 High CMV 1.6 mA 600
10
75
10
1.5 mV 4 300 (typ)
10
AD629 High CMV 0.9 mA 500 77
7
1 mV 6 550 (typ)
7
AD626 High CMV 1.5 mA 100 55
11
500 V 1 250 (typ)
AMP03 High BW G = 1 3.5 mA 3 MHz 85
7
400 V NS 750 (typ)
7
NOTES
NS = not specifed, NA = not applicable, S.S. = single supply.
1
Refer to ADI website at www.analog.com for latest products and specifcations.
2
At 1 kHz. RTI noise = (e
ni
)
2
+ (e
no
/G)
2
.
3
Operating at a gain of 20.
4
For 10 kHz, <2 kU source imbalance.
5
Referred to input: RFI.
6
Operating at a gain of 50.
7
Operating at a gain of 1.
8
At frequency = 4 MHz.
9
At frequency 10 kHz.
10
Operating at a gain of 0.1.
11
For 1 kHz, 10 kHz.
12
DC to 10 kHz.
The use of large value precision resistors, which are
sometimes several hundred thousand ohms, offers ex-
cellent input protection at the expense of a higher overall
noise level. Table 4-1 provides a performance summary
of Analog Devices difference amplifer products.
The AD8202 consists of a preamp and buffer arranged
as shown in Figure 4-1.
4-2
As shown in Figure 4-2, the preamp incorporates a dy-
namic bridge (subtractor) circuit. Identical networks
(within the shaded areas) consisting of R
A
, R
B
, R
C
,
and R
G
attenuate input signals applied to Pins 1 and
8. Note that when equal amplitude signals are asserted
at inputs 1 and 8, and the output of A1 is equal to
the common potential (i.e., zero), the two attenuators
form a balanced-bridge network. When the bridge is
balanced, the differential input voltage at A1, and thus
its output, will be zero.
Any common-mode voltage applied to both inputs will
keep the bridge balanced and the A1 output at zero.
Because the resistor networks are carefully matched, the
common-mode signal rejection approaches this ideal
state. However, if the signals applied to the inputs differ,
the result is a difference at the input to A1. A1 responds
by adjusting its output to drive R
B
, by way of R
G
, to
adjust the voltage at its inverting input until it matches
the voltage at its noninverting input.
By attenuating voltages at Pins 1 and 8, the amplifer
inputs are held within the power supply range, even if
Pins 1 and 8 input levels exceed the supply, or fall below
common (ground.) The input network also attenuates
normal (differential) mode voltages. R
C
and R
G
form an
attenuator that scales A1 feedback, forcing large output
signals to balance relatively small differential inputs. The
resistor ratios establish the preamp gain at 10.
Because the differential input signal is attenuated and
then amplified to yield an overall gain of 10, the
amplifier A1 operates at a higher noise gain, multiplying
defciencies such as input offset voltage and noise with
respect to Pins 1 and 8.
To minimize these errors while extending the common-
mode range, a dedicated feedback loop is employed to
reduce the range of common-mode voltage applied to
A1 for a given overall range at the inputs. By offsetting
the range of voltage applied to the compensator, the
input common-mode range is also offset to include
voltages more negative than the power supply. Ampli-
fer A3 detects the common-mode signal applied to A1
and adjusts the voltage on the matched R
CM
resistors
to reduce the common-mode voltage range at the A1
inputs. By adjusting the common voltage of these resis-
tors, the common-mode input range is extended while
the normal mode signal attenuation is reduced, leading
to better performance referred to input.
The output of the dynamic bridge taken from A1 is
connected to Pin 3 by way of a 100 kU series resistor,
provided for low-pass fltering and gain adjustment.
The resistors in the input networks of the preamp and
the buffer feedback resistors are ratio-trimmed for
high accuracy.
The output of the preamp drives a gain-of-2 buffer
amplifer A2, implemented with carefully matched
feedback resistors R
F
.
The two-stage system architecture of the AD8202
(Figure 4-2) enables the user to incorporate a low-pass
flter prior to the output buffer. By separating the gain
into two stages, a full-scale, rail-to-rail signal from the
preamp can be fltered at Pin 3, and a half-scale signal
resulting from fltering can be restored to full scale by
the output buffer amp. The source resistance seen by
the inverting input of A2 is approximately 100 kU,
to minimize the effects of A2s input bias current.
However, this current is quite small and errors result-
ing from applications that mismatch the resistance
are correspondingly small.
100k
A1
A3
R
CM
R
CM
(TRIMMED)
R
A
IN
R
G
R
C
R
B
R
A
R
C
R
B
R
G
+IN
COM
A2
R
F
R
F
AD8202
3 4
5
2
8 1
Figure 4-2. AD8202 Simplifed Schematic
4-3
The AD8205 is a single-supply difference amplifer that
uses a unique architecture to accurately amplify small
differential current shunt voltages in the presence of
rapidly changing common-mode voltages. It is offered
in both packaged and die form.
In typical applications, the AD8205 is used to measure
current by amplifying the voltage across a current shunt
placed across the inputs.
The gain of the AD8205 is 50 V/V, with an accuracy of
1.2%. This accuracy is guaranteed over the operating
temperature range of 40`C to +125`C. The die tem-
perature range is 40`C to +150`C with a guaranteed
gain accuracy of 1.3%.
The input offset is less than 2 mV referred to the input at
25`C, and 4.5 mV maximum referred to the input over
the full operating temperature range for the packaged
part. The die input offset is less than 6 mV referred to
the input over the die operating temperature range.
The AD8205 operates with a single supply from 4.5 V to
10 V (absolute maximum = 12.5 V). The supply current
is less than 2 mA.
High accuracy trimming of the internal resistors allows
the AD8205 to have a common-mode rejection ratio
better than 78 dB from dc to 20 kHz. The common-mode
rejection ratio over the operating temperature is 76 dB
for both the die and packaged part.
The output offset can be adjusted from 0.05 V to 4.8 V
(V+ = 5 V) for unipolar and bipolar operation.
The AD8205 consists of two amplifers (A1 and A2),
a resistor network, small voltage reference, and a bias
circuit (not shown). See Figure 4-3.
AD8205
+IN IN
250mV
GND
A1
A2
R
A
R
A
R
B
R
B
R
F
R
F
R
D
R
D
R
E
R
F
R
C
R
C
V
OUT
R
REF
R
REF
V
REF
1
V
REF
2
Figure 4-3. Simplifed Schematic
The set of input attenuators preceding A1 consist of R
A
,
R
B
, and R
C
, which reduce the common-mode voltage to
match the input voltage range of A1. The two attenuators
form a balanced-bridge network. When the bridge is bal-
anced, the differential voltage created by a common-mode
voltage is 0 V at the inputs of A1. The input attenuation
ratio is 1/16.7. The combined series resistance of R
A
, R
B
,
and R
C
is approximately 200 kU 20%.
By attenuating the voltages at Pin 1 and Pin 8, the A1
amplifer inputs are held within the power supply range,
even if Pin 1 and Pin 8 exceed the supply or fall below
common (ground). A reference voltage of 250 mV
biases the attenuator above ground. This allows
the amplifier to operate in the presence of negative
common-mode voltages.
The input network also attenuates normal (differential)
mode voltages. A1 amplifes the attenuated signal by 26.
The input and output of this amplifer are differential to
maximize the ac common-mode rejection.
A2 converts the differential voltage from A1 into a single-
ended signal and provides further amplifcation. The gain
of this second stage is 32.15.
The reference inputs, V
REF
1 and V
REF
2, are tied through
resistors to the positive input of A2, which allows the
output offset to be adjusted anywhere in the output
operating range. The gain is 1 V/V from the reference
pins to the output when the reference pins are used
in parallel. The gain is 0.5 V/V when they are used to
divide the supply.
The ratios of Resistors R
A
, R
B
, R
C
, R
D
, and R
F
are
trimmed to a high level of precision to allow the
common-mode rejection ratio to exceed 80 dB. This
is accomplished by laser trimming the resistor ratio
matching to better than 0.01%.
The total gain of 50 is made up of the input attenuation
of 1/16.7 multiplied by the frst stage gain of 26 and the
second stage gain of 32.15.
The output stage is Class A with a PNP pull-up transistor
and a 300 A current sink pull-down.
4-4
The AMP03 is a monolithic, unity gain, 3 MHz dif-
ferential amplifier. Incorporating a matched thin-film
resistor network, the AMP03 features stable opera-
tion over temperature without requiring expensive
external matched components. The AMP03 is a basic
analog building block for differential amplifier and
instrumentation applications (Figure 4- 4).
V
EE
4
REFERENCE 1
OUTPUT 6
V
CC
7
SENSE 5
+IN 3
IN 2
25k 25k
25k 25k
AMP03
Figure 4-4. AMP03 Functional Block Diagram
The differential amplifer topology of the AMP03 serves
both to amplify the difference between two signals and
to provide extremely high rejection of the common-mode
input voltage. With a typical common-mode rejection of
100 dB, the AMP03 solves common problems encountered
in instrumentation design. It is ideal for performing either
the addition or subtraction of two input signals without
using expensive externally matched precision resistors.
Because of its high CMR over frequency, the AMP03 is
an ideal general-purpose amplifer for data acquisition
systems that must operate in a noisy environment. Figures
4-5 and 4-6 show the AMP03s CMR and closed-loop
gain vs. frequency.
120
110
100
90
80
70
60
50
40
30
10
1 10 100 1k 10k 10k 1M
20
0
FREQUENCY (Hz)
C
O
M
M
O
N
-
M
O
D
E
R
E
J
E
C
T
I
O
N
(
d
B
)
T
A
= 25C
V
S
= 15V
Figure 4-5. AMP03 CMR vs. Frequency
50
100 1k 10k 10k 10M 1M
30
20
10
0
10
20
30
40
FREQUENCY (Hz)
C
L
O
S
E
D
-
L
O
O
P
G
A
I
N
(
d
B
)
T
A
= 25C
V
S
= 15V
Figure 4-6. AMP03 Closed-Loop Gain
vs. Frequency
Figure 4-7 shows the small signal pulse response of
the AMP03.
100
90
0
50mV 1s
T
A
= 25C
V
S
= 15V
Figure 4-7. AMP03 Small Signal Pulse Response
The AD626 is a single- or dual-supply differential
amplifer consisting of a precision balanced attenuator,
a very low drift preamplifier (A1), and an output
buffer amplifier (A2). It has been designed so that
small differential signals can be accurately amplifed
and fltered in the presence of large common-mode
voltages (much greater than the supply voltage) without
the use of any other active components.
4-5
Figure 4-8 shows the main elements of the AD626. The
signal inputs at Pins 1 and 8 are frst applied to dual
resistive attenuators, R1 through R4, whose purpose is
to reduce the peak common-mode voltage at the input
to the preamplifera feedback stage based on the very
low drift op amp A1. This allows the differential input
voltage to be accurately amplifed in the presence of
large common-mode voltagessix times greater than
that which can be tolerated by the actual input to A1. As
a result, the input common-mode range extends to six
times the quantity (V
S
1 V). The overall common-mode
error is minimized by precise laser-trimming of R3 and
R4, thus giving the AD626 a common-mode rejection
ratio of at least 10,000:1 (80 dB). The output of A1 is
connected to the input of A2 via 100 kU (R12) resistor
to facilitate the low-pass fltering of the signal of interest.
The AD626 is easily confgured for gains of 10 or 100. For
a gain of 10, Pin 7 is simply left unconnected; similarly,
for a gain of 100, Pin 7 is grounded. Gains between 10
and 100 are easily set by connecting a resistor between
Pin 7 and analog GND. Because the on-chip resistors
have an absolute tolerance of 20% (although they are
ratio matched to within 0.1%), at least a 20% adjustment
range must be provided. The nominal value for this gain
setting resistor is equal to
R
GAIN
=

50 000
10
555
,

100
90
0%
10
500mV 20s
Figure 4-9. The Large Signal Pulse
Response of the AD626. G = 10
Figure 4-9 shows the large signal pulse response of
the AD626.
The AD629 is a unity gain difference amplifer designed
for applications that require the measurement of signals
with common-mode input voltages of up to 270 V.
The AD629 keeps error to a minimum by providing
excellent CMR in the presence of high common-mode
input voltages. Finally, it can operate from a wide power
supply range of 2.5 V to 18 V.
AD626
C1
5pF
+IN
IN
R1
200k
R2
200k
R3
41k
C2
5pF
R4
41k
R5
4.2k
R11
10k
R6
500
R7
500
R8
10k
R10
10k
R14
555
GND
GAIN = 100
R13
10k
R15
10k
R17
95k
R9
10k
R12
100k
FILTER
OUT
+V
S
A1
A2
V
S
Figure 4-8. AD626 Simplifed Schematic
4-6
The AD629 can replace costly isolation amplifiers
in applications that do not require galvanic isola-
tion. Figure 4-10 is the connection diagram of the
AD629. Figure 4-11 shows the AD629s CMR vs.
frequency.

Figure 4-10. AD629 Connection Diagram
100
95
90
85
80
75
70
65
60
55
20 100 1k 10k 20k
50
FREQUENCY (Hz)
C
M
R
(
d
B
)
Figure 4-11. Common-Mode Rejection
vs. Frequency
High Frequency Differential Receiver/Amplifers
Although not normally associated with difference ampli-
fers, the AD8130 series of very high speed differential
receiver/amplifers represent a new class of products
that provide effective common-mode rejection at VHF
frequencies. The AD8130 has a 3 dB bandwidth of
270 MHz, an 80 dB CMRR at 2 MHz, and a 70 dB
CMRR at 10 MHz.
V
OUT
+V
S
PD
V
S
3
7
2
1
8
V
IN
4
5
REF
FB
6
Figure 4-12. AD8130 Block Diagram
Figure 4-12 is a block diagram of the AD8130. Its design
uses an architecture called active feedback which differs
from that of conventional op amps. The most obvious
differentiating feature is the presence of two separate
pairs of differential inputs compared to a conventional
op amps single pair. Typically for the active feedback
architecture, one of these input pairs is driven by a
differential input signal, while the other is used for the
feedback. This active stage in the feedback path is where
the term active feedback is derived. The active feedback
architecture offers several advantages over a conventional
op amp in several types of applications. Among these are
excellent common-mode rejection, wide input common-
mode range, and a pair of inputs that are high impedance
and totally balanced in a typical application.
10k 100M 100k 1M 10M
120
110
100
90
80
70
60
50
40
30
FREQUENCY (Hz)
C
O
M
M
O
N
-
M
O
D
E
R
E
J
E
C
T
I
O
N
(
d
B
)
V
S
= 2.5V
V
S
= 5V, 12V
Figure 4-13. AD8130 Common-Mode
Rejection vs. Frequency
4-7
In addition, while an external feedback network
establishes the gain response as in a conventional
op amp, its separate path makes it totally independent of
the signal input. This eliminates any interaction between
the feedback and input circuits, which traditionally causes
problems with CMRR in conventional differential-input
op amp circuits.
1 400 10 100
7
6
5
4
3
2
1
0
1
2
3
FREQUENCY (MHz)
G
A
I
N
(
d
B
)
V
S
= 2.5V
V
S
= 5V
V
S
= 12V
Figure 4-14. AD8130 Frequency Response
vs. Supply Voltage
Figure 4-13 shows the CMR vs. frequency of the AD8130.
Figure 4-14 shows its f requency response vs. sup-
ply voltage.
For details concerning the entire line of monolithic in-
amps produced by Analog Devices, refer to Appendix B.
Figure 4-15 shows the AD8130s CMR vs. fre-
quency.
100
95
90
80
70
60
50
40
1k 10k 100k 1M 10M
30
FREQUENCY (Hz)
C
M
R
(
d
B
)
V
S
= 15V
V
S
= 5V
Figure 4-15. AD8130 CMR vs. Frequency
5-1
Dual-Supply Operation
The conventional way to power an in-amp has been
from a split or dual polarity power supply. This has
the obvious advantage of allowing both a positive and
a negative input and output swing.
Single-Supply Operation
Single-supply operation has become an increasingly desir-
able characteristic of a modern in-amp. Many present day
data acquisition systems are powered from a single low
voltage supply. For these systems, there are two vitally
important characteristics. First, the in-amps input range
should extend between the positive supply and the nega-
tive supply (or ground). Second, the amplifers output
should be rail-to-rail as well, providing an output swing to
within 100 mV or less of either supply rail or ground. In
contrast, a standard dual-supply in-amp can only swing
to within a volt or two of either supply or ground. When
operated from a 5 V single supply, these in-amps have
only a volt or two of output voltage swing, while a true
rail-to-rail amplifer can provide a peak-to-peak output
nearly as great as the supply voltage. Another important
point is that a single-supply, or rail-to-rail in-amp, will
still operate well (or even better) from a dual supply, and
it will often operate at lower power than a conventional
dual-supply device.
Power Supply Bypassing, Decoupling, and
Stability Issues
Power supply decoupling is an important detail that is
often overlooked by designers. Normally, bypass capaci-
tors (values of 0.1 F are typical) are connected between
the power supply pins of each IC and ground. Although
usually adequate, this practice can be ineffective or even
create worse transients than no bypassing at all. It is im-
portant to consider where the circuits currents originate,
where they will return, and by what path. Once that has
been established, bypass these currents around ground
and other signal paths.
In general, like op amps, most monolithic in-amps have
their integrators referenced to one or both power supply
lines and should be decoupled with respect to the output
reference terminal. This means that for each chip a bypass
capacitor should be connected between each power supply
pin and the point on the board where the in-amps reference
terminal is connected, as shown in Figure 5-1.

Figure 5-1. Recommended Method for

Power Supply Bypassing
For a much more comprehensive discussion of these is-
sues, refer to application note AN-202 An IC Amplifer
Users Guide to Decoupling, Grounding, and Making
Things Go Right for a Change, by Paul Brokaw, on the
ADI website at www.analog.com.
THE IMPORTANCE OF AN INPUT
GROUND RETURN
One of the most common applications problems that
arises when using in-amp circuits is failure to provide
a dc return path for the in-amps input bias currents.
This usually happens when the in-amps inputs are
capacitively coupled. Figure 5-2 shows just such an
arrangement. Here, the input bias currents quickly
charge up capacitors C1 and C2 until the in-amps
output rails, either to the supply or ground.

Figure 5-2. An AC-Coupled In-Amp Circuit

Without an Input Ground Return
Chapter V
APPLYING IN-AMPS EFFECTIVELY
5-2
The solution is to add a high value resistance (R1, R2)
between each input and ground, as shown in Figure 5-3.
The input bias currents can now fow freely to ground
and do not build up a large input offset as before. In
the vacuum tube circuits of years past, a similar effect
occurred, requiring a grid leak resistance between the
grid (input) and ground to drain off the accumulated
charge (the electrons on the grid).
AC Input Coupling
Referring again to Figure 5-3, practical values for R1
and R2 are typically 1 MU or less. The choice of resistor
value is a trade-off between offset errors and capacitance
value. The larger the input resistor, the greater the input
offset voltage due to input offset currents. Offset voltage
drift will also increase.
With lower resistor values, higher value input capacitors
must be used for C1 and C2 to provide the same 3 dB
corner frequency
F
3 dB
= (1/(2rR1C1)) where R1 = R2 and C1 = C2

Figure 5-3. A High Value Resistor between

Each Input and Ground Provides an Effective
DC Return Path
Unless there is a large dc voltage present on the
input side of the ac coupling capacitor, nonpolarized
capacitors should be used. Therefore, in the interest of
keeping component size as small as possible, C
1
and
C
2
should be 0.1 F or less. Generally, the smaller
the capacitor value the better, because it will cost less
and be smaller in size. The voltage rating of the input
coupling capacitor needs to be high enough to avoid
breakdown from any high voltage input transients that
might occur.
RC Component Matching
Since
(I
B1
R1) (I
B2
R2) = AV
OS
any mismatch between R1 and R2 will cause an input
offset imbalance (I
B1
I
B2
) which will create an input
offset voltage error.
A good guideline is to keep I
B
R < 10 mV.
The input bias currents of Analog Devices in-amps
vary widely, depending on input architecture. However,
the vast majority have maximum input bias currents
between 1.5 nA and 10 nA. Table 5-1 gives typical R
and C cookbook values for ac coupling using 1% metal
flm resistors and two values of input bias current.
Figure 5-4 shows the recommended dc return for a
transformer-coupled input.

Figure 5-4. Recommended DC Return Path for a Transformer-Coupled Input

5-3
CABLE TERMINATION
When in-amps are used at frequencies above a few hun-
dred kilohertz, properly terminated 50 U or 75 U coaxial
cable should be used for input and output connections.
Normally, cable termination is simply a 50 U or 75 U
resistor connected between the cable center conductor
and its shield at the end of the coaxial cable. Note that
a buffer amplifer may be required to drive these loads
to useful levels.
INPUT PROTECTION BASICS
FOR ADI IN-AMPS
Input Protection from ESD and DC Overload
As interface amplifers for data acquisition systems,
instrumentation amplifers are often subjected to input
overloads, i.e., voltage levels in excess of their full scale
for the selected gain range or even in excess of the supply
voltage. These overloads fall into two general classes:
steady state and transient (ESD, etc.), which occur for
only a fraction of a second. With 3-op amp in-amp
designs, when operating at low gains (10 or less), the
gain resistor acts as a current-limiting element in series
with their resistor inputs. At high gains, the lower value
of R
G
may not adequately protect the inputs from
excessive currents.
Standard practice is to place current-limiting resistors
in each input, but adding this protection also increases
the circuits noise level. A reasonable balance needs to
be found between the protection provided and the
increased resistor (Johnson) noise introduced. Cir-
cuits using in-amps with a relatively high noise level
can tolerate more series protection without seriously
increasing their total circuit noise.
Of course, the less added noise the better, but a good
guideline is that circuits needing this extra protection
can easily tolerate resistor values that generate 30% of
the total circuit noise. For example, a circuit using an
in-amp with a rated noise level of 20 nV/Hz can tolerate
an additional 6 nV/Hz of Johnson noise.
Use the following cookbook method to translate this
number into a practical resistance value. The Johnson
noise of a 1 kU resistor is approximately 4 nV/Hz. This
value varies as the square root of the resistance. So, a
20 kU resistor would have 20 times as much noise as
the 1 kU resistor, which is 17.88 nV/Hz (4.4721 times
4 nV/Hz). Because both inputs need to be protected,
two resistors are needed and their combined noise will
add as the square root of the number of resistors (the
root sum of squares value). In this case, the total added
noise from the two 20 kU resistors will be 25.3 nV/Hz
(17.88 times 1.414).
Figure 5-5 provides details on the input architecture
of the AD8221 in-amp. As shown, it has internal
400 U resistors that are in series with each input
transistor junction.
IN
R
G
+IN Q1 Q2
+V
S
+V
S
400 400
V
S
V
S
+V
S
+V
S
6mA MAX INPUT CURRENT
Figure 5-5. AD8221 In-Amp Input Circuit
Table 5-1. Recommended Component Values
for AC Coupling In-Amp Inputs
Input Bias V
OS
V
OS
Error
RC Coupling Components Current at Each for 2%
3 dB BW C1, C2 R1, R2 (IB) Input R1, R2 Mismatch
2 Hz 0.1 F 1 MU 2 nA 2 mV 40 V
2 Hz 0.1 F 1 MU 10 nA 10 mV 200 V
30 Hz 0.047 F 115 kU 2 nA 230 V 5 V
30 Hz 0.1 F 53.6 kU 10 nA 536 V 11 V
100 Hz 0.01 F 162 kU 2 nA 324 V 7 V
100 Hz 0.01 F 162 kU 10 nA 1.6 mV 32 V
500 Hz 0.002 F 162 kU 2 nA 324 V 7 V
5-4
The AD8221 was designed to handle maximum input
currents of 6 mA steady state (or dc). Its internal resistors
and diodes will protect the device from input voltages
0.7 V above the positive supply, or 2.4 V more negative
than the minus supply (6 mA 0.4 kU). Therefore,
for 15 V supplies, the maximum safe input level is
+15.7 V, 17.4 V. Additional external series resistors
can be added to increase this level considerably, at the
expense of higher circuit noise level.
The AD8221 in-amp is a very low noise device, with a
maximum (e
NI
) 8 nV/Hz. A single 1 kU resistor will
add approximately 107 nV/Hz of noise. This would
raise the maximum dc level to approximately 22.5 V
above each supply or 37.5 V with 15 V supplies.
Figure 5-6 shows the input section of the AD620 in-
amp. This is very similar to that of the AD8221: both
use a 400 U resistor in series with each input, and both
use diode protection. The chief differences are the four
additional AD8221 diodes. One set is tied between
each input and the positive supply, and the other set is
connected between the base of each input transistor and
the negative supply. The AD620 uses its 400 U internal
resistor and a single set of diodes to protect against
negative input voltages. For positive voltage overloads,
it relies on its own base-emitter input junction to act as
the clamping diode.

Figure 5-6. AD620 Series (AD620, AD621,
AD622) In-Amp Input Circuit
IN
200k
+IN Q1 Q2
+V
S
+V
S
2k 2k
6mA MAX INPUT CURRENT
+V
S
+V
S
V
S
V
S
V
S
V
S
Figure 5-7. AD627 In-Amp Input Circuit
The AD627 can tolerate 20 mA transient input currents
(Figure 5-7). In addition, it has built-in 2 kU resistors
and can handle input voltages 40 V higher than its supply
lines (20 mA times 2 kU). This level of protection is quite
benefcial. Because of its low power, many of the AD627s
applications will use a low voltage single power supply.
If even more protection is needed, quite large external
resistors can be added without seriously degrading the
AD627s 38 nV/Hz noise level. In this case, adding two
5 kU resistors will raise the circuits noise approximately
13 nV/Hz (30 percent), but would provide an additional
100 V of transient overload protection.
Figure 5-8 shows the input architecture of the AD623
in-amp. In this design, the internal (ESD) diodes are
located before the input resistors, and as a consequence
provide less protection than the other designs. The AD623
can tolerate 10 mA maximum input current, but in many
cases, some external series resistance will be needed to
keep input current below this level.

Figure 5-8. AD623 In-Amp Input Circuit

Since the AD623s device noise is approximately
35 nV/Hz, up to 5 kU of external resistance can be
added here to provide 50 V of dc overload protection,
while only increasing input noise to 38 nV/Hz total.
5-5
Table 5-2 provides recommended series protection resis-
tor values for a 10% or 40% increase in circuit noise.
Table 5-2. Recommended Series
Protection Resistor Values
Recommended
Max External Protection
In-Amp Input Resistors Adding
Noise Overload Additional Noise*
Device (e
NI
) Current of 10% of 40%
AD8221 8 nV/Hz 6 (mA) 340 U 2.43 kU
AD8225 8 nV/Hz 6 (mA) 340 U 2.43 kU
AD620 9 nV/Hz 6 (mA) 348 U 2.49 kU
AD621 9 nV/Hz 6 (mA) 348 U 2.49 kU
AD622 9 nV/Hz 6 (mA) 348 U 2.49 kU
AD623 35 nV/Hz 10 (mA) 8.08 kU 40.2 kU
AD627 38 nV/Hz 20 (mA) 8.87 kU 43.2 kU
*This noise level is for two resistors, one in series with
each resistor.
Adding External Protection Diodes
Device input protection may be increased with the
addition of external clamping diodes as shown in
Figure 5-9. As high current diodes are used, input
protection is increased, which allows the use of much
lower resistance input protection resistors which, in turn,
reduce the circuits noise.
Unfortunately, most ordinary diodes (Schottky, silicon,
etc.) have high leakage currents that will cause large offset
errors at the in-amps output; this leakage increases
exponentially with temperature. This tends to rule out
the use of external diodes in applications where the
in-amp is used with high impedance sources.
Specialty diodes with much lower leakage are available,
but these are often diffcult to fnd and are expensive.
For the vast majority of applications, limiting resistors
alone provide adequate protection for ESD and longer
duration input transients.

Figure 5-9. Using External Components

to Increase Input Protection
Despite their limitations, external diodes are often
required in some special applications, such as electric
shock defbrillators, which utilize short duration, high
voltage pulses. The combination of external diodes and
very large input resistors (as high as 100 kU) may be
needed to adequately protect the in-amp.
It is a good idea to check the diodes specifcations
to ensure that their conduction begins well before
the in-amps internal protection diodes start drawing
current. Although they provide excellent input protec-
tion, standard Schottky diodes can have leakage up to
several mA. However, as in the example of Figure 5-9,
fast Schottky barrier rectifers, such as the international
rectifer type SD101 series, can be used; these devices
have 200 nA max leakage currents and 400 mW typical
power dissipation.
ESD and Transient Overload Protection
Protecting in-amp inputs from high voltage transients
and ESD events is very important for a circuits long-
term reliability. Power dissipation is often a critical factor
as input resistors, whether internal or external, must
be able to handle most of the power of the input pulse
without failing.
ESD events, while they may be very high voltage, are
usually of very short duration and are normally one-time
events. Since the circuit has plenty of time to cool down
before the next event occurs, modest input protection is
suffcient to protect the device from damage.
On the other hand, regularly occurring short duration
input transients can easily overheat and burn out the
input resistors or the in-amps input stage. A 1 kU resis-
tor, in series with an in-amp input terminal drawing
20 mA, will dissipate 0.4 W, which can easily be handled
by a standard 0.5 W or greater surface-mount resistor.
If the input current is doubled, power consumption
quadruples as it increases as the square of the input
current (or as the square of the applied voltage).
Although it is a simple matter to use a higher power
protection resistor, this is a dangerous practice, as the
power dissipation will also increase in the in-amps input
stage. This can easily lead to device failure (see the preced-
ing section on input protection basics for input current
limitations of ADI in-amps). Except for ESD events, it
is always best to adopt a conservative approach and treat
all transient input signals as full duration inputs.
Designs that are expected to survive such events over long
periods of time must use resistors with enough resistance
to protect the in-amps input circuitry from failure and
enough power to prevent resistor burnout.
5-6
DESIGN ISSUES AFFECTING DC ACCURACY
The modern in-amp is continually being improved,
providing the user with ever-increasing accuracy and
versatility at a lower price. Despite these improvements
in product performance, there remain some fundamental
applications issues that seriously affect device accuracy.
Now that low cost, high resolution ADCs are commonly
used, system designers need to ensure that if an in-amp
is used as a preamplifer ahead of the converter, the in-
amps accuracy matches that of the ADC.
Designing for the Lowest Possible Offset
Voltage Drift
Offset drift errors include not just those associated with
the active device being used (IC in-amp or discrete in-amp
design using op amps), but also thermocouple effects in
the circuits components or wiring. The in-amps input
bias and input offset currents fowing through unbalanced
source impedances also create additional offset errors. In
discrete op amp in-amp designs, these errors can increase
with temperature unless precision op amps are used.
Designing for the Lowest Possible Gain Drift
When planning for gain errors, the effects of board layout,
the circuits thermal gradients, and the characteristics of
any external gain setting resistors are often overlooked. A
gain resistors absolute tolerance, its thermal temperature
coeffcient, its physical position relative to other resis-
tors in the same gain network, and even its physical
orientation (vertical or horizontal) are all-important
design considerations if high dc accuracy is needed.
In many ADC preamp circuits, an external user-
selected resistor sets the gain of the in-amp, so the
absolute tolerance of this resistor and its variation
over temperature, compared to that of the ICs on-
chip resistors, will affect the circuits gain accuracy.
Resistors commonly used include through-hole 1%
1/4 W metal flm types and 1% 1/8 W chip resistors.
Both types typically have a 100 ppm/C temperature
coeffcient. However, some chip resistors can have TCs
of 200 ppm/ `C or even 250 ppm/ `C.
Even when a 1% 100 ppm/`C resistor is used, the gain
accuracy of the in-amp will be degraded. The resistors
initial room temperature accuracy is only 1%, and
the resistor will drift another 0.01% (100 ppm/`C) for
every `C change in temperature. The initial gain error
can easily be subtracted out in software, but to correct
for the error vs. temperature, frequent recalibrations (and
a temperature sensor) would be required.
If the circuit is calibrated initially, the overall gain accuracy
is reduced to approximately 10 bits (0.1%) accuracy for
a 10`C change. An in-amp with a standard 1% metal flm
gain resistor should never be used ahead of even a 12-bit
converter: it would destroy the accuracy of a 14-bit or
16-bit converter.
Additional error sources associated with external resistors
also affect gain accuracy. The frst are variations in resistor
heating caused by input signal level. Figure 5-10, a simple
op amp voltage amplifer, provides a practical example.

Figure 5-10. An Example of How Differences in
Input Signal Level Can Introduce Gain Errors
Under zero signal conditions, there is no output signal
and no resistor heating. When an input signal is ap-
plied, however, an amplifed voltage appears at the op
amp output. When the amplifer is operating with gain,
Resistor R1 will be greater than R2. This means that
there will be more voltage across R1 than across R2.
The power dissipated in each resistor equals the square
of the voltage across it divided by its resistance in ohms.
The power dissipated and, therefore, the internal heating
of the resistor will increase in proportion to the value of
the resistor.
In the example, R1 is 9.9 kU and R2 is 1 kU. Consequently,
R1 will dissipate 9.9 times more power than R2. This
leads to a gain error that will vary with input level. The
use of resistors with different temperature coeffcients
can also introduce gain errors.

Figure 5-11. A Typical Discrete 3-Op Amp In-Amp

Using Large Value, Low TC Feedback Resistors
Even when resistors with matched temperature coef-
fcients (TC) are used, gain errors that vary with input
signal level can still occur. The use of larger (i.e., higher
power) resistors will reduce these effects, but accurate,
low TC power resistors are expensive and hard to fnd.
5-7
When a discrete 3-op amp in-amp is used, as shown
in Figure 5-11, these errors will be reduced. In a 3-op
amp in-amp, there are two feedback resistors, R1 and
R2, and one gain resistor, R
G
. Since the in-amp uses two
feedback resistors while the op amp uses only one, each
of the in-amps resistors only needs to dissipate half the
power (for the same gain). Monolithic in-amps, such as
the AD620, offer a further advantage by using relatively
large value (25 kU) feedback resistors. For a given gain
and output voltage, large feedback resistors will dissipate
less power (i.e., P = V
2
/R
F
). Of course, a discrete in-amp
can be designed to use large value, low TC resistors as
well, but with added cost and complexity.
Another less serious but still signifcant error source is
the so-called thermocouple effect, sometimes referred
to as thermal EMF. This occurs when two different
conductors, such as copper and metal flm, are tied to-
gether. When this bimetallic junction is heated, a simple
thermocouple is created. When using similar metals such
as a copper-to-copper junction, a thermoelectric error
voltage of up to 0.2 mV/`C may be produced. An example
of these effects is shown in Figure 5-12.
A fnal error source occurs when there is a thermal gradi-
ent across the external gain resistor. Something as simple
as mounting a resistor on end to conserve board space
will invariably produce a temperature gradient across
the resistor. Placing the resistor fat down against the PC
board will cure this problem unless there is air fowing
along the axis of the resistor (where the air fow cools one
side of the resistor more than the other side). Orienting
the resistor so that its axis is perpendicular to the airfow
will minimize this effect.

Figure 5-12. Thermocouple Effects Inside
Discrete Resistors
Practical Solutions
As outlined, a number of dc offset and gain errors are
introduced when external resistors are used with a mono-
lithic in-amp. Discrete designs tend to have even larger
errors. There are three practical solutions to this problem:
use higher quality resistors, use software correction, or,
better still, use an in-amp that has all of its gain resistors
on-chip, such as the AD621.
Option 1: Use a Better Quality Gain Resistor
As a general rule, only 12-bit or 13-bit gain performance
is possible using commonly available 1% resistors,
which assumes that some type of initial calibration
is performed.
A practical solution to this problem is to simply use a
better quality resistor. A signifcant improvement can be
made using a 0.1% 1/10 W surface-mount resistor. Aside
from having a 10 better initial accuracy, it typically has
a TC of only 25 ppm/`C, which will provide better than
13-bit accuracy over a 10`C temperature range.
If even better gain accuracy is needed, there are specialty
houses that sell resistors with lower TCs, but these are
usually expensive military varieties.
Option 2: Use a Fixed-Gain In-Amp
By far, the best overall dc performance is provided
by using a monolithic in-amp, such as the AD621 or
AD8225, in which all the resistors are contained within
the IC. Now all resistors have identical TCs, all are
at virtually the same temperature, and any thermal
gradients across the chip are very small, and gain error drift
is guaranteed and specifed to very high standards.
At a gain of 10, the AD621 has a guaranteed maximum
dc offset shift of less than 2.5 V/`C and a maximum gain
drift of 5 ppm/C, which is only 0.0005 %/`C.
The AD8225 is an in-amp with a fxed gain of 5. It has
a maximum offset shift of 2 V/`C and a maximum drift
of 0.3 V/`C.
RTI AND RTO ERRORS
Another important design consideration is how circuit
gain affects many in-amp error sources such as dc offset
and noise. An in-amp should be regarded as a two stage
amplifer with both an input and an output section. Each
section has its own error sources.
Because the errors of the output section are multiplied
by a fxed gain (usually 2), this section is often the
principal error source at low circuit gains. When the
in-amp is operating at higher gains, the gain of the
input stage is increased. As the gain is raised, errors
contributed by the input section are multiplied, while
output errors are not. So, at high gains, the input stage
errors dominate.
5-8
Since device specifcations on different data sheets often
refer to different types of errors, it is very easy for the
unwary designer to make an inaccurate comparison
between products. Any (or several) of four basic error
categories may be listed: input errors, output errors, total
error RTI, and total error RTO. Here follows an attempt
to list, and hopefully simplify, an otherwise complicated
set of defnitions.
Input errors are those contributed by the amplifers input
stage alone; output errors are those due to the output
section. Input related specifcations are often combined
and classifed together as a referred to input (RTI) error,
while all output related specifcations are considered
referred to output (RTO) errors.
For a given gain, an in-amps input and output errors
can be calculated using the following formulas:
Total Error, RTI = Input Error + (Output Error/Gain)
Total Error, RTO = (Gain Input Error) + Output Error
Sometimes the spec page will list an error term as RTI
or RTO for a specifed gain. In other cases, it is up to the
user to calculate the error for the desired gain.
Offset Error
Using the AD620A as an example, the total voltage
offset error of this in-amp when operating at a gain of
10 can be calculated using the individual errors listed on
its specifcations page. The (typical) input offset of the
AD620 (V
OSI
) is listed as 30 V. Its output offset (V
OSO
)
is listed as 400 V. Thus, the total voltage offset referred
to input, RTI, is equal to
Total RTI Error = V
OSI
+ (V
OSO
/G) = 30 V + (400 V/10)
= 30 V + 40 V = 70 V
The total voltage offset referred to the output, RTO, is
equal to
Total Offset Error RTO = (G (V
OSI
)) + V
OSO
= (10 (30 V))
+ 400 V = 700 V
Note that the two error numbers (RTI vs. RTO) are 10
in value and logically they should be, as at a gain of 10,
the error at the output of the in-amp should be 10 times
the error at its input.
Noise Errors
In-amp noise errors also need to be considered in a
similar way. Since the output section of a typical 3-op
amp in-amp operates at unity gain, the noise contribution
from the output stage is usually very small. But there
are 3-op amp in-amps that operate the output stage at
higher gains and 2-op amp in-amps regularly operate the
second amplifer at gain. When either section is operated
at gain, its noise is amplifed along with the input signal.
Both RTI and RTO noise errors are calculated the same
way as offset errors, except that the noise of two sections
adds as the root mean square. That is
Input Noise eni Output Noise eno
Total Noise RTI eni eno Gain
Total Noise RTO Gain eni eno
= =
= ( ) + ( )
= ( ) ( )
+ ( )
,
2 2
2
2
For example, the (typical) noise of the AD620A
is specified as 9 nV/Hz eni and 72 nV/Hz eno.
Therefore, the total RTI noise of the AD620A operating
at a gain of 10 is equal to
Total Noise RTI eni eno Gain = ( ) + ( ) =
( ) + ( ) =
2 2
2 2
9 72 10 11 5 . nV Hz
REDUCING RFI RECTIFICATION ERRORS IN
IN-AMP CIRCUITS
Real world applications must deal with an ever
increasing amount of radio frequency interference
(RFI). Of particular concern are situations in which
signal transmission lines are long and signal strength is
low. This is the classic application for an in-amp since
its inherent common-mode rejection allows the device
to extract weak differential signals riding on strong
common-mode noise and interference.
One potential problem that is frequently overlooked,
however, is that of radio frequency rectifcation inside
the in-amp. When strong RF interference is present, it
may become rectifed by the IC and then appear as a dc
output offset error. Common-mode signals present at
an in-amps input are normally greatly reduced by the
amplifers common-mode rejection.
Unfortunately, RF rectifcation occurs because even the
best in-amps have virtually no common-mode rejec-
tion at frequencies above 20 kHz. A strong RF signal
may become rectifed by the amplifers input stage
and then appear as a dc offset error. Once rectifed,
no amount of low-pass fltering at the in-amp output
will remove the error. If the RF interference is of an
intermittent nature, this can lead to measurement
errors that go undetected.
Designing Practical RFI Filters
The best practical solution is to provide RF attenuation
ahead of the in-amp by using a differential low-pass
flter. The flter needs to do three things: remove as much
RF energy from the input lines as possible, preserve
the ac signal balance between each line and ground
5-9
(common), and maintain a high enough input imped-
ance over the measurement bandwidth to avoid loading
the signal source.
Figure 5-13 provides a basic building block for a wide
number of differential RFI flters. Component values
shown were selected for the AD8221, which has a typical
3 dB bandwidth of 1 MHz and a typical voltage noise
level of 7 nV/Hz. In addition to RFI suppression, the
flter provides additional input overload protection, as
resistors R1a and R1b help isolate the in-amps input
circuitry from the external signal source.
Figure 5-14 is a simplifed version of the RFI circuit. It
reveals that the flter forms a bridge circuit whose output
appears across the in-amps input pins. Because of this,
any mismatch between the time constants of C1a/R1a
and C1b/R1b will unbalance the bridge and reduce high
frequency common-mode rejection. Therefore, resistors
R1a and R1b and capacitors C1a and C1b should always
be equal.
As shown, C2 is connected across the bridge output so that
C2 is effectively in parallel with the series combination of
C1a and C1b. Thus connected, C2 very effectively reduces
any ac CMR errors due to mismatching. For example, if
C2 is made 10 times larger than C1, this provides a 20
reduction in CMR errors due to C1a/C1b mismatch.
Note that the flter does not affect dc CMR.
The RFI flter has two different bandwidths: differential
and common mode. The differential bandwidth defnes
the frequency response of the flter with a differential input
signal applied between the circuits two inputs, +IN and
IN. This RC time constant is established by the sum of
the two equal-value input resistors (R1a, R1b), together
with the differential capacitance, which is C2 in parallel
with the series combination of C1a and C1b.
The 3 dB differential bandwidth of this filter is
equal to
BW
R C C
DIFF
=
+ ( )
1
2 2 2 1
+

+IN
RFI FILTER
IN
C1a
1000pF
C2
0.01F
C1b
1000pF
1
2
R
G
3
4 5
6
7
8
REF
V
OUT AD8221
G = 1+
49.4k
R
G
V
S
0.01F 0.33F
0.01F 0.33F
+V
S
R1a
4.02k
R1b
4.02k
Figure 5-13. LP Filter Circuit Used to Prevent RFI Rectifcation Errors
C1a
C1b
C2
R1a
R1b
+IN
IN
V
OUT IN-AMP
Figure 5-14. Capacitor C2 Shunts C1a/C1b and Very Effectively Reduces AC CMR Errors Due to
Component Mismatching
5-10
The common-mode bandwidth defnes what a com-
mon-mode RF signal sees between the two inputs tied
together and ground. Its important to realize that C2
does not affect the bandwidth of the common-mode
RF signal, as this capacitor is connected between the
two inputs (helping to keep them at the same RF signal
level). Therefore, common-mode bandwidth is set by the
parallel impedance of the two RC networks (R1a/C1a
and R1b/C1b) to ground.
The 3 dB common-mode bandwidth is equal to
BW
R C
CM
=
1
2 1 1
Using the circuit of Figure 5-13, with a C2 value of
0.01 F as shown, the 3 dB differential signal bandwidth
is approximately 1,900 Hz. When operating at a gain of
5, the circuits measured dc offset shift over a frequency
range of 10 Hz to 20 MHz was less than 6 V RTI. At
unity gain, there was no measurable dc offset shift.
The RFI flter should be built using a PC board with
ground planes on both sides. All component leads should
be made as short as possible. The input flter common
should be connected to the amplifer common using the
most direct path. Avoid building the flter and the in-amp
circuits on separate boards or in separate enclosures, as
this extra lead length can create a loop antenna. Instead,
physically locate the flter right at the in-amps input
terminals. A further precaution is to use good quality
resistors that are both noninductive and nonthermal (low
TC). Resistors R1 and R2 can be common 1% metal flm
units. However, all three capacitors need to be reasonably
high Q, low loss components. Capacitors C1a and C1b
need to be 5% tolerance devices to avoid degrading
the circuits common-mode rejection. The traditional 5%
silver micas, miniature size micas, or the new Panasonic
2% PPS flm capacitors (Digi-key part # PS1H102G-
ND) are recommended.
Selecting RFI Input Filter Component Values Using
a Cookbook Approach
The following general rules will greatly ease the design
of an RC input flter.
1. First, decide on the value of the two series resis-
tors while ensuring that the previous circuitry can
adequately drive this impedance. With typical values
between 2 kU and 10 kU, these resistors should not
contribute more noise than that of the in-amp itself.
Using a pair of 2 kU resistors will add a Johnson noise
of 8 nV/Hz; this increases to 11 nV/Hz with 4 kU
resistors and to 18 nV/Hz with 10 kU resistors.
2. Next, select an appropriate value for capacitor C2,
which sets the flters differential (signal) bandwidth.
Its always best to set this as low as possible without
attenuating the input signal. A differential bandwidth
of 10 times the highest signal frequency is usually
adequate.
3. Then select values for capacitors C1a and C1b, which
set the common-mode bandwidth. For decent ac
CMR, these should be 10% the value of C2 or less.
The common-mode bandwidth should always be less
than 10% of the in-amps bandwidth at unity gain.
Specifc Design Examples
An RFI Circuit for AD620 Series In-Amps
Figure 5-15 is a circuit for general-purpose in-amps such
as the AD620 series, which have higher noise levels
(12 nV/Hz) and lower bandwidths than the AD8221.
+

+IN
RFI FILTER
IN
C1a
1000pF
C2
0.047F
C1b
1000pF
3
1
R
G
8
2 4
5
6
7
REF
V
OUT AD620
V
S
0.01F 0.33F
0.01F 0.33F
+V
S
R1a
4.02k
R1b
4.02k
Figure 5-15. RFI Circuit for AD620 Series In-Amp
5-11
+

+IN
RFI FILTER
IN
C1a
1000pF
C2
0.022F
C1b
1000pF
3
1
R
G
8
2 4
5
6
7
REF
V
OUT AD627
V
S
0.01F 0.33F
0.01F 0.33F
+V
S
20k
20k
Figure 5-16. RFI Suppression Circuit for the AD627
Accordingly, the same input resistors were used but
capacitor C2 was increased approximately fve times
to 0.047 F to provide adequate RF attenuation. With
the values shown, the circuits 3 dB bandwidth is ap-
proximately 400 Hz; the bandwidth may be increased
to 760 Hz by reducing the resistance of R1 and R2
to 2.2 kU. Note that this increased bandwidth does not
come free. It requires the circuitry preceding the in-amp
to drive a lower impedance load and results in somewhat
less input overload protection.
An RFI Circuit for Micropower In-Amps
Some in-amps are more prone to RF rectifcation than
others and may need a more robust flter. A micropower
in-amp, such as the AD627, with its low input stage
operating current, is a good example. The simple
expedient of increasing the value of the two input
resistors, R1a/R1b, and/or that of capacitor C2, will
provide further RF attenuation, at the expense of a
reduced signal bandwidth.
Since the AD627 in-amp has higher noise (38 nV/Hz)
than general-purpose ICs such as the AD620 series
devices, higher value input resistors can be used without
seriously degrading the circuits noise performance.
The basic RC RFI circuit of Figure 5-13 was modifed
to include higher value input resistors, as shown in
Figure 5-16.
The flter bandwidth is approximately 200 Hz. At a gain
of 100, the maximum dc offset shift with a 1 V p-p input
applied is approximately 400 V RTI over an input range
of 1 Hz to 20 MHz. At the same gain, the circuits RF
signal rejection (RF level at output/RF applied to the
input) will be better than 61 dB.
5-12
An RFI Filter for the AD623 In-Amp
Figure 5-17 shows the recommended RFI circuit for
use with the AD623 in-amp. Because this device is less
prone to RFI than the AD627, the input resistors can
be reduced in value from 20 kU to 10 kU; this increases
the circuits signal bandwidth and lowers the resistors
noise contribution. Moreover, the 10 kU resistors still
provide very effective input protection. With the values
shown, the bandwidth of this flter is approximately
400 Hz. Operating at a gain of 100, the maximum dc
offset shift with a 1 V p-p input is less than 1 V RTI.
At the same gain, the circuits RF signal rejection is
better than 74 dB.
AD8225 RFI Filter Circuit
Figure 5-18 shows the recommended RFI flter for this
in-amp. The AD8225 in-amp has a fxed gain of 5 and a
bit more susceptibility to RFI than the AD8221. Without
the RFI flter, with a 2 V p-p, 10 Hz to 19 MHz sine wave
applied, this in-amp measures about 16 mV RTI of dc
offset. The flter used provides a heavier RF attenuation
than that of the AD8221 circuit by using larger resistor
values: 10 kU instead of 4 kU. This is permissible because
of the AD8225s higher noise level. Using the flter, there
was no measurable dc offset error.
+

+IN
RFI FILTER
IN
C1a
1000pF
C2
0.022F
C1b
1000pF
3
1
R
G
8
2 4
5
6
7
REF
V
OUT AD623
V
S
0.01F 0.33F
0.01F 0.33F
+V
S
10k
10k
Figure 5-17. AD623 RFI Suppression Circuit
+

+IN
RFI FILTER
IN
C1a
1000pF
C2
0.01F
C1b
1000pF
2
3 4
5
6
7
REF
V
OUT AD8225
V
S
0.01F 0.33F
0.01F 0.33F
+V
S
10k
10k
Figure 5-18. AD8225 RFI Filter Circuit
5-13
Common-Mode Filters Using X2Y

Capacitors*
Figure 5-19 shows the connection diagram for an X2Y
capacitor. These are very small, three terminal devices
with four external connectionsA, B, G1, and G2. The
G1 and G2 terminals connect internally within the device.
The internal plate structure of the X2Y capacitor forms
an integrated circuit with very interesting properties. Elec-
trostatically, the three electrical nodes form two capacitors
that share the G1 and G2 terminals. The manufactur-
ing process automatically matches both capacitors very
closely. In addition, the X2Y structure includes an effec-
tive autotransformer/common-mode choke. As a result,
when these devices are used for common-mode flters,
they provide greater attenuation of common-mode signals
above the flters corner frequency than a comparable RC
flter. This usually allows the omission of capacitor C2,
with subsequent savings in cost and board space.

Figure 5-19. X2Y Electrostatic Model

Figure 5-20a illustrates a conventional RC common-
mode flter, while Figure 5-20b shows a common-mode
flter circuit using an X2Y device. Figure 5-21 is a
graph contrasting the RF attenuation provided by
these two flters.

Figure 5-21. RFI Attenuation, X2Y vs.
Conventional RC Common-Mode Filter

Figure 5-20a. Conventional RC Common-Mode Filter

Figure 5-20b. Common-Mode Filter Using X2Y Capacitor

*C1 is part number 500X14W103KV4. X2Y components may be purchased from Johanson Dielectrics, Sylmar, CA 91750, (818) 364-9800. For a full
listing of X2Y manufacturers visit: http://www.x2y.com/manufacturers.
5-14
Using Common-Mode RF Chokes for In-Amp
RFI Filters
As an alternative to using an RC input flter, a commercial
common-mode RF choke may be connected in front of
an in-amp, as shown in Figure 5-22. A common-mode
choke is a two-winding RF choke using a common core.
Any RF signals that are common to both inputs will
be attenuated by the choke. The common-mode choke
provides a simple means for reducing RFI with a mini-
mum of components and provides a greater signal pass
band, but the effectiveness of this method depends on
the quality of the particular common-mode choke being
used. A choke with good internal matching is preferred.
Another potential problem with using the choke is that
there is no increase in input protection as is provided by
the RC RFI flters.
Using an AD620 in-amp with the RF choke specifed,
at a gain of 1,000, and a 1 V p-p common-mode sine
wave applied to the input, the circuit of Figure 5-22
reduces the dc offset shift to less than 4.5 V RTI. The
high frequency common-mode rejection ratio was also
greatly improved, as shown in Table 5-3.
Table 5-3. AC CMR vs. Frequency
Using the Circuit of Figure 5-22
Frequency CMRR (dB)
100 kHz 100
333 kHz 83
350 kHz 79
500 kHz 88
1 MHz 96
+

+IN
PULSE
ENGINEERING
#B4001 COMMON-MODE
RF CHOKE
IN
R
G
REF
V
OUT
V
S
0.01F 0.33F
0.01F 0.33F
+V
S
IN-AMP
Figure 5-22. Using a Commercial Common-Mode RF Choke for RFI Suppression
5-15
Because some in-amps are more susceptible to RFI than
others, the use of a common-mode choke may sometimes
prove inadequate. In these cases, an RC input flter is
a better choice.
RFI TESTING
Figure 5-23 shows a typical setup for measuring RFI
rejection. To test these circuits for RFI suppression,
connect the two input terminals together using very short
leads. Connect a good quality sine wave generator to this
input via a 50 V terminated cable.
Using an oscilloscope, adjust the generator for a 1 V
peak-to-peak output at the generator end of the cable.
Set the in-amp to operate at high gain (such as a gain
of 100). DC offset shift is simply read directly at the
in-amps output using a DVM. For measuring high
frequency CMR, use an oscilloscope connected to the
in-amp output by a compensated scope probe and measure
the peak-to-peak output voltage (i.e., feedthrough) vs.
input frequency. When calculating CMRR vs. frequency,
remember to take into account the input termination
(V
IN
/2) and the gain of the in-amp.
CMRR
V
V
Gain
IN
OUT
=

20
2
log
USING LOW-PASS FILTERING TO IMPROVE
SIGNAL-TO-NOISE RATIO
To extract data from a noisy measurement, low-pass fl-
tering can be used to greatly improve the signal-to-noise
ratio of the measurement by removing all signals that are
not within the signal bandwidth. In some cases, band-pass
fltering (reducing response both below and above the
signal frequency) can be employed for an even greater
improvement in measurement resolution.
+

TERMINATION
RESISTOR
(50 OR 75 TYPICAL)
RF
SIGNAL
GENERATOR
R
G
REF
V
OUT
TO
SCOPE OR DVM
IN-AMP
V
S
0.01F 0.33F
0.01F 0.33F
+V
S
RFI
INPUT
FILTER
Figure 5-23. Typical Test Setup for Measuring an In-Amps RFI Rejection
5-16
The 1 Hz, 4-pole active flter of Figure 5-24 is an example
of a very effective low-pass flter that normally would be
added after the signal has been amplifed by the in-amp.
This flter provides high dc precision at low cost while
requiring a minimum number of components.
Note that component values can simply be scaled
to provide corner frequencies other than 1 Hz (see
Table 5-4). If a 2-pole filter is preferred, simply take
the output from the frst op amp.
Table 5-4. Recommended Component Values for a 1 Hz, 4-Pole Low-Pass Filter
Section 1 Section 2
Desired Low- Frequency Frequency C1 C2 C3 C4
Pass Response (Hz) Q (Hz) (Q) (F) (F) (F) (F)
Bessel 1.43 0.522 1.60 0.806 0.116 0.107 0.160 0.0616
Butterworth 1.00 0.541 1.00 1.31 0.172 0.147 0.416 0.0609
0.1 dB Chebychev 0.648 0.619 0.948 2.18 0.304 0.198 0.733 0.0385
0.2 dB Chebychev 0.603 0.646 0.941 2.44 0.341 0.204 0.823 0.0347
0.5 dB Chebychev 0.540 0.705 0.932 2.94 0.416 0.209 1.00 0.0290
1.0 dB Chebychev 0.492 0.785 0.925 3.56 0.508 0.206 1.23 0.0242
The low levels of current noise, input offset, and input
bias currents in the quad op amp (either an AD704 or
OP497) allow the use of 1 MU resistors without sacrifcing
the 1 V/`C drift of the op amp. Thus, lower capacitor
values may be used, reducing cost and space.
Furthermore, since the input bias current of these op
amps is as low as their input offset currents over most
of the MIL temperature range, there is rarely a need to
use the normal balancing resistor (along with its noise-
reducing bypass capacitor). Note, however, that adding
the optional balancing resistor will enhance performance
at temperatures above 100`C.
1/2 AD706
1/2 OP297
1/2 AD706
1/2 OP297
2M
R
10
0.01F
OUTPUT
2M
0.01F
C
3
1M 1M
R
6
R
7
C
4
1M 1M
R
8
R
9
CAPACITORS C
2
C
4
ARE
SOUTHERN ELECTRONICS
MPCC, POLYCARBONATE,
5%, 50V
OPTIONAL BALANCE
RESISTOR NETWORKS
CAN BE REPLACED
WITH A SHORT
R
6
= R
7
Q
1
=
C
1
4C
2
W =
1
R
6
C
1
C
2
R
10
C
1
C
2
C
5
A1, A2 ARE AD706 OR OP297
R
8
= R
9
Q
2
=
C
3
4C
4
W =
1
R
8
C
3
C
4
C
5
INPUT
Figure 5-24. A 4-Pole Low-Pass Filter for Data Acquisition
5-17

Figure 5-25. External DC and AC CMRR Trim Circuit for a Discrete 3-Op Amp In-Amp
Specifed values are for a 3 dB point of 1.0 Hz. For other
frequencies, simply scale capacitors C1 through C4 di-
rectly; i.e., for 3 Hz Bessel response, C1 = 0.0387 F, C2
= 0.0357 F, C3 = 0.0533 F, and C4 = 0.0205 F.
EXTERNAL CMR AND SETTLING TIME
ADJUSTMENTS
When a very high speed, wide bandwidth in-amp is
needed, one common approach is to use several op
amps or a combination of op amps and a high band-
width subtractor amplifer. These discrete designs may be
readily tuned-up for best CMR performance by external
trimming. A typical circuit is shown in Figure 5-25. The
dc CMR should always be trimmed frst, since it affects
CMRR at all frequencies.
The +V
IN
and V
IN
terminals should be tied together
and a dc input voltage applied between the two inputs
and ground. The voltage should be adjusted to provide
a 10 V dc input. A dc CMR trimming potentiometer
would then be adjusted so that the outputs are equal and
as low as possible, with both a positive and a negative
dc voltage applied.
AC CMR trimming is accomplished in a similar
manner, except that an ac input signal is applied.
The input frequency used should be somewhat lower
than the 3 dB bandwidth of the circuit.
The input amplitude should be set at 20 V p-p with
the inputs tied together. The ac CMR trimmer is then
nulled-set to provide the lowest output possible. If the best
possible settling time is needed, the ac CMR trimmer
may be used, while observing the output wave form
on an oscilloscope. Note that, in some cases, there will
be a compromise between the best CMR and the fastest
settling time.
6-1
Composite In-Amp Circuit Has Excellent High
Frequency CMR
The primary benefit of an in-amp circuit is that it
provides common-mode rejection. While the AD8221
and AD8225 both have an extended CMR frequency
range, most in-amps fail to provide decent CMR at
frequencies above the audio range.
The circuit in Figure 6-1 is a composite instrumentation
amplifer with a high common-mode rejection ratio. It
features an extended frequency range over which the
instrumentation amplifer has good common-mode
rejection (Figure 6-2). The circuit consists of three in-
strumentation amplifers. Two of these, U1 and U2, are
correlated to one another and connected in antiphase. It
is not necessary to match these devices because they are
correlated by design. Their outputs, OUT1 and OUT2,
drive a third instrumentation amplifer that rejects com-
mon-mode signals and amplifers differential signals.
The overall gain of the system can be determined by
adding external resistors. Without any external resistors,
the system gain is 2 (Figure 6-3). The performance of the
circuit with a gain of 100 is shown in Figure 6-4.

Figure 6-1. A Composite Instrumentation Amplifer

Chapter VI
IN-AMP AND DIFF AMP APPLICATIONS CIRCUITS
VCM
COMMON-MODE
SIGNAL,
3.5V p-p @ 20kHz
(1V/DIV)
UNCORRECTED
CMRR ERROR
(10mV/DIV)
OUTPUT SIGNAL
(1mV/DIV)
OUT1
OUT3
Figure 6-2. CMR of the Circuit in Figure 6-1 at 20 kHz
FREQUENCY (Hz)
C
M
R
R
(
d
B
)
90
80
100 1k 10k 100k
70
60
50
40
OUT3
OUT1
Figure 6-3. CMRR vs. Frequency at a Gain of 2
6-2
+15V
+15V
15V
15V
10F 0.1F
10F 0.1F
AD8221
REF
+IN
IN
49.9
350
350 350
350
CHB
SEL B
CHA
SEL A
R
A
R
F
R
IN
A
R
IN
B
V
S
+15V
V
OUT
+V
S
COMP
AD630AR
OP1177
12
13
1 8
R
B
14 10
17
16
15
19
20
9 11
15V
4.99k 4.99k 4.99k
2F 2F 2F
Figure 6-6. Using an AC Signal to Excite the Bridge
FREQUENCY (Hz)
C
M
R
R
(
d
B
)
115
105
95
85
100 1k 10k 100k
75
OUT3
OUT1
Figure 6-4. CMR of the System at a Gain of 100
Since U1 and U2 are correlated, their common-mode
errors are the same. Therefore, these errors appear as
common-mode input signal to U3, which rejects
them. In fact, if it is necessary, OUT1 and OUT2 can
directly drive an analog-to-digital converter (ADC).
The differential-input stage of the ADC will reject the
common-mode signal, as seen in Figure 6-5.
U1
AD623
+

+V
S
V
S
REF
U2
AD623
+

+V
S
V
S
REF
+IN
IN
+V
S
V
S
OUT1
GND
V
REF
AD7825
OUT2
+
V
DM
+
V
CM
DIGITAL
DATA
OUTPUT
Figure 6-5. The OUT1 and OUT2 signals of
the frst stage can directly drive an analog-
to-digital converter, allowing the ADC to
reject the common-mode signal.
STRAIN GAGE MEASUREMENT USING AN
AC EXCITATION
Strain gage measurements are often plagued by offset
drift, 1/f noise, and line noise. One solution is to use an
ac signal to excite the bridge, as shown in Figure 6-6. The
AD8221 gains the signal and an AD630AR synchronously
demodulates the waveform. What results is a dc output
proportional to the strain on the bridge. The output
signal is devoid of all dc errors associated with the in-amp
and the detector, including offset and offset drift.
6-3
C1
IN
IN
V
S
A2
V
OUT
TO ADC
A1
V
IN
V
CM
100k
10k
10k
15V
0.1F
100k
V
REF
R
G
R
G
R
F
C
FILTER
10k
AD628
8
1
2 3 6
4 7
5
+

IN
IN

+
+15V
0.1F
+V
S
DIFFERENTIAL
INPUT SIGNAL
Figure 6-7. Basic Differential Input Connection with Single-Pole LP Filter
In Figure 6-6, a 400 Hz signal excites the bridge. The
signal at the AD8221s input is an ac voltage. Similarly,
the signal at the input of the AD630 is ac; the signal is dc
at the end of the low-pass flter following the AD630.
The 400 Hz ac signal is rectifed and then averaged; dc
errors are converted in an ac signal and removed by the
AD630. Ultimately, a precision dc signal is obtained.
The AD8221 is well suited for this application because
its high CMRR over frequency ensures that the signal
of interest, which appears as a small difference voltage
riding on a large sinusoidal common-mode voltage, is
gained and the common-mode signal is rejected. In
typical instrumentation amplifers, CMRR falls off at
about 200 Hz. In contrast, the AD8221 continues to
reject common-mode signals beyond 10 kHz.
If an ac source is not available, a commutating voltage
may be constructed using switches. The AD8221s high
CMRR over frequency rejects high frequency harmonics
from a commutating voltage source.
APPLICATIONS OF THE AD628 PRECISION
GAIN BLOCK
The AD628 can be operated as either a differential/scaling
amplifer or as a pin-strapped precision gain block.
Specifcally designed for use ahead of an analog-to-digital
converter, the AD628 is extremely useful as an input
scaling and buffering amplifer. As a differential amplifer,
it can extract small differential voltages riding on large
common-mode voltages up to 120 V. As a prepack-
aged precision gain block, the pins of the AD628 can
be strapped to provide a wide range of precision gains,
allowing for high accuracy data acquisition with very
little gain or offset drift.
The AD628 uses an absolute minimum of external com-
ponents. Its tiny MSOP provides these functions in the
smallest size package available on the market. Besides
high gain accuracy and low drift, the AD628 provides a
very high common-mode rejection, typically more than
90 dB at 1 kHz while still maintaining a 60 dB CMRR
at 100 kHz.
The AD628 includes a V
REF
pin to allow a dc (midscale)
offset for driving single-supply ADCs. In this case, the
V
REF
pin may simply be tied to the ADCs reference pin,
which also allows easy ratiometric operation.
Why Use a Gain Block IC?
Real-world measurement requires extracting weak signals
from noisy sources. Even when a differential measurement
is made, high common-mode voltages are often present.
The usual solution is to use an op amp or, better still, an
in-amp, and then perform some type of low-pass fltering
to reduce the background noise level.
The problem with this traditional approach is that a
discrete op amp circuit will have poor common-mode
rejection and its input voltage range will always be less than
the power supply voltage. When used with a differential
signal source, an in-amp circuit using a monolithic IC
will improve common-mode rejection. However, signal
sources greater than the power supply voltage, or signals
riding on high common-mode voltages, cannot handle
6-4
IN
IN
V
S
A2
V
OUT
TO ADC
A1
V
IN
V
CM
100k
10k
10k
15V
0.1F
100k
V
REF
R
G
C
FILTER
10k
AD628
8
1
2 3 6
4 7
5
+

IN
IN

+
+15V
0.1F
+V
S
R
G
DIFFERENTIAL
INPUT SIGNAL
Figure 6-8. AD628 Connection for Gains Less Than 0.1
standard in-amps. In addition, in-amps using a single
external gain resistor suffer from gain drift. Finally, low-
pass fltering usually requires the addition of a separate
op amp, along with several external components. This
drains valuable board space.
The AD628 eliminates these common problems by
functioning as a scaling amplifer between the sensor,
the shunt resistor, or another point of data acquisition,
as well as the ADC. Its 120 V max input range permits
the direct measurement of large signals or small signals
riding on large common-mode voltages.
Standard Differential Input ADC Buffer Circuit
with Single-Pole LP Filter
Figure 6-7 shows the AD628 connected to accept a
differential input signal riding on a very high com-
mon-mode voltage. The AD628 gain block has two
internal amplifers: A1 and A2. Pin 3 is grounded, thus
operating amplifer A1 at a gain of 0.1. The 100 kU
input resistors and other aspects of its design allow
the AD628 to process small input signals riding on
common-mode voltages up to 120 V.
The output of A1 connects to the plus input of amplifer
A2 through a 10 kU resistor. Pin 4 allows connecting an
external capacitor to this point, providing single-pole
low-pass fltering.
Changing the Output Scale Factor
Figure 6-7 reveals that the output scale factor of the
AD628 may be set by changing the gain of amplifer
A2. This uncommitted op amp may be operated at any
convenient gain higher than unity. When confgured, the
AD628 may be set to provide circuit gains between 0.1
and 1,000.
Since the gain of A1 is 0.1, the combined gain of A1
and A2 equals
V
V
G R R
OUT
IN
F G
= = +
( ) ( )
0 1 1 .
Therefore
10 1 G
R
R
F
G
( ) =
For ADC buffering applications, the gain of A2 should
be chosen so that the voltage driving the ADC is close
to its full-scale input range. The use of external resistors,
R
F
and R
G
to set the output scale factor (i.e., gain of A2)
will degrade gain accuracy and drift essentially to the
resistors themselves.
A separate V
REF
pin is available for offsetting the AD628
output signal, so it is centered in the middle of the ADCs
input range. Although Figure 6-7 indicates 15 V, the
circuit may be operated from 2.25 V to 18 V dual
supplies. This V
REF
pin may also be used to allow single-
supply operation; V
REF
may simply be biased at V
S
/2.
Using an External Resistor to Operate the AD628 at
Gains Below 0.1
The AD628 gain block may be modifed to provide any
desired gain from 0.01 to 0.1, as shown in Figure 6-8.
6-5
C2
IN
IN
V
S
A2
V
OUT
TO ADC
A1
V
IN
V
CM
100k
10k
10k
15V
0.1F
100k
V
REF
R
G
R
G
R
F
C
FILTER
10k
AD628
8
1
2 3 6
4 7
5
+

IN
IN

+
+15V
0.1F
C1
0.1F
+V
S
DIFFERENTIAL
INPUT SIGNAL
Figure 6-9. Differential Input Circuit with Two-Pole Low-Pass Filtering
This connection is the same as the basic wide input range
circuit of Figure 6-7, but with Pins 5 and 6 strapped,
and with an external resistor, R
G
, connection between
Pin 4 and ground. The pin strapping operates amplifer
A2 at unity gain. Acting with the on-chip 10 kU resistor
at the output of A1, R
GAIN
forms a voltage divider that
attenuates the signal between the output of A1 and the
input of A2. The gain for this connection equals 0.1 V
IN
((10 kU + R
G
)/R
G
).
Differential Input Circuit with Two-Pole
Low-Pass Filtering
The circuit in Figure 6-9 is a modifcation of the basic
ADC interface circuit. Here, two-pole low-pass fltering
is added for the price of one additional capacitor (C2).
As before, the frst pole of the low-pass flter is set by
the internal 10 kU resistor at the output of A1 and the
external capacitor C1. The second pole is created by an
external RC time constant in the feedback path of A2,
consisting of capacitor C2 across resistor R
F
. Note that
this second pole provides a more rapid roll-off of fre-
quencies above its RC corner frequency (1/(2rRC)) than
a single-pole LP flter. However, as the input frequency
is increased, the gain of amplifer A2 eventually drops
to unity and will not be further reduced. So, amplifer
A2 will have a voltage gain set by the ratio of R
F
/R
G
at
frequencies below its 3 dB corner and have unity gain
at higher frequencies.

Figure 6-10. Frequency Response of the
Two-Pole LP Filter
Figure 6-10 shows the flters output vs. frequency using
components chosen to provide a 200 Hz 3 dB corner
frequency. There is a sharp roll-off between the corner
frequency and approximately 10 the corner frequency.
Above this point, the second pole starts to become less
effective and the rate of attenuation is close to that of a
single-pole response.
6-6
IN
IN
V
S
A2
V
OUT
A1
100k
10k
10k
15V
0.1F
100k
V
REF
V
IN
R
G
C
FILTER
AD628
8
1
2 3 6
4 7
5
+

IN
IN

+
+15V
0.1F
+V
S
10k
Figure 6-11. Circuit with a Gain of +10 Using No External Components
Table 6-1.
Two-Pole LP Filter
Input Range: 10 V p-p F.S. for a 5 V p-p Output
R
F
= 49.9 kU, R
G
= 12.4 kU
3 dB Corner Frequency
200 Hz 1 kHz 5 kHz 10 kHz
Capacitor C2 0.01 F 0.002 F 390 pF 220 pF
Capacitor C1 0.047 F 0.01 F 0.002 F 0.001 F
Table 6-2.
Two-Pole LP Filter
Input Range: 20 V p-p F.S. for a 5 V p-p Output
R
F
= 24.3 kU, R
G
= 16.2 kU
3 dB Corner Frequency
200 Hz 1 kHz 5 kHz 10 kHz
Capacitor C2 0.02 F 0.0039 F 820 pF 390 pF
Capacitor C1 0.047 F 0.01 F 0.002 F 0.001 F
Tables 6-1 and 6-2 provide typical flter component
values for various 3 dB corner frequencies and two
different full-scale input ranges. Values have been
rounded off to match standard resistor and capacitor
values. Capacitors C1 and C2 need to be high Q, low
drift devices; low grade disc ceramics should be avoided.
High quality NPO ceramic, Mylar, or polyester flm
capacitors are recommended for the lowest drift and
best settling time.
Using the AD628 to Create Precision Gain Blocks
Real-world data acquisition systems require amplifying weak
signals enough to apply them to an ADC. Unfortunately,
when confgured as gain blocks, most common amplifers
have both gain errors and offset drift.
In op amp circuits, the usual two resistor gain setting
arrangement has accuracy and drift limitations. Using
standard 1% resistors, amplifer gain can be off by 2%.
The gain will also vary with temperature because each
resistor will drift differently. Monolithic resistor networks
can be used for precise gain setting, but these components
increase cost, complexity, and board space.
The gain block circuits of Figures 6-11 to 6-15 overcome
all of these performance limitations, are very inexpensive,
and offer a single MSOP solution. The AD628 provides
this complete function using the smallest IC package
available. Since all resistors are internal to the AD628
gain block, both accuracy and drift are excellent.
All of these pin-strapped circuits (using no external
components) have a gain accuracy better than 0.2%,
with a gain TC better than 50 ppm/C.
Operating the AD628 as a +10 or 10 Precision
Gain Block
Figure 6-11 shows an AD628 precision gain block IC
connected to provide a voltage gain of +10. The gain
block may be confgured to provide different gains by
strapping or grounding the appropriate pin. The gain
block itself consists of two internal amplifers: a gain of
0.1 difference amplifer (A1) followed by an uncommitted
buffer amplifer (A2).
The input signal is applied between the V
REF
pin (Pin 3)
and ground. With the input tied to Pin 3, the voltage at
the positive input of A1 equals V
IN
(100 kU/110 kU)
which is V
IN
(10/11). With Pin 6 grounded, the minus
6-7
IN
IN
V
S
A2
V
OUT
A1
100k
10k
10k
15V
0.1F
100k
V
REF
V
IN
R
G
C
FILTER
AD628
8
1
2 3 6
4 7
5
+

IN
IN

+
+15V
0.1F
+V
S
10k
Figure 6-12. Companion Circuit Providing a Gain of 10
IN
IN
V
S
A2
V
OUT
A1
100k
10k
10k
100k
V
REF
V
IN
R
G
C
FILTER
AD628
8
1
2 3 6
4 7
5
+

IN
IN

+
+V
S
10k
Figure 6-13. A Gain of +11 Circuit
input of A2 equals 0 V. Therefore, the positive input of
A2 will be forced by feedback from the output of A2 to
be 0 V as well. The output of A1 then must also be at
0 V. Since the negative input of A1 must be equal to the
positive input of A1, both will equal V
IN
(10/11).
This means that the output voltage of A2 (V
OUT
) will
equal
V V
V V
OUT IN
IN IN
= ( ) + ( ) =
( ) =
10 11 1 100 10
10 11 11 10
k k
The companion circuit in Figure 6-12 provides a gain of
10. This time the input is applied between the negative
input of A2 (Pin 6) and ground. Operation is exactly the
same, but now the input signal is inverted 180` by A2.
With Pin 3 grounded, the positive input of A1 is at 0 V,
so feedback will force the negative input of A1 to zero
as well. Since A1 operates at a gain of 1/10 (0.1), the
output of A2 that is needed to force the negative input
of A1 to zero is minus 10 V
IN
.
The two connections will have different input impedances.
When driving Pin 3 (Figure 6-11), the input impedance
to ground is 110 kU, while it is approximately 50 GU
when driving Pin 6 (Figure 6-12). The 3 dB bandwidth
for both circuits is approximately 110 kHz for 10 mV
and 95 kHz for 100 mV input signals.
Operating the AD628 at a Precision Gain of +11
The gain of +11 circuit (Figure 6-13) is almost identi-
cal to the gain of +10 connection, except that Pin 1 is
strapped to Pin 3, rather than being grounded. This
6-8
IN
IN
V
S
A2
V
OUT A1
100k
10k
10k
15V
0.1F
100k
V
REF
V
IN
R
G
C
FILTER
AD628 8
1
2 3 6
4 7
5
+

IN
IN

+
+15V
0.1F
+V
S
10k
Figure 6-14. AD628 Precision Gain of +1
IN
IN
V
S
A2
V
OUT
A1
100k
10k
10k
100k
V
REF
V
IN
R
G
C
FILTER
AD628
8
1
2 3 6
4 7
5
+

IN
IN

+
+V
S
10k
Figure 6-15. Precision 10 Gain Block with Feedforward
connects the two internal resistors (100 kU and 10 kU)
that are tied in parallel to the plus input of A1. So, this
now removes the 10 kU/110 kU voltage divider between
V
IN
and the positive input of A1. Thus modifed, V
IN
drives
the positive input through approximately a 9 kU resistor.
Note that this series resistance is negligible compared to
the very high input impedance of amplifer A1. The gain
from Pin 8 to the output of A1 is 0.1. Therefore, feedback
will force the output of A2 to equal 10 V
IN
. The 3 dB
bandwidth of this circuit is approximately 105 kHz for
10 mV and 95 kHz for 100 mV input signals.
Operating the AD628 at a Precision Gain of +1
Figure 6-14 shows the AD628 connected to provide a
precision gain of +1. As before, this connection uses
the gain blocks internal resistor networks for high gain
accuracy and stability.
The input signal is applied between the V
REF
pin
and ground. Because Pins 1 and 8 are grounded, the
input signal runs through a 100 kU/110 kU input at-
tenuator to the plus input of A1. The voltage equals V
IN

(10/11) = 0.909 V
IN
. The gain from this point to the
output of A1 will equal 1 + (10 kU/100 kU) = 1.10.
Therefore, the voltage at the output of A1 will equal
V
IN
(1.10) (0.909) = 1.00. Amplifer A2 is operated
as a unity gain buffer (as Pins 5 and 6 tied together),
providing an overall circuit gain of +1.
Increased BW Gain Block of 9.91 Using Feedforward
The circuit of Figure 6-12 can be modified slightly
by applying a small amount of positive feedback to
increase its bandwidth, as shown in Figure 6-15.
The output of amplifier A1 feeds back its positive
input by connecting Pin 4 and Pin 1 together. Now,
Gain = (10 1/11) = 9.91.
6-9
380k
380k
20k 21.1k
6
5 1
2
3
V
IN
VCM +15V
15V
GND1
AD629
R2
9k
OP27
R1
1k
R3
0.1k
R1
1k
GND2
V
OUT
GROUND INTERFERENCE
I
OUT
Figure 6-16. Current Transmitter
The resulting circuit is still stable because of the large
amount of negative feedback applied around the entire
circuit (from the output of A2 back to the negative
input of A1). This connection actually results in a small
signal 3 dB bandwidth of approximately 140 kHz. This
is a 27% increase in bandwidth over the unmodifed
circuit in Figure 6-9. However, gain accuracy is reduced
to 2%.
CURRENT TRANSMITTER REJECTS
GROUND NOISE
Many systems use current fow to control remote instru-
mentations. The advantage of such a system is its ability
to operate with two remotely connected power supplies,
even if their grounds are not the same. In such cases, it is
necessary for the output to be linear with respect to the
input signal, and any interference between the grounds
must be rejected. Figure 6-16 shows such a circuit.
For this circuit
I
V
OUT
IN
=
( ) 10
1k
I
V
OUT
IN
=
( ) V
k 1
The AD629, a difference amplifer with very high
common-mode range, is driven by an input signal Pin 3.
Its transfer function is
V V
OUT IN
=
Where:
V
OUT
is measured between Pin 6 and its reference
(Pin 1 and Pin 5), and the input V
IN
is measured
between Pin 3 and Pin 2. The common-mode signal,
VCM, will be rejected.
In order to reduce the voltage at Pin 6, an inverter
with a gain of 9 is connected between Pin 6 and its
reference. The inverter sets the gain of the transmitter
such that for a 10 V input, the voltage at Pin 6 only
changes by 1 V; yet, the difference between Pin 6 and
its reference is 10 V.
6-10
A1
A2
R3
10k
R4
100k
R2
100k
R1
10k
10k
13.3k
3.32k
3.32k
V1
AD7450
REFERENCE
5V
2.5V
V
R
V
B
V
A
PRECISION
REFERENCE
AD780
5V
8
3 6
6
IN
1 5
+IN OUT
A1
A2
R3
10k
R2
100k
R4
100k
10k
R1
10k
V2
1
+IN
8
IN
5
OUT
3
AD628
AD628
4
4
2
2
R
G
C
FLIT
V
S
V
REF
R
G
C
FLIT
V
S
V
REF
C
V
R
7
5V
V
S
7
5V
V
S
Figure 6-19. This ADC Interface Circuit Attenuates and Level Shifts a 10 V Differential
Signal While Operating from a Single 5 V Supply
Since the gain between the noninverting terminal of the
OP27 and the output of the AD629 is 1, no modulation
of the output current will take place as a function of the
output voltage V
OUT
. The scaling resistor R3 is 100 U to
make 1 mA/V of input signal.
OP27 was chosen because, at a noise gain of 10, its
bandwidth does not compromise the transmitter. Figure
6-17 is the transfer function of the output voltage V
OUT

vs. the input voltage V
IN
. Figure 6-18 is a demonstration
of how well the transmitter rejects ground noise.
5V 5V
HORIZONTAL: INPUT 5V/DIV
VERTICAL: OUTPUT 5mA/DIV
Figure 6-17. Transfer Function
2V 5ms 1mV
TOP: GROUND NOISE 2V/DIV
BOTTOM: V
OUT
ERROR AT FULL-SCALE 1A/DIV
Figure 6-18. Interference Rejection
HIGH LEVEL ADC INTERFACE
The circuit of Figure 6-19 provides an interface between
large level analog inputs as high as 10 V operating on
dual supplies and a low level, differential input ADC,
operating on a single supply.
As shown, two AD628 difference amplifiers are
connected in antiphase. The differential output, V
1
V
2
,
is an attenuated version of the input signal
V V
V V
A B
1 2
5
=
( )
6-11
The difference amplifers reject the common-mode
voltage on inputs V
A
and V
B
. The reference voltage,
V
R
, which the AD780 develops and the ADC and the
amplifer share, sets the output common-mode voltage.
A single capacitor, C, placed across the C
FILT
pins, low-
pass flters the difference signal, V
1
V
2
. The 3 dB pole
frequency is f
P
= 1/(40,000 r C). The difference
signal is amplifed by 1.5. Thus, the total gain of this
circuit is 3/10.
Figure 6-20 shows a 10 V input signal (top), the signals at
the output of each AD628 (middle), and the differential
output (bottom). The benefts of this confguration go
beyond simply interfacing with the ADC. The circuit
improves specifcations such as common-mode rejection
ratio, offset voltage, drift, and noise by a factor of 2
because the errors of each AD628 are not correlated.
Tek RUN: 50k SAMPLES/SEC HI RES
T
1
3
M1
T INPUT
20V p-p
SINGLE-ENDED
OUTPUTS
3V p-p
DIFFERENTIAL
OUTPUT
6V p-p
1ms/DIV
Figure 6-20. The Waveforms Show a 10 V
Input Signal (top), the Signals at the Output
of Each AD628 (middle), and the Differential
Output (bottom)
The output demonstrates an 85 dB SNR (Figure 6-21).
The two AD628s interface with an AD7450 12-bit,
differential-input ADC. The AD7450 easily rejects
residual common-mode signals at the output of the
difference amplifiers. Figure 6-22 shows the common-
mode error at the output of the AD628.
CH1 A SPECTRUM 12dB/REF 13dBV
0
85dBV
400Hz
Figure 6-21. The Circuit in Figure 6-19 has
an 85 dBV SNR
T
COMMON-MODE
ERROR OF
DIFFERENTIAL
OUTPUT
INPUT
20V p-p
COMMON-MODE
ERROR OF
COMMON-MODE
OUTPUT
T
20V p-p
200V p-p
80V p-p
Figure 6-22. The Common-Mode Input (top)
Measures 20 V p-p. The common-mode error of
the differential output (middle) is 20 V p-p. The
error of the common-mode output (bottom) is
80 V p-p.
The topmost waveform is a 10 V, common-mode input
signal. The middle waveform, measuring 150 V, is
the common-mode error measured differentially
from the output of the two AD628s. The bottom
waveform, measuring 80 V, is the common-mode
error that results.
A HIGH SPEED NONINVERTING SUMMING
AMPLIFIER
The schematic in Figure 6-23 is that of a common
summing amplifer with multiple inputs and one single-
ended output. It is a variation of an inverting amplifer.
Point X is a virtual ground and referred to as a summing
junction. The transfer function for this circuit is
V RF R V RF R V RF R V
O
= ( ) + ( ) + ( )
[ ]
1 1 2 2 3 3
6-12
VO
R1
I1
V1
R2
I2
V2
R3
I3
V3
X
RF
IF
Figure 6-23. A Traditional Summing Amplifer
This indicates that the output is a weighted sum of the
inputs with the weights being determined by the resis-
tance ratio. If all resistances are equal, the circuit yields
the inverted sum of its inputs.
V V V V
O
= + + ( ) 1 2 3
Note that if we want the result V
O
= (V1 + V2 + V3), we
need an additional inverter with Gain = 1. Further-
more, this circuit has many disadvantages, such as low
input impedance, different input impedance for positive
and negative inputs, low bandwidth and highly matched
resistors are needed.
Figure 6-24 is the schematic of a high speed summing
amplifer, which can sum up as many as four input volt-
ages without the need for an inverter to change the sign
of the output. This could prove very useful in audio and
video applications. The circuit contains three low cost
high speed instrumentation amplifers. The frst two
interface with input signals and their total sum is taken
at the third amplifers output with respect to ground.
The inputs are very high impedance and the signal that
appears at the network output is noninverting.
Figure 6-25 is the performance photo at 1 MHz. The top
trace is the input signal for all four inputs. The middle
trace is the sum of inputs V1 and V2. The bottom trace
is the output of the system, which is the total sum of all
four inputs.
1
2
3
M 400ns 125MS/s
A CH1 40.0mV
CH1
CH3
1.0V CH2 1.0V
1.0V
8.0ns/pt
T
Figure 6-25. Performance Photo of the
Circuit in Figure 6-24
1
8
4
5
AD8130
VO1
V1
V2
6
1
8
4
5
AD8130
VO2
V3
V4
6
1
8
4
5
AD8130
VO
6
Figure 6-24. A Summing Circuit with High Input Impedance
6-13
Figure 6-26 demonstrates the high bandwidth of the
system in Figure 6-24. As we can see, the 3 dB point
is about 220 MHz.
FREQUENCY (MHz)
G
A
I
N
(
d
B
)
4
6
5
4
3
2
1
0
1
2
3
1 10 100 1k
P
S
= 5V
Figure 6-26. Frequency Response of
Summing Circuit in Figure 6-24
HIGH VOLTAGE MONITOR
A high accuracy, high voltage monitor is shown in
Figure 6-27.
AD629
380k
380k
6
380k
2
1
3
21.11k
V
IN
GND
20k
R1
100k 5
4
5V
7
+5V
OP177
C1
200pF
15V
+15V
V
OUT
2
3
7
4
6
Figure 6-27. High Voltage Monitor
An integrator (OP177) supplies negative feedback around
a difference amplifer (AD629), forcing its output to stay
at 0 V. The voltage divider on the inverting input sets
the common-mode voltage of the difference amplifer
to V
IN
/20. V
OUT
, the integrator output and the measure-
ment output, sources the required current to maintain
the common-mode voltage. R1 and C1 compensate the
system to a bandwidth of 200 kHz.
The transfer function is V
OUT
= V
IN
/19. For example, a
400 V p-p input signal will produce a 21 V p-p output.
Figure 6-28 shows that the measured system nonlinearity
is less than 20 ppm over the entire 400 V p-p input range.
System noise is about 550 nV/Hz referred to the input,
or around 2 mV peak noise voltage (10 ppm of full scale)
over a 300 kHz bandwidth.
V
IN
(V)
N
O
N
L
I
N
E
A
R
I
T
Y
E
R
R
O
R
(
p
p
m
)
0
10
20
10
20
200 150 100 50 0 50 100 150 200
Figure 6-28. Nonlinearity vs. V
IN
HIGH COMMON-MODE REJECTION SINGLE-
SUPPLY CIRCUIT
The circuit of Figure 6-29 can extract tiny signals riding
on very large common-mode voltages and its single
supply. Also, unless the converter is driven differentially,
the noise on the analog-to-digital converter (ADC)
reference pin is indistinguishable from a real signal.
The circuit of Figure 6-29 solves both of these problems.
It provides a gain of 2, along with differential inputs and
a differential output. The ADC reference sets the output
common-mode level. The amplifer is constructed with
two subtractors, each compliant to high common-mode
voltage. These subtractors are set up so that the positive
input of one connects to the negative input of the other,
and vice versa. Their reference pins are tied together and
connected to the ADCs reference pin.
6-14
380k
380k
6
21.1k
5
2
3
1
AD629 #1
380k
20k
OUTP
380k
380k
6
21.1k
5
2
3
1
AD629 #2
380k
20k
OUTN
DGND
GND
A
IN
REF
A
IN
ADC
V
IN
V
CM
+IN
IN
Figure 6-29. A High CMV Single-Supply Circuit
As the input signal increases, one output, OUTP,
increases, while the other output, OUTN, decreases. Both
outputs remain centered with respect to the common-
mode level set by the ADCs reference.
Figure 6-30 illustrates the circuits performance with a
single 5 V power supply. At the top is a 1 kHz, 3 V p-p
input signal. At the bottom are the two outputs in
antiphase to produce a 3 V p-p signal centered around
the 2.5 V reference.
CH1 1.00V CH2 1.00V
CH4 1.00V
M 200s
INPUT SIGNAL 1V p-p/DIV
5V POWER SUPPLY
Figure 6-30. Top Trace is the Input Signal; Bottom
Trace Is Antiphase Output, 40 V p-p on +2.5 dc
Figure 6-31 demonstrates the systems ability to reject
a 1 kHz, 60 V p-p common-mode signal. The upper
waveform shows the common-mode input, while the
lower waveform shows the output.
CH3
MATH1
20.0V
20.0mV 200s
M 200s
Figure 6-31. With a 5 V Supply and a 1 kHz, 60 V p-p
Common-Mode Signal (Upper Trace), the Circuits
Output (Lower Trace) Illustrates the High Common-
Mode Rejection
Bigger power supplies, such as 15 V, can be used for
larger common-mode signals. Figure 6-32 shows that
the system can reject a 400 V p-p common-mode signal
(upper waveform), with the residual error of less than
100 mV p-p shown in the lower waveform.
CH3
MATH1
100V
5.00mV 1.00mV
M1.00ms CH3 204V
Figure 6-32. Using a 15 V Supply, the Circuit
Reduces a 400 V p-p Common-Mode Signal
(Upper Trace) to Under 10 mV p-p (Lower Trace)
6-15
REF 1
IN 2
+IN 3
V
S
4
NC
NC = NO CONNECT
8
+V
S
7
OUT 6
+REF 5
21.11k 380k
380k
380k
AD629
20k
10k
3
6
COMPENSATION
POLE AMPLIFIER
OP97
2
0.1F
7
4
V
BUS
19
DATA
OUT
AD7476
GND SCLK
VDD CS
VIN
SDATA
CHIP
SELECT
CLOCK
IN
V
BUS
39VTO
79V
15V
V
BUS
= +14.1V V
BUS
= +5V
V
BUS
= +5V
10k
2N2222 OR
EQUIV.
ADR425
5V REF
0.1F
0.1F
1nF
Figure 6-33. Precision Remote Voltage Measurement of 48 V Power Distribution Bus
PRECISION 48 V BUS MONITOR
Telephone equipment power supplies normally consist
of a 48 V dc power source and an array of batteries. The
batteries provide backup power during ac power line
outages and help regulate the 48 V dc supply voltage.
Although nominally 48 V, the dc voltage on the
telephone lines can vary anywhere from 40 V to 80 V and
is subject to surges and fuctuations. Supply regulation
at the source has little effect on remote voltage levels and
equipment failures resulting from surges, brownouts, or
other line faults, may not always be detected.
Capturing power supply information from remote com-
munications equipment requires precise measurement
of the voltages, sometimes under outdoor temperature
conditions. High common-mode voltage difference
amplifers have been used to monitor current. However,
these versatile components can also be used as voltage
dividers, enabling remote monitoring of voltage levels
as well.
Figure 6-33 shows a precision monitor using just
two integrated circuits, which derives its power from
the 48 V supply. A low cost transistor and Zener
diode combination provide 15 V supply voltage for
the amplifers.
The AD629 IC is a self-contained high common-mode
voltage difference amplifer. Connected as shown, it
reduces the differential input voltage by approximately
19 V, thus acting as a precision voltage divider. An
additional amplifer is required for loop stability.
The output from the OP-07 drives an AD7476 ADC.
The circuit features several advantages over alternative
solutions. The AD629s laser trimmed divider resis-
tors exhibit essentially perfect matching and tracking
over temperature. Linearity errors from 40 V to
80 V are nearly immeasurable. Figures 6-34 and
6-35 are linearity and temperature drift curves for
this circuit.
6-16
4.5
4.0
3.5
3.0
2.5
30 40 50 60 70 80 90
2.0
INPUT VOLTAGE (V)
O
U
T
P
U
T
V
O
L
T
A
G
E
(
V
)
Figure 6-34. Output vs. Input Linearity for
the Circuit of the 48 V Bus Monitor
2.1064
50 0 50 100
2.1050
2.1052
2.1054
2.1056
2.1058
2.1060
2.1062
TEMPERATURE (C)
O
U
T
P
U
T
V
O
L
T
A
G
E
(
V
)
Figure 6-35. Temperature Drift of the
48 V Bus Monitor
HIGH-SIDE CURRENT SENSE WITH A
LOW-SIDE SWITCH
A typical application for the AD8205 is high-side
measurement of a current through a solenoid for PWM
control of the solenoid opening. Typical applications
include hydraulic transmission control and diesel injec-
tion control.
Two typical circuit confgurations are used for this type
of application.
In this case, the PWM control switch is ground referenced.
An inductive load (solenoid) is tied to a power supply. A
resistive shunt is placed between the switch and the load
(see Figure 6-36). An advantage of placing the shunt
on the high side is that the entire current, including the
recirculation current, can be measured since the shunt
remains in the loop when the switch is off. In addition,
diagnostics can be enhanced because shorts to ground
can be detected with the shunt on the high side.
In this circuit confguration, when the switch is closed,
the common-mode voltage moves down to near the
negative rail. When the switch is opened, the voltage
reversal across the inductive load causes the common-
mode voltage to be held one diode drop above the battery
by the clamp diode.
+IN V
REF
1 +V
S
OUT
IN GND V
REF
2 NC
INDUCTIVE
LOAD
AD8205
CLAMP
DIODE
42V
BATTERY
SHUNT
SWITCH
NC = NO CONNECT
5V
Figure 6-36. Low-Side Switch
6-17
HIGH-SIDE CURRENT SENSE WITH A
HIGH-SIDE SWITCH
This confguration minimizes the possibility of unex-
pected solenoid activation and excessive corrosion
(see Figure 6-37). In this case, both the switch and the
shunt are on the high side. When the switch is off, this
removes the battery from the load, which prevents damage
from potential shorts to ground, while still allowing the
recirculating current to be measured and providing for
diagnostics. Removing the power supply from the load for
the majority of the time minimizes the corrosive effects
that could be caused by the differential voltage between
the load and ground.
When using a high-side switch, the battery voltage
is connected to the load when the switch is closed,
causing the common-mode voltage to increase to the
battery voltage. In this case, when the switch is opened,
the voltage reversal across the inductive load causes the
common-mode voltage to be held one diode drop below
ground by the clamp diode.
+IN V
REF
1 +V
S
OUT
IN GND V
REF
2 NC
INDUCTIVE
LOAD
AD8205
CLAMP
DIODE
42V
BATTERY
SHUNT
SWITCH
NC = NO CONNECT
5V
Figure 6-37. High-Side Switch
Another typical application for the AD8205 is as part of
the control loop in H-bridge motor control. In this case,
the AD8205 is placed in the middle of the H-bridge (see
Figure 6-38) so that it can accurately measure current in
both directions by using the shunt available at the motor.
This is a better solution than a ground referenced op
amp because ground is not typically a stable reference
voltage in this type of application. This instability in the
ground reference causes the measurements that could
be made with a simple ground referenced op amp to be
inaccurate.
+IN V
REF
1 +V
S
OUT
IN GND V
REF
2 NC
AD8205
SHUNT
5V
2.5V
5V
CONTROLLER
NC = NO CONNECT
MOTOR
Figure 6-38. Motor Control Application
The AD8205 measures current in both directions as the
H-bridge switches and the motor changes direction. The
output of the AD8205 is confgured in an external
reference bidirectional mode.
BRIDGE APPLICATIONS
Instrumentation amplifiers are widely used for buff-
ering and amplifying the small voltage output from
transducers that make use of the classic four resistor
Wheatstone bridge.
A Classic Bridge Circuit
Figure 6-39 shows the AD627 confgured to amplify the
signal from a classic resistive bridge. This circuit will
work in either dual- or single-supply mode. Typically, the
bridge will be excited by the same voltage used to power
the in-amp. Connecting the bottom of the bridge to the
negative supply of the in-amp (usually either 0, 5 V,
12 V, or 15 V) sets up an input common-mode voltage
that is optimally located midway between the supply
voltages. It is also appropriate to set the voltage on the
AD627
V
OUT
V
REF
V
S
+V
S
V
DIFF
R
G
=
200k
GAIN-5
0.1F
0.1F
Figure 6-39. A Classic Bridge Circuit for Low Power Applications
6-18
REF pin to midway between the supplies, especially if
the input signal will be bipolar. However, the voltage
on the REF pin can be varied to suit the application.
A good example of this is when the REF pin is tied to
the V
REF
pin of an analog-to-digital converter (ADC)
whose input range is (V
REF
V
IN
). With an available
output swing on the AD627 of (V
S
+ 100 mV) to
(+V
S
150 mV), the maximum programmable gain is
simply this output range divided by the input range.
A Single-Supply Data Acquisition System
The bridge circuit of Figure 6-40 is excited by a +5 V
supply. The full-scale output voltage from the bridge
(10 mV), therefore, has a common-mode level of
2.5 V. The AD623 removes the common-mode voltage
component and amplifes the input signal by a factor
of 100 (R
GAIN
= 1.02 kU). This results in an output
signal of 1 V.
In order to prevent this signal from running into the
AD623s ground rail, the voltage on the REF pin has
to be raised to at least 1 V. In this example, the 2 V
reference voltage from the AD7776 ADC is used to
bias the AD623s output voltage to 2 V 1 V. This
corresponds to the input range of the ADC.
A Low Dropout Bipolar Bridge Driver
The AD822 can be used for driving a 350 U Wheat-
stone bridge. Figure 6-41 shows one-half of the AD822
being used to buffer the AD589, a 1.235 V low power
reference. The output of +4.5 V can be used to drive an
A/D converter front end. The other half of the AD822
is confgured as a unity-gain inverter and generates the
other bridge input of 4.5 V.
Resistors R1 and R2 provide a constant current for
bridge excitation. The AD620 low power instrumen-
tation amplifer is used to condition the differential
output voltage of the bridge. The gain of the AD620
is programmed using an external resistor, R
G
, and
determined by
G
R
G
= +
49 4
1
. k
10mV
+5V
0.1F
AD623
REF
R
G
1.02k
+5V
REF
OUT
REF
IN
A
IN
AD7776
+5V
0.1F
Figure 6-40. A Single-Supply Data Acquisition System

AD620
+

1/2
AD822
+V
S
49.9k
+1.235V
AD589
10k
1%
26.4k, 1%
R1
20
+

R
G
TO A/D CONVERTER
REFERENCE INPUT
+V
S
V
REF
V
S
350
350 350
350
1 2
AD822
+

10k
1%
10k
1%
R2
20
V
S
4.5V + +
+ +
0.1F
0.1F
1F
1F
+5V +V
S
5V V
S
GND
Figure 6-41. Low Dropout Bipolar Bridge Driver
6-19
TRANSDUCER INTERFACE APPLICATIONS
Instrumentation amplifiers have long been used as
preamplifiers in transducer applications. High quality
transducers typically provide a highly linear output,
but at a very low level, and a characteristically high
output impedance. This requires the use of a high
gain buffer/preamplifier that will not contribute any
discernible noise of its own to that of the signal.
Furthermore, the high output impedance of the typical
transducer may require that the in-amp have a low
input bias current.
Table 6-3 gives typical characteristics for some common
transducer types.
Since most transducers are slow, bandwidth require-
ments of the in-amp are modest: a 1 MHz small
signal bandwidth at unity gain is adequate for most
applications.
MEDICAL EKG APPLICATIONS
An EKG is a challenging real-world application, as a
small 5 mV signal must be extracted in the presence
of much larger 60 Hz noise and large dc common-
mode offset variations. Figure 6-42 shows a block
diagram of a typical EKG monitor circuit. The value
of capacitor C
X
is chosen to maintain stability of the
right leg drive loop.
Three outputs from the patient are shown here, although
several more may be used. The output buffer ampli-
fers should be low noise, low input bias current FET
op amps, since the patient sensors are typically very
high impedance and signal levels may be quite low. A
three resistor summing network is used to establish a
common sense point to drive the force amplifer. The
output from the force amplifer servos current through
the patient until the net sum output from the three
buffer amplifers is zero.
A
B
C
BUFFER
AMPLIFIERS
IN-AMP#1
IN-AMP#2
C-B
A-B
IN-AMP#3
A-C
0.03Hz
HIGH-
PASS
FILTER
0.03Hz
HIGH-
PASS
FILTER
0.03Hz
HIGH-
PASS
FILTER
A
B
C
PATIENT/CIRCUIT
PROTECTION/ISOLATION
A
B
C
F
C
X
Figure 6-42. A Medical EKG Monitor Circuit
6-20
Table 6-3. Typical Transducer Characteristics
Recommended
Transducer Type Type of Output Output Z ADI In-Amp/Diff Amp
Thermistor Resistance Changes 50 U to 1 MU AD620, AD621, AD623,
with Temperature (TC) @ +25`C AD627, AD629, AD8221,
4%/`C @ +25`C AD8225
High Nonlinear Output
Single-Supply
Thermocouple Low Source Z 20 U to 20 kU AD620, AD621, AD623,
10 V/`C to 100 V/`C (10 U typ) AD627, AD8221
mV Output Level
@ +25`C Single-Supply
Resistance Temperature Low Source Z 20 U to 20 kU AD620, AD621, AD623,
Detector (RTD) with Temperature (+TC) @ 0`C AD627, AD8221, AD8225
(In Bridge Circuit) 0.1%/`C to 0.66%/`C
Single- or Dual-Supply
Level Sensors
Thermal Types Thermistor Output (Low) 500 U to 2 kU AD626, AD628, AD629,
Float Types Variable Resistance 100 U to 2 kU AD8225
Output of mV to Several Volts
Single-Supply
Load Cell Variable Resistance 120 U to 1 kU AD620, AD621, AD8221,
(Strain Gage Bridge) 2 mV/V of Excitation AD8225
(Weight Measurement) 0.1% Typical Full-Scale Change
Single- or Dual-Supply
Current Sense (Shunt) Low Value Resistor Output A Few Ohms AD626, AD628, AD629,
High Common-Mode Voltage (or less) AD8202, AD8205
EKG Monitors Low Level Differential 500 kU AD620, AD621, AD623,
(Single-Supply Output Voltage AD627, AD8221, AD8225
Bridge Confguration) 5 mV Output Typical
Single- or Dual-Supply
Photodiode Sensor Current Increases 10
9
U AD620, AD621, AD622,
with Light Intensity AD623, AD627, AD8221
1 pA to 1 A I
OUTPUT

Single-Supply
Hall Effect Magnetic 5 mV/kG to 120 mV/kG 1 U to 1 kU AD620, AD621, AD622,
AD623, AD627, AD8221
6-21
Three in-amps are used to provide three separate out-
puts for monitoring the patients condition. Suitable
ADI products include AD8221, AD627, and AD623
in-amps and AD820, AD822 (dual), and AD824
(quad) op amps for use as the buffer. Each in-amp is
followed by a high-pass flter that removes the dc com-
ponent from the signal. It is common practice to omit
one of the in-amps and determine the third output by
software (or hardware) calculation.
Proper safeguards, such as isolation, must be added to
this circuit to protect the patient from possible harm.
REMOTE LOAD-SENSING TECHNIQUE
The circuit of Figure 6-43 is a unity gain instrumentation
amplifer that uses its sense and reference pins to mini-
mize any errors due to parasitic voltage drops within the
circuit. If heavy output currents are expected, and there
is a need to sense a load that is some distance away from
the circuit, voltage drops due to trace or wire resistance
can cause errors. These voltage drops are particularly
troublesome with low resistance loads, such as 50 U.
The sense terminal completes the feedback path for the
instrumentation amplifer output stage and is normally
connected directly to the in-amp output. Similarly, the
reference terminal sets the reference voltage about which
the in-amps output will swing. This connection puts
the IR drops inside the feedback loop of the in-amp
and virtually eliminates any IR errors.
This circuit will provide a 3 dB bandwidth better than
3 MHz. Note that any net capacitance between the
twisted pairs is isolated from the in-amps output by
25 kU resistors, but any net capacitance between the
twisted pairs and ground needs to be minimized to
maintain stability. So, unshielded twisted-pair cable is
recommended for this circuit. For low speed applications
that require driving long lengths of shielded cable, the
AMP01 should be substituted for the AMP03 device.
The AMP01 can drive capacitance loads up to 1 F, while
the AMP03 is limited to driving a few hundred pF.
*
*
OUTPUT
GROUND
TWISTED
PAIRS
REMOTE
LOAD
IN
+IN
SENSE
+V
CC
OUTPUT
V
EE
REFERENCE
25k
25k
25k 25k
6
7
1
2
3
4
5
AMP03
TWISTED
PAIRS
+V
IN
V
IN
*1N4148 DIODES ARE OPTIONAL. DIODES LIMITTHE OUTPUT
VOLTAGE EXCURSION IF SENSE AND/OR REFERENCE LINES
BECOME DISCONNECTED FROMTHE LOAD.
Figure 6-43. A Remote Load Sensing Connection
6-22
A PRECISION VOLTAGE-TO-CURRENT
CONVERTER
Figure 6-44 is a precision voltage-to-current converter
whose scale factor is easily programmed for exact de-
cade ratios using standard 1% metal flm resistor values.
The AD620 operates with full accuracy on standard
5 V power supply voltages. Note that although the
quiescent current of the AD620 is only 900 A, the
addition of the AD705 will add an additional 380 A
current consumption.
A CURRENT SENSOR INTERFACE
Figure 6-45 shows a novel circuit for sensing low-level
currents. It makes use of the large common-mode range of
the AD626. The current being measured is sensed across
resistor R
S
. The value of R
S
should be less than 1 kU
and should be selected so that the average differential
voltage across this resistor is typically 100 mV.
To produce a full-scale output of +4 V, a gain of 40 is
used, adjustable by +20% to absorb the tolerance in the
sense resistor. Note that there is suffcient headroom to
allow at least a 10% overrange (to +4.4 V).
AD620
R
G
V
S
V
IN+
V
IN
LOAD
R1
I
L
Vx
I =
L
R1
=
IN+
[(V ) (V )] G
IN
R1
WHERE G = 1 +
49,400
R
G
6
5
+ V
X
4
2
1
8
3
7
+V
S
AD705
0.1F
0.1F
+V
S
0.1F
0.1F
V
S
6
7
4
2
3
Figure 6-44. A Precision Voltage-to-Current Converter that Operates on 5 V Supplies
R
S
CF
OPTIONAL
LOW-PASS
FILTER
OUTPUT
+V
S
CURRENT IN
CURRENT OUT
0.1F
1
2
3
4
8
7
6
5
IN +IN
G = 100
OUT
AD626
200k 200k
100k
G=
2
ANALOG
GND
V
S
FILTER
1/6
G=30
+V
S
0.1F
V
S
R
S
CURRENT
SENSOR
Figure 6-45. Current Sensor Interface
6-23
OUTPUT BUFFERING LOW POWER IN-AMPS
The AD627 low power in-amp is designed to drive load
impedances of 20 kU or higher, but can deliver up to
20 mA to heavier loads with low output voltage swings.
If more than 20 mA of output current is required, the
AD627s output should be buffered with a precision
low power op amp, such as the AD820, as shown in
Figure 6-46. This op amp can swing from 0 V to 4 V
on its output while driving a load as small as 600 U.
The addition of the AD820 isolates the in-amp from
the load, thus greatly reducing any thermal effects.
0.1F
+V
S
V
S
R
G
REF
0.1F
0.1F
V
S
0.1F
V
OUT
AD627
AD820
3
1
8
2
4
5
6
7
3
2
7
4
6
Figure 6-46. Output Buffer for Low
Power In-Amps
A 4 mA TO 20 mA SINGLE-SUPPLY RECEIVER
Figure 6-47 shows how a signal from a 4 mA to 20 mA
transducer can be interfaced to the ADuC812, a 12-bit
ADC with an embedded microcontroller. The signal from
a 4 mA to 20 mA transducer is single-ended. This initially
suggests the need for a simple shunt resistor to convert
the current to a voltage at the high impedance analog
input of the converter. However, any line resistance in
the return path (to the transducer) will add a current-
dependent offset error. So, the current must be sensed
differentially. In this example, a 24.9 U shunt resistor
generates a maximum differential input voltage to the
AD627 of between 100 mV (for 4 mA in) and 500 mV
(for 20 mA in). With no gain resistor present, the AD627
amplifes the 500 mV input voltage by a factor of 5 to
2.5 V, the full-scale input voltage of the ADC. The zero
current of 4 mA corresponds to a code of 819 and the
LSB size is 4.9 mV.
AD627
0.1F
24.9 R
G
REF
4mA20mA
4mA20mA
TRANSDUCER
AGND DGND
AIN 07
V
REF
+5V
AVDD
+5V
DVDD
ADuC812
MICROCONVERTER
+5V
LINE
IMPEDANCE
0.1F 0.1F
3
1
8
2
4
5
6
7
G = 5
Figure 6-47. A 4 mA to 20 mA Receiver Circuit
6-24
A SINGLE-SUPPLY THERMOCOUPLE
AMPLIFIER
Because the common-mode input range of the AD627
extends 0.1 V below ground, it is possible to measure
small differential signals with little or no common-
mode component. Figure 6-48 shows a thermocouple
application where one side of the J-type thermocouple
is grounded. Over a temperature range from 200`C
to +200`C, the J-type thermocouple delivers a voltage
ranging from 7.890 mV to +10.777 mV.
A programmed gain on the AD627 of 100 (R
G
= 2.1 kU)
and a voltage on the AD627 REF pin of 2 V results in
the AD627s output voltage ranging from 1.110 V to
3.077 V relative to ground.
SPECIALTY PRODUCTS
Analog Devices sells a number of specialty products,
many of which were designed for the audio market that
are useful for some in-amp applications. Table 6-4 lists
some of these products.
R
G AD627
0.1F
V
OUT
+5V
J-TYPE
THERMOCOUPLE
+2V
REF
COPPER
WIRES
THERMOCOUPLE
WIRES
COLD JUNCTION
COMPENSATION
1
8
3
2
4
5
6
7
Figure 6-48. A Thermocouple Amplifer Using a Low Power, Single-Supply In-Amp
Table 6-4. Specialty Products Available from Analog Devices
Model CMR
Number Description BW (DC) Supply Features
SSM2141 Diff Line Receiver 3 MHz 100 dB 18 V High CMR, Audio Subtractor
SSM2143 Diff Line Receiver 7 MHz (G = 0.5) 90 dB 6 V to 18 V Low Distortion, Audio Subtractor
SSM2019 Audio Preamp 2 MHz (G = 1) 74 dB 5 V to 18 V Low Noise, Low Distortion, Audio IA
7-1
Chapter VII
MATCHING IN-AMP CIRCUITS TO MODERN ADCs
Calculating ADC Requirements
The resolution of commercial ADCs is specifed in bits.
In an ADC, the available resolution equals (2
n
)1, where
n is the number of bits. For example, an 8-bit converter
provides a resolution of (2
8
)1, which equals 255. In this
case, the full-scale input range of the converter divided
by 255 will equal the smallest signal it can resolve. For
example, an 8-bit ADC with a 5 V full-scale input range
will have a limiting resolution of 19.6 mV.
In selecting an appropriate ADC to use, we need to
fnd a device that has a resolution better than the
measurement resolution but, for economys sake, not
a great deal better.
Table 7-1 provides input resolution and full-scale
input range using an ADC with or without an in-amp
preamplifer. Note that the system resolution specifed
in the fgure refers to that provided by the converter
together with the in-amp preamp (if used). Also, note
that for any low level measurement, not only are low
ful attention to component layout, grounding, power
supply bypassing, and often, the use of balanced,
shielded inputs.
For many applications, an 8- or 10-bit converter is
appropriate. The decision to use a high resolution
converter alone, or to use a gain stage ahead of a
lower resolution converter, depends on which is more
important: component cost, or parts count and ease
of assembly.
Adding amplifcation before the ADC will also reduce
the circuits full-scale input range, but it will lower the
resolution requirements (and, therefore, the cost) of
the ADC.
For example, using an in-amp with a gain of 10 ahead of
an 8-bit, 5 V ADC will increase circuit resolution from
19.5 mV (5 V/256) to 1.95 mV. At the same time, the
full-scale input range of the circuit will be reduced to
500 mV (5 V/10).
Table 7-1. Typical System Resolutions vs. Converter Resolution
and Preamp (IA) Gain
Converter
Resolution FS System
Converter mV/Bit In-Amp Range Resolution
Type (2
n
)1 (5 V/((2
n
)1)) Gain (V p-p) (mV p-p)
10-Bit 1,023 4.9 mV 1 5 4.9
10-Bit 1,023 4.9 mV 2 2.5 2.45
10-Bit 1,023 4.9 mV 5 1 0.98
10-Bit 1,023 4.9 mV 10 0.5 0.49
12-Bit 4,096 1.2 mV 1 5 1.2
12-Bit 4,096 1.2 mV 2 2.5 0.6
12-Bit 4,096 1.2 mV 5 1 0.24
12-Bit 4,096 1.2 mV 10 0.5 0.12
14-Bit 16,383 0.305 mV 1 5 0.305
14-Bit 16,383 0.305 mV 2 2.5 0.153
14-Bit 16,383 0.305 mV 5 1 0.061
14-Bit 16,383 0.305 mV 10 0.5 0.031
16-Bit 65,535 0.076 mV 1 5 0.076
16-Bit 65,535 0.076 mV 2 2.5 0.038
16-Bit 65,535 0.076 mV 5 1 0.015
16-Bit 65,535 0.076 mV 10 0.5 0.008
7-2
ADI In-Amp AD8221AR
Small Signal BW: 562 kHz
Noise (e
NI
): 8 nV/Hz
V
OS
: 60 V Max
In-Amp Gain: 10
Maximum Output
Voltage Swing: 3.9 V
CMRR: 90 dB (DC-60 Hz)
Nonlinearity: 10 ppm Max
Resolution: 0.0003% (18 Bits)
Supply Voltage: 5 V
Supply Current: 1 mA Max
0.01% Settling Time
for 5 V Step: 5 s
0.001% Settling Time
for 5 V Step: 6 s
Recommended
ADI ADC#1 AD7685
Resolution: 16 Bits
Input Range: 0 V to 5 V
Sampling Rate: Up to 250 kSPS
S/D Supply: 3 V or 5 V
Power: 1.7 mW @ 2.5 V and
6 mW typ @ 5 V
Comments: Same package, the AD7685
can be driven through a
simple RC from the AD8221
directly. The REF pin can be
driven to ft the ADC range.
Recommended
ADI ADC#2 AD7453/AD7457
Resolution: 12 Bits
Input Range: 0 V to VDD
Sampling Rate: 555 kSPS/100 kSPS
S/D Supply: 3 V or 5 V
Power: 0.3 mA @ 100 kSPS
Comments: Single channel, pseudo
differential inputs in a
SOT-23 package
Matching ADI In-Amps with Some Popular ADCs
Table 7-2 shows recommended ADCs for use with the latest generation of ADI in-amps.
Table 7-2. Recommended ADCs for Use with ADI In-Amps
ADI In-Amp AD620AR
Small Signal BW: 800 kHz
Noise (e
NI
): 9 nV/Hz
V
OS
: 125 V Max
In-Amp Gain: 10
Maximum Output
Voltage Swing: 3.9 V
CMRR: 73 dB (DC-60 Hz)
Nonlinearity: 40 ppm Max
Resolution: 0.0013% (16 Bits)
Supply Voltage: 5 V
Supply Current: 1.3 mA Max
0.01% Settling Time
for 5 V Step: 7 s
Recommended
ADI ADC#1 AD7663
Resolution: 16 Bits
Input Range: Multiple such as 10 V,
5 V, ...
Sampling Rate: Up to 250 kSPS
S/D Supply: 5 V
Power: 2.7 mA @ 100 kSPS
Comments: Allow more and larger
input ranges
Recommended
ADI ADC#2 AD7895
Resolution: 12 Bits
Input Range: Multiple such as 10 V,
2.5 V, 0 V to 2.5 V
Sampling Rate: 200 kSPS
S/D Supply: 5 V
Power: 2.2 mA @ 100 kSPS
Comments: Allows a bipolar or unipolar
input with a single supply
7-3
Table 7-2. Recommended ADCs for Use with ADI
In-Amps (continued)
ADI In-Amp AD8225 Fixed Gain of 5
Small Signal BW: 900 kHz
Noise (e
NI
): 8 nV/Hz
V
OS
: 125 V Max
In-Amp Gain: 5
Maximum Output
Voltage Swing: 4 V
CMRR: 90 dB (DC-60 Hz)
Nonlinearity: 10 ppm Max
Resolution: 0.0013% (16 Bits)
Supply Voltage: 5V
Supply Current: 1.2 mA Max
0.01% Settling Time
for 5 V Step: 3.2 s
0.001% Settling Time
for 5 V Step: 4 s
Recommended
ADI ADC#1 AD7661
Resolution: 16 Bits
Input Range: 0 V to 2.5 V
Sampling Rate: Up to 100 kSPS
S/D Supply: 5 V
Power: 8 mA @ 100 kSPS with
reference
Comments: Provide a reference voltage
Recommended
ADI ADC#2 AD7940
Resolution: 14 Bits
Input Range: 0 V to VDD
Sampling Rate: 100 kSPS
S/D Supply: 3 V or 5 V
Power: 0.83 mA @ 100 kSPS
Comments: Single channel in a SOT-23
ADI In-Amp AD623AR
Small Signal BW: 100 kHz
Noise (e
NI
): 35 nV/Hz
V
OS
: 200 V Max
In-Amp Gain: 10
Maximum Output
Voltage Swing: 4.5 V
CMRR: 90 dB (DC-60 Hz)
Nonlinearity: 50 ppm Typ
Resolution: 0.02% (12 Bits)
Supply Voltage: 5 V
Supply Current: 0.55 mA Max
0.01% Settling Time
for 5 V Step: 20 s
Recommended
ADI ADC#1 AD7688
Resolution: 12 Bits
Input Range: 0 V to V
REF
V or 0 V to
2 V
REF
V
Sampling Rate: 1 MSPS for both ADCs
S/D Supply: Single 2.7 V to 5.25 V
Power: 24 mW Max at 1 MSPS with
5 V supply 11.4 mV Max at
1 MSPS with 3 V supply
Comments: Dual, 2-channel simultaneous
sampling ADC with a
serial interface
Recommended
ADI ADC#2 AD7862/AD7684
Resolution: 12 Bits
Input Range: 0 V to +2.5 V, 0 V to +5 V,
2.5 V, 5 V, 10 V
Sampling Rate: 600 kSPS for one channel
S/D Supply: Single 5 V
Power: 90 mW typ
Comments: 4-channel simultaneous
sampling ADC with a
parallel interface
Recommended
ADI ADC#3 AD7863/AD7865
Resolution: 14 Bits
Input Range: 0 V to +2.5 V, 0 V to +5 V,
2.5 V, 5 V, 10 V
Sampling Rate: 175 kSPS for both channels/
360 kSPS for one channel,
respectively
S/D Supply: Single 5 V
Power: 70 mW typ/115 mV typ ,
respectively
Comments: 2-/4-channel (respectively)
simultaneous sampling ADC
with a parallel interface
Recommended
ADI ADC#4 AD7890/AD7891/AD7892
Resolution: 12 Bits
Input Range: 0 V to +2.5 V, 0 V to
+4.096 V, 0 V to +5 V,
2.5 V, 5 V10 V
Sampling Rate: 117/500/600 kSPS, respectively
S/D Supply: Single 5 V supply
Power: 30/85/60 mW typ, respectively
Comments: 8/8/1 channels, respectively
7-4
High Speed Data Acquisition
As the speed and accuracy of modern data acquisi-
tion systems have increased, a growing need for high
bandwidth instrumentation amplifers has developed
particularly in the feld of CCD imaging equipment
where offset correction and input buffering are required.
Here, double-correlated sampling techniques are often
used for offset correction of the CCD imager. As shown
in Figure 7-1, two sample-and-hold amplifers moni-
tor the pixel and reference levels, and a dc-corrected
output is provided by feeding their signals into an
instrumentation amplifer.
Table 7-2. Recommended ADCs for Use with ADI
In-Amps (continued)
ADI In-Amp AD627AR
Small Signal BW: 30 kHz
Noise (e
NI
): 38 nV/Hz
V
OS
: 200 V Max
In-Amp Gain: 10
Maximum Output
Voltage Swing: 4.9 V
CMRR: 77 dB (DC-60 Hz)
Nonlinearity: 100 ppm Max
Resolution: 0.02% (12 Bits)
Supply Voltage: 5 V
Supply Current: 85 A Max
0.01% Settling Time
for 5 V Step: 135 s
Recommended
ADI ADC#1 AD7923/AD7927
Resolution: 12 Bits
Input Range: 0 V to V
REF
or 0 V to 2 V
REF
Sampling Rate: 200 kSPS
S/D Supply: Single, 2.7 V to 5.25 V
Power: 3.6 mW Max @ 200 kSPS
with a 3 V supply
Comments: 8-/4-channel ADCs, respec-
tively, with a serial interface
and channel sequencer
Recommended
ADI ADC#2 AD7920
Resolution: 12 Bits
Input Range: 0 to V
DD
Sampling Rate: 250 kSPS
S/D Supply: 2.35 V or 5.25 V
Power: 3 mW typ @ 250 kSPS with
3 V supply
Comments: Single channel, serial ADC in
6 lead SC-70
7-5
INSTRUMENTATION
AMPLIFIER
NEED 12-BIT
ACCURACY
@1MHz
DC
CORRECTED
OUTPUT
SAMPLE-
AND-HOLD
TOTAL SETTLING TIME FOR SAMPLE-AND-HOLD
AND IN-AMP MUST BE LESS THAN 500ns
PIXEL LEVEL
INPUT
REFERENCE
LEVEL INPUT
2MHz
500ns
ADC
AD671
PIXEL LEVEL
REFERENCE
LEVEL
PIXEL
#1
PIXEL
#2
Figure 7-1. In-Amp Buffers ADC and Provides DC Correction
Figure 7-2 shows how a single multiplexed high
bandwidth in-amp can replace several slow speed
nonmultiplexed buffers. The system benefts from
the common-mode noise reduction and subsequent
increase in dynamic range provided by the in-amp.
ADC
AD671
HIGH SPEED IA
MUX
SIGNAL
INPUTS
MUX
SIGNAL
INPUTS
Figure 7-2. Single High Speed In-Amp and
Mux Replace Several Slow Speed Buffers
Previously, the low bandwidths of commonly available
instrumentation amplifers, plus their inability to
drive 50 U loads, restricted their use to low frequency
applicationsgenerally below 1 MHz. Some higher
bandwidth amplifers have been available, but these
have been fxed-gain types with internal resistors. With
these amplifers, there was no access to the inverting and
noninverting terminals of the amplifer. Using modern
op amps and employing the complementary bipolar
(CB) process video bandwidth instrumentation ampli-
fers that offer both high bandwidths and impressive dc
specifcations may now be constructed. Common-mode
rejection may be optimized by trimming or by using
low cost resistor arrays.
The bandwidth and settling time requirements de-
manded of an in-amp buffering an ADC, and for the
sample-and-hold function preceding it, can be quite
severe. The input buffer must pass the signal along fast
enough so that the signal is fully settled before the ADC
takes its next sample. At least two samples per cycle are
required for an ADC to unambiguously process an input
signal (FS/2)this is referred to as the Nyquist criteria.
Therefore, a 2 MHz ADC, such as the AD671, requires
that the input buffer/sample hold sections preceding
it provide 12-bit accuracy at a 1 MHz bandwidth.
Settling time is equally important: the sampling rate
of an ADC is the inverse of its sampling frequencyfor
the 2 MHz ADC, the sampling rate is 500 ns. This
means that for a total throughput rate of less than
1 s, these same input buffer/sample hold sections
must have a total settling time of less than 500 ns.
7-6
IN
+IN
SENSE
+V
S
OUTPUT
V
S
REF
25k
25k
25k
25k
6
7
1
2
3
4
5
AMP03
+V
IN
V
IN
+V
S
V
OUT
0.01F
V
S
0.01F
+V
S
0.01F
V
S
0.01F
AD825
1k
1k
222k
R
F
R
G
R
F
AD825
ADC
Figure 7-3. A High Performance, High Speed In-Amp Circuit
A High Speed In-Amp Circuit for Data Acquisition
Figure 7-3 shows a discrete in-amp circuit using two
AD825 op amps and an AMP03 differential (subtractor)
amplifer. This design provides both high performance
and high speed at moderate gains. Circuit gain is set
by resistor R
G
where Gain = 1 + 2 R
F
/R
G
. Resistors R
F

should be kept at around 1 kU to ensure maximum band-
width. Operating at a gain of 10 (using a 222 U resistor
for R
G
) the 3 dB bandwidth of this circuit is approxi -
mately 3.4 MHz. The ac common- mode rejection
ratio (gai n of 10, 1 V p- p common- mode signal
applied to the inputs) is 60 dB from 1 Hz to 200 kHz
and 43 dB at 2 MHz. And it provides better than
46 dB CMRR from 4 MHz to 7 MHz. The RFI rejection
characteristics of this amplifer are also excellentthe
change in dc offset voltage vs. common-mode fre-
quency is better than 80 dB from 1 Hz up to 15 MHz.
Quiescent supply current for this circuit is 15 mA.
For lower speed applications requiring a low input
current device, the AD823 FET input op amp can be
substituted for the AD825.
This circuit can be used to drive a modern, high speed
ADC such as the AD871 or AD9240, and to provide
very high speed data acquisition. The AD830 can also
be used for many high speed applications.
A-1
To successfully apply any electronic component, a full
understanding of its specifcations is required. That is to
say, the numbers contained in a data sheet are of little
value if the user does not have a clear picture of what
each specifcation means.
In this section, a typical monolithic instrumentation
amplifer data sheet is reviewed. Some of the more
Appendix A
INSTRUMENTATION AMPLIFIER SPECIFICATIONS
important specifcations are discussed in terms of how
they are measured and what errors they might contribute
to the overall performance of the circuit.
Table A-1 shows a portion of the data sheet for the Analog
Devices AD8221 instrumentation amplifer.
Table A-1. AD8221 Specifcations
1
AR Grade BR Grade ARM Grade
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit
COMMON-MODE
REJECTION RATIO (CMRR)
CMRR DC to 60 Hz with
1 kU Source Imbalance V
CM
= 10 V to +10 V
G = 1 80 90 80 dB
G = 10 100 110 100 dB
G = 100 120 130 120 dB
G = 1,000 130 140 130 dB
CMRR at 10 kHz V
CM
= 10 V to +10 V
G = 1 80 80 80 dB
G = 10 90 100 90 dB
G = 100 100 110 100 dB
G = 1,000 100 110 100 dB
NOISE RTI noise = e
NI
2
+ (e
NO
/G)
2

Voltage Noise, 1 kHz
Input Voltage Noise, e
NI
V
IN+
, V
IN
, V
REF
= 0 8 8 8 nV/Hz
Output Voltage Noise, e
NO
75 75 75 nV/Hz
RTI f = 0.1 Hz to 10 Hz
G = 1 2 2 2 V p-p
G = 10 0.5 0.5 0.5 V p-p
G = 100 to 1,000 0.25 0.25 0.25 V p-p
Current Noise f = 1 kHz 40 40 40 fA/Hz
f = 0.1 Hz to 10 Hz 6 6 6 pA p-p
VOLTAGE OFFSET
2

Input Offset, V
OSI
V
S
= 5 V to 15 V 60 25 70 V
Over Temperature T = 40`C to +85`C 86 45 135 V
Average TC 0.4 0.3 0.9 V/`C
Output Offset, V
OSO
V
S
= 5 V to 15 V 300 200 600 V
Over Temperature T = 40`C to +85`C 0.66 0.45 1.00 mV
Average TC 6 5 9 V/`C
Offset RTI vs. Supply (PSR) V
S
= 2.3 V to 18 V
G = 1 90 110 94 110 90 100 dB
G = 10 110 120 114 130 100 120 dB
G = 100 124 130 130 140 120 140 dB
G = 1,000 130 140 140 150 120 140 dB
INPUT CURRENT
Input Bias Current 0.5 1.5 0.2 0.4 0.5 2 nA
Over Temperature T = 40`C to +85`C 2.0 1 3 nA
Average TC 1 1 3 pA/`C
Input Offset Current 0.2 0.6 0.1 0.4 0.3 1 nA
Over Temperature T = 40`C to +85`C 0.8 0.6 1.5 nA
Average TC 1 1 3 pA/`C
B
C
D
E
A
A-2
AR Grade BR Grade ARM Grade
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
R
IN
20 20 20 kU
I
IN

IN+
, V
IN
, V
REF
= 0 50 60 50 60 50 60 A
Voltage Range V
S
+V
S
V
S
+V
S
V
S
+V
S
V
Gain to Output 1 0.0001 1 0.0001 1 0.0001 V/V
POWER SUPPLY
Operating Range V
S
= 2.3 V to 18 V 2.3 18 2.3 18 2.3 18 V
Quiescent Current 0.9 1 0.9 1 0.9 1 mA
Over Temperature T = 40`C to +85`C 1 1.2 1 1.2 1 1.2 mA
DYNAMIC RESPONSE
Small Signal 3 dB
Bandwidth
G = 1 825 825 825 kHz
G = 10 562 562 562 kHz
G = 100 100 100 100 kHz
G = 1,000 14.7 14.7 14.7 kHz
Settling Time 0.01% 10 V Step
G = 1 to 100 10 10 10 s
G = 1,000 80 80 80 s
Settling Time 0.001% 10 V Step
G = 1 to 100 13 13 13 s
G = 1,000 110 110 110 s
Slew Rate G = 1 1.5 1.7 1.5 1.7 1.5 1.7 V/s
G = 5 to 100 2 2.5 2 2.5 2 2.5 V/s
GAIN G = 1 + (49.4 kU/R
G
)
Gain Range 1 1,000 1 1,000 1 1,000 V/V
Gain Error V
OUT
10 V
G = 1 0.03 0.02 0.1 %
G = 10 0.3 0.15 0.3 %
G = 100 0.3 0.15 0.3 %
G = 1,000 0.3 0.15 0.3 %
Gain Nonlinearity V
OUT
= 10 V to +10 V
G = 1 to 10 R
L
= 10 kU 3 10 3 10 5 15 ppm
G = 100 R
L
= 10 kU 5 15 5 15 7 20 ppm
G = 1,000 R
L
= 10 kU 10 40 10 40 10 50 ppm
G = 1 to 100 R
L
= 2 kU 10 95 10 95 15 100 ppm
Gain vs. Temperature
G = 1 3 10 2 5 3 10 ppm/`C
G > 1
3
50 50 50 ppm/`C
INPUT
Input Impedance
Differential 100 ||2 100 ||2 100 ||2 GU ||pF
Common Mode 100 ||2 100 ||2 100 ||2 GU ||pF
Input Operating
Voltage Range
4
V
S
= 2.3 V to 5 V V
S
+ 1.9 +V
S
1.1 V
S
+ 1.9 +V
S
1.1 V
S
+ 1.9 +V
S
1.1 V
Over Temperature T = 40`C to +85`C V
S
+ 2.0 +V
S
1.2 V
S
+ 2.0 +V
S
1.2 V
S
+ 2.0 +V
S
1.2 V
Input Operating
Voltage Range V
S
= 5 V to 18 V V
S
+ 1.9 +V
S
1.2 V
S
+ 1.9 +V
S
1.2 V
S
+ 1.9 +V
S
1.2 V
Over Temperature T = 40`C to +85`C V
S
+ 2.0 +V
S
1.2 V
S
+ 2.0 +V
S
1.2 V
S
+ 2.0 +V
S
1.2 V
OUTPUT R
L
= 10 kU
Output Swing V
S
= 2.3 V to 5 V V
S
+ 1.1 +V
S
1.2 V
S
+ 1.1 +V
S
1.2 V
S
+ 1.1 +V
S
1.2 V
Over Temperature T = 40`C to +85`C V
S
+ 1.4 +V
S
1.3 V
S
+ 1.4 +V
S
1.3 V
S
+ 1.4 +V
S
1.3 V
Output Swing V
S
= 5 V to 18 V V
S
+ 1.2 +V
S
1.4 V
S
+ 1.2 +V
S
1.4 V
S
+ 1.2 +V
S
1.4 V
Over Temperature T = 40`C to +85`C V
S
+ 1.6 +V
S
1.5 V
S
+ 1.6 +V
S
1.5 V
S
+ 1.6 +V
S
1.5 V
Short-Circuit Current 18 18 18 mA
TEMPERATURE RANGE
Specifed Performance 40 +85 40 +85 40 +85 C
Operational
4
40 +125 40 +125 40 +125 C
NOTES
1
V
S
= 15 V, V
REF
= 0 V, T
A
= +25`C, G = 1, R
L
= 2 kU, unless otherwise noted.
2
Total RTI V
OS
= (V
OSI
) + (V
OSO
/G).
3
Does not include the effects of external resistor R
G
.
4
One input grounded. G = 1.
F
G
H
H
I
J
K
L
M
N
A-3
(A) Specifcations (Conditions)
A statement at the top of the data sheet explains that
the listed specifications are typically @ T
A
= 25`C,
V
S
= 15 V, and R
L
= 10 kU, unless otherwise noted.
This tells the user that these are the normal operating
conditions under which the device is tested. Deviations
from these conditions might degrade (or improve) perfor-
mance. For situations where deviations from the normal
conditions (such as a change in temperature) are likely,
the signifcant effects are usually indicated within the
specs. The statement at the top of the specifcations table
also tells us what all numbers are unless noted; typical
is used to state that the manufacturers characterization
process has shown a number to be average, however,
individual devices may vary.
Instrumentation amplifers designed for true rail-to-rail
operation have a few critical specifcations that need to
be considered. Their input voltage range should allow the
in-amp to accept input signal levels that are close to the
power supply or ground. Their output swing should be
within 0.1 V of the supply line or ground. In contrast, a
typical dual-supply in-amp can swing only within 2 V or
more of the supply or ground. In 5 V single-supply data
acquisition systems, an extended output swing is vital
because it allows the full input range of the ADC to be
used, providing high resolution.
(B) Common-Mode Rejection
Common-mode rejection is a measure of the change in
output voltage when the same voltage is applied to both
inputs. CMR is normally specifed as input, which allows
for in-amp gain. As the gain is increased, there will be a
higher output voltage for the same common-mode input
voltage. These specifcations may be given for either a
full range input voltage change or for a specifed source
imbalance in ohms.
Common-mode rejection ratio is a ratio expression,
while common-mode rejection is the logarithm of
that ratio. Both specifcations are normally referred to
output (RTO).
That is
CMRR
ChangeinOutput Voltage
ChangeinCommon Mode Input Voltage
=

While
CMR = 20 Log10 CMRR
For example, a CMRR of 10,000 corresponds to a CMR
of 80 dB. For most in-amps, the CMR increases with
gain because most designs have a front end confgura-
tion that rejects common-mode signals while amplifying
differential (i.e., signal) voltages.
Common-mode rejection is usually specifed for a full
range common-mode voltage change at a given frequency,
and a specifed imbalance of source impedance (e.g., l kU
source unbalance, at 60 Hz).
(C) AC Common-Mode Rejection
As might be expected, an in-amps common-mode rejec-
tion does vary with frequency. Usually, CMR is specifed
at dc or at very low input frequencies. At higher gains, an
in-amps bandwidth does decrease, lowering its gain and
introducing additional phase shift in its input stage.
Since any imbalance in phase shift in the differential input
stage will show up as a common-mode error, ac CMRR
will usually decrease with frequency. Figure A-1 shows
the CMR vs. frequency of the AD8221.

Figure A-1. AD8221 CMR vs. Frequency
(D) Voltage Offset
Voltage offset specifcations are often considered a
fgure of merit for instrumentation amplifers. While
any initial offset may be adjusted to zero through the
use of hardware or software, shifts in offset voltage due
to temperature variations are more diffcult to correct.
Intelligent systems using a microprocessor can use a
temperature reference and calibration data to correct
for this, but there are many small signal, high gain ap-
plications that do not have this capability.
A-4
Voltage offset and drift comprise four separate error
defnitions: room temperature (25`C), input and output,
offset, and offset drift over temperature referred to both
input and output.
An in-amp should be regarded as a 2-stage amplifer with
both an input and an output section. Each section has
its own error sources. Because the errors of the output
section are multiplied by a fxed gain (usually 2), this
section is often the principal error source at low circuit
gains. When the in-amp is operating at higher gains, the
gain of the input stage is increased. As the gain is raised,
errors contributed by the input section are multiplied,
while output errors are reduced. Thus, at high gains, the
input stage errors dominate.
Input errors are those contributed by the input stage
alone; output errors are those due to the output section.
Input related specifcations are often combined and
classifed together as referred to input (RTI) errors while
all output related specifcations are considered referred to
output (RTO) errors. It is important to understand that
although these two specifcations often provide numbers
that are not the same, either error term is correct because
each defnes the total error in a different way.
For a given gain, an in-amps input and output errors
can be calculated using the following formulas
Total Error, RTI = Input Error + (Output Error/Gain)
Total Error, RTO = (Gain Input Error) + Output Error
Sometimes the specifcation page will list an error term as
RTI or RTO for a specifed gain. In other cases, it is up
to the user to calculate the error for the desired gain.
As an example, the total voltage offset error of the
AD620A in-amp when it is operating at a gain of 10
can be calculated using the individual errors listed on
its specifcations page. The (typical) input offset of the
AD620 (V
OSI
) is listed as 30 V. Its output offset (V
OSO
)
is listed as 400 V. The total voltage offset referred to
input, RTI, is equal to
Total RTI Error = V
OSI
+ (V
OSO
/G) = 30 V + (400 V/10)
= 30 V + 40 V = 70 V
The total voltage offset referred to the output, RTO, is
equal to
Total Offset Error RTO = (G (V
OSI
)) + V
OSO
= (10 (30 V))
+ 400 V = 700 V.
Note that RTO error is 10 times greater in value than
the RTI error. Logically, it should be, because at a gain
of 10, the error at the output of the in-amp should be
10 times the error at the input.
(E) Input Bias and Offset Currents
Input bias currents are those currents fowing into or
out of the input terminals of the in-amp. In-amps using
FET input stages have lower room temperature bias cur-
rents than their bipolar cousins, but FET input currents
double approximately every 11`C. Input bias currents
can be considered a source of voltage offset error (i.e.,
input current fowing through a source resistance causes
a voltage offset). Any change in bias current is usually of
more concern than the magnitude of the bias current.
Input offset current is the difference between the two input
bias currents. It leads to offset errors in in-amps when source
resistances in the two input terminals are unequal.
Although instrumentation amplifers have differential
inputs, there must be a return path for their bias cur-
rents to fow to common (ground).
If this return path is not provided, the bases (or gates)
of the input devices are left foating (unconnected) and
the in-amps output will rapidly drift either to common
or to the supply.
Therefore, when amplifying foating input sources, such
as transformers (those without a center tap ground
connection), or ungrounded thermocouples, or any ac-
coupled input sources, there must still be a dc path from
each input to ground. A high value resistor of 1 MU to
10 MU connected between each input and ground will
normally be all that is needed to correct this condition.
(F) Operating Voltage Range
A single-supply in-amp should have the same overall
operating voltage range whether it is using single or
dual supplies. That is, a single-supply in-amp, which is
specifed to operate with dual-supply voltages from 1 V
to 18 V, should also operate over a 2 V to 36 V range
with a single supply, but this may not always be the case.
In fact, some in-amps, such as the AD623, will operate
to even lower equivalent voltage levels in single-supply
mode than with a dual-supply mode. For this reason, it
is always best to check the data sheet specifcations.
(G) Quiescent Supply Current
This specifies the quiescent or nonsignal power supply
current consumed by an in-amp within a specified
operating voltage range.
With the increasing number of battery-powered appli-
cations, device power consumption becomes a critical
design factor. Products such as the AD627 have a very
low quiescent current consumption of only 60 A, which
at 5 V is only 0.3 mW. Compare this power level to that
of an older, vintage dual-supply product, such as the
AD526. That device draws 14 mA with a 15 V supply
A-5
(30 V total) for a whopping 420 mW, 1,400 times the
power consumption of the AD627. The implications for
battery life are dramatic.
With the introduction of products such as the AD627,
very impressive overall performance is achieved while only
microamps of supply current are consumed. Of course,
some trade-offs are usually necessary, so micropower
in-amps tend to have lower bandwidth and higher noise
than full power devices. The ability to operate rail-to-rail
from a single-supply voltage is an essential feature of any
micropower in-amp.
(H) Settling Time
Settling time is defned as the length of time required
for the output voltage to approach, and remain within, a
certain tolerance of its fnal value. It is usually specifed
for a fast full-scale input step and includes output slew-
ing time. Since several factors contribute to the overall
settling time, fast settling to 0.1% does not necessarily
mean proportionally fast settling to 0.01%. In addition,
settling time is not necessarily a function of gain. Some
of the contributing factors to long settling times include
slew rate limiting, underdamping (ringing), and thermal
gradients (long tails).
(I) Gain
These specifcations relate to the transfer function of the
device. The products gain equation is normally listed at
the beginning of the specifcations page.
The gain equation of the AD8221 is
Gain
49,400
R
1
G
= +

To select an R
G
for a given gain, solve the following
equation for R
G
R
G
G
=

49 400
1
,
The following are samples of calculated resistance for
some common gains
G = 1: R
G
= ~ (open circuit)
G = 9.998: R
G
= 5.49 kU
G = 100: R
G
= 499 U
G = 991: R
G
= 49.9 U
Note that there will be a gain error if the standard re-
sistance values are different from those calculated. In
addition, the tolerance of the resistors used (normally 1%
metal flm) will also affect accuracy. There also will be
gain drift, typically 50 ppm/`C to 100 ppm/`C, if standard
resistors are used. Of course, the user must provide a very
clean (low leakage) circuit board to realize an accurate
gain of 1, since even a 200 MU leakage resistance will
cause a gain error of 0.2%.
Normal metal flm resistors are within 1% of their
stated value, which means that any two resistors could
be as much as 2% different in value from one another.
Thin flm resistors in monolithic integrated circuits
have an absolute tolerance of only 20%. The matching
between resistors on the same chip, however, can be
excellent typically better than 0.1%and resistors
on the same chip will track each other thermally, so
gain drift over temperature is greatly reduced.
(J) Gain Range
Often specifed as having a gain range of 1 to 1,000,
many instrumentation amplifers will often operate at
higher gains than 10,000, but the manufacturer will not
promise a specifc level of performance.
(K) Gain Error
In practice, as the gain resistor becomes increasingly
smaller, any errors due to the resistance of the metal runs
and bond wires inside the IC package become signifcant.
These errors, along with an increase in noise and drift,
may make higher gains impractical.
In 3-op amp and in-amp designs, both gain accuracy
and gain drift may suffer because the external resistor
does not exactly ratio match the ICs internal resistors.
Moreover, the resistor chosen is usually the closest 1%
metal flm value commonly available, rather than the
calculated resistance value; so this adds an additional
gain error. Some in-amps, such as the AD8230, use two
resistors to set gain. Assuming that gain is set solely by
the ratio of these two resistors in the IC, this can provide
potentially signifcant improvement in both gain accuracy
and drift. The best possible performance is provided by
monolithic in-amps that have all their resistors internal
to the IC, such as the AD621.
The number provided for this specifcation describes
maximum deviation from the gain equation. Monolithic
in-amps, such as the AD8221, have very low factory
trimmed gain errors. Although externally connected
gain networks allow the user to set the gain exactly, the
temperature coeffcients of these external resistors and
the temperature differences between individual resistors
within the network all contribute to the circuits overall
gain error.
A-6
If the data eventually is digitized and fed to an intelligent
system (such as a microprocessor), it may be possible to
correct for gain errors by measuring a known reference
voltage and then multiplying by a constant.
(L) Nonlinearity
Nonlinearity is defned as the deviation from a straight
line on the plot of an in-amps output voltage vs. input
voltage. Figure A-2 shows the transfer function of a device
with exaggerated nonlinearity.
The magnitude of this error is equal to
Nonlinearity
Actual Output CalculatedOutput
Rated Full ScaleOutput Range
=

This deviation can be specifed relative to any straight

line or to a specifc straight line. There are two commonly
used methods of specifying this ideal straight line relative
to the performance of the device.

Figure A-2. Transfer Function Illustrating
Exaggerated Nonlinearity
The best straight line method of defning nonlinearity con-
sists of measuring the peak positive and the peak negative
deviation and then adjusting the gain and offset of the
in-amp so that these maximum positive and negative
errors are equal. For monolithic in-amps this is usually
accomplished by laser trimming thin flm resistors or
by other means. The best straight line method provides
impressive specifcations, but it is much more diffcult
to perform. The entire output signal range needs to be
examined before trimming to determine the maximum
positive and negative deviations.
The endpoint method of specifying nonlinearity requires
that any offset and/or gain calibrations are performed at
the minimum and maximum extremes of the output range.
Usually offset is trimmed at a very low output level while
scale factor is trimmed near the maximum output level.
This makes trimming much easier to implement but may
result in nonlinearity errors of up to twice those attained
using the best straight line technique. This worst-case
error will occur when the transfer function is bowed in
one direction only.
Most linear devices, such as instrumentation amplifers,
are specifed for best straight line linearity. This needs
to be considered when evaluating the error budget for a
particular application.
Regardless of the method used to specify nonlinearity,
the errors thus created are irreducible. That is to say,
these errors are neither fxed nor proportional to input
or output voltage and, therefore, cannot be reduced by
external adjustment.
(M) Gain vs. Temperature
These numbers provide both maximum and typical
deviations from the gain equation as a function of tem-
perature. As stated in the Gain Error section (K), the TC
of an external gain resistor will never exactly match that
of other resistors within the IC package. Therefore, the
best performance over temperature is usually achieved by
in-amps using all internal gain resistors. Gain drift error
can be subtracted out in software by using a temperature
reference and calibration data.
(N) Key Specifcations for Single-Supply In-Amps
There are some specifcations that apply to single-supply
(i.e., rail-to-rail) in-amp products, which are of great
importance to designers powering in-amps from low
voltage, single-supply voltages.
Input and Output Voltage Swing
A single-supply in-amp needs to be able to handle
input voltages that are very close to the supply and
ground. In a typical dual-supply in-amp, the input
(and output) voltage range is within about 2 V of the
supply or ground. This becomes a real problem when
the device is powered from a 5 V supply, or can be
especially diffcult when using the new 3.3 V standard.
A standard in-amp operating from a 5 V single-supply
line has only about 1 V of headroom remaining; with
a 3.3 V supply, it has virtually none.
Fortunately, a decent single-supply in-amp, such as the
AD627, will allow an output swing within 100 mV of
the supply and ground. The input level is somewhat less,
within 100 mV of ground and 1 V of the supply rail. In
critical applications, the reference terminal of the in-amp
can be moved off center to allow a symmetrical input
voltage range.
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C-1
A
AC CMR vs. frequency table, 5-14
AC input coupling, 5-2
AD620:
dual-supply in-amp, 3-9
in-amp:
closed-loop gain vs. frequency, 3-4
CMR vs. frequency, 3-4
gain nonlinearity, 3-4
industry standard, 3-2, 3-3
input circuit, 5-4
RFI circuit, 5-10, 5-11
simplifed schematic, 3-3
small signal pulse response, 3-4
low power in-amp, 6-18
monolithic in-amp, 5-7
precision voltage-to-current converter, 6-22
AD621:
in-amp:
closed-loop gain vs. frequency, 3-6
CMR vs. frequency, 3-6
gain nonlinearity, 3-6
greater accuracy, 3-5
simplifed schematic, 3-5
small signal pulse response, 3-6
monolithic in-amp, 5-7
AD622:
low-cost in-amp:
closed-loop gain vs. frequency, 3-8
CMR vs. frequency, 3-8
gain nonlinearity, 3-8
AD623:
in-amp:
3-op amp circuit basis, 3-8
closed-loop gain vs. frequency, 3-9
CMR vs. frequency, 3-10
gain nonlinearity, 3-10
input circuit, 5-4
RFI flter, 5-12
RFI suppression circuit, 5-12
simplifed schematic, 3-9
small signal pulse response, 3-10
single-supply data circuit, 6-18
AD627:
classic bridge circuit, 6-17
CMR vs. frequency, 2-6
in-amp:
closed-loop gain vs. frequency, 3-12
CMR vs. frequency, 3-12
feedback loops, 3-11
gain, equation, 3-11
gain nonlinearity, 3-12
input circuit, 5-4
RFI suppression circuit, 5-11
simplifed schematic, 3-11
small signal pulse response, 3-12
low power in-amp, 6-23, 6-24
monolithic 2-op amp in-amp, 2-5, 2-6
AD628:
block diagram, 1-5
difference amplifer, 6-10, 6-11
differential scaling amplifer, 6-4
low gain, circuit, 6-4
precision gain block:
circuit, 6-3
gain of +1 circuit, 6-8
gain of +10 circuit, 6-6
gain of +11 circuit, 6-7
gain of 10 circuit, 6-7, 6-8
high CMRR, 6-3
no external components, 6-6
AD629:
difference amplifer, 1-8, 6-13
high common-mode range, 6-9, 6-10
high common-mode voltage, 6-15
monolithic difference amplifer, 2-1
AD671, ADC, multiplexer, 7-5
AD822, unity-gain inverter, 6-18
AD8205:
motor control application, 6-17
switch applications, 6-16, 6-17
AD8221:
bridge circuit, 1-1
CMR vs. frequency, A-3
gain equation, A-5
in flter, circuits, 5-13
in-amp:
characteristics, 3-2, 3-3
closed-loop gain vs. frequency, 3-3
CMR vs. frequency, 3-3
input circuit, 5-3
pinout, 3-3
simplifed schematic, 3-2
transfer function, 3-2
low noise device, 5-4
AD8225:
in-amp, RFI flter circuit, 5-12
CMR vs. frequency, 3-7
Index
C-2
gain nonlinearity, 3-7
monolithic in-amp, 3-7, 5-7
simplifed schematic, 3-7
AD8230:
in-amp:
auto-zeroing, 2-7, 2-8
circuits, 2-7
gain, circuit, 2-8
preamp phase, circuits, 2-8 to 2-10
AD8555, single-supply sensor amplifer, 2-9
ADC:
high level interface, 6-10
interface circuit:
single-supply, 6-10
common-mode input, 6-11
SNR, 6-11
recommended for in-amp tables, 7-2 to 7-4
requirements, calculation, 7-1
system resolution vs. converter resolution and
preamp gain table, 7-1
ADuC812, 12-bit ADC, embedded microcontroller, 6-23
AMP03, differential amplifer, 7-6
Audio applications, in-amp, 1-6
B
Bandwidth, in-amp, 1-8, 1-9
Bessel flter values, 5-16
Bipolar bridge, low dropout, driver, 6-18
Bridge:
applications, 6-17 to 6-24
using AC excitation, 6-2
Butterworth flter values, 5-16
C
Cable, shielding, 6-21
Cable termination, 5-3
CCD imaging, 7-4
CCD imaging equipment, in-amp, 1-6
Chebychev flter values, 5-16
Circuit:
bridge, 3-op amp in-amp, CMR, 1-4
bridge preamp, 1-1
CMR, 1-1 to 1-5
AC, in-amp, A-3
common-mode voltage, 1-2
dc values, 1-3
equation, 1-2
in-amp, 1-7, A-3
op amp vs. in-amp, 1-3 to 1-5
signal amplifcation, 1-1 to 1-3
CMR trimming, 5-17
CMRR:
calculation, 5-15
in-amp, A-3
Cold junction compensation, 6-24
Common-mode flter:
conventional, 5-13
with X2Y capacitor, 5-13
Common-mode gain, 1-2
Common-mode rejection, see CMR
Common-mode rejection ratio, see CMRR
Common-mode RF choke for in-amp RFI flter, 5-14
Common-mode voltage, 1-1, 1-2
in op amp circuit, 1-3
Composite in-amp:
circuit, 6-1
CMR, 6-1
CMR at gain of 100, 6-2
CMRR vs. frequency, 6-1
Controlling, in-amp, 1-6
Conversion, differential to single-ended, in-amp, 1-9
Current sense characteristics, table, 6-20
Current sensor interface, 6-22
Current transmitter, circuit, 6-9
D
Data acquisition, in-amp, 1-5
DC return path, 5-2
Decoupling, 5-1
Difference amplifer, 6-13
block diagram, 1-5
circuit, 1-5
IC, 1-5
nonlinearity vs. voltage, 6-13
selection table, B-1
use, 1-5 to 1-6
Differential input circuit:
single-pole low-pass flter, 6-3
two-pole low-pass flter, 6-5
Differential signal voltage, 1-1
Digi-key part no. PS1H102GND, 5-10
Diode, leakage, 5-5
E
EKG monitor characteristics, table, 6-20
Electrostatic discharge, see ESD
Error, calculations, 5-8
ESD:
input protection, 5-3
overload protection, 5-5
External CMR, performance, 5-17
External gain resistor, thermal gradient, error source, 5-7
External protection diodes, 5-5
C-3
F
Fast Schottky barrier rectifer, 5-5
Filter:
common-mode, using X2Y capacitors, 5-13
common-mode bandwidth, 5-10
component values, corner frequencies, tables, 6-6
differential:
bandwidths, 5-9
basic circuit, 5-9
low-pass, to improve SNR, 5-15, 5-16
RFI, 5-9, 5-12 to 5-15
two-pole low-pass, frequency response, 6-5
Float sensor characteristics, table, 6-20
G
Gain:
buffered subtractor circuit, 2-2
in-amp, 1-8
Gain error, in-amp, A-5, A-6
Gain range, in-amp, A-5
Gain resistor:
error source, 5-7
required value, table, 3-10
Gain vs. temperature, in-amp, A-6
Grid leak resistance, 5-2
Ground plane, in flter construction, 5-10
H
Hall effect magnetic characteristics, table, 6-20
High speed data acquisition, 7-4 to 7-6
High speed signal conditioning, in-amp, 1-6
High voltage monitor circuit, 6-13
High-side current sense, 6-17
I
Impedance, high input, in-amp, 1-8
In-amp:
2-op amp, 2-4 to 2-10
3-op amp, 2-2, 2-3
CMRR trim circuit, 5-17
feedback resistors, design, 5-6
3-op amp bridge circuit, CMR, 1-4
AC input coupling recommended component
values table, 5-3
application, 5-1 to 5-17
applications circuit, 6-1 to 6-24
auto-zeroing, 2-6 to 2-10
bipolar input stages, higher CMR, 2-3
buffers ADC, DC correction, 7-5
characteristics, 1-7 to 1-9
circuit:
CMR, 6-1, 6-2
matched to ADCs, 7-1 to 7-6
CMR, 1-7
composite, circuit, 6-1, 6-2
DC accuracy, design issues, 5-6, 5-7
defnition, 1-1
differential vs. common-mode input signals,
circuit, 1-6
dual-supply operation, 5-1
external protection diodes, 5-5
external resistor, 1-7
fxed gain, DC performance, 5-7
functional block diagram, 1-6
high CMR, 1-2
high quality, defnition, 1-7 to 1-9
high speed, high performance, 7-6
input ground return, 5-1, 5-2
input protection basics, 5-3 to 5-5
internal characteristics, 2-1 to 2-10
low cost, 3-8 to 3-10
low noise, 1-8
low power, single-supply, 3-11, 3-12
low power output buffering, 6-23
micropower, RFI circuit, 5-11
monolithic, 3-1 to 3-12
advantages, 3-1
for single-supply operation, 3-8 to 3-10
multiplexed, 7-5
operating gains table, 2-4
output, 1-7
power supply bypassing, 5-1
RFI rejection measurement, circuit, 5-15
selection table, B-1
single-supply, key specifcations, A-6
single-supply operation, 5-1
specifcations, A-1 to A-6
stability, 5-1
summary table, 3-1
transducer interface application, 6-19
uses, 1-5 to 1-6
vs. op amp, 3-1
characteristics, 1-1, 1-2
Wheatstone bridge, 6-17
In-amp circuit, input buffers, CMR, 1-4
Input bias:
in-amp, 1-8, A-4
Input noise, 5-8
Input and output voltage swing, in-amp, A-6
Input transient, 5-5
International rectifer SD101 series, 5-5
C-4
J
J-type thermocouple, 6-24
Johanson Dielectrics, X2Y capacitor, 5-13
Johnson noise, 5-3
L
Level sensor characteristics, table, 6-20
Linearity, best straight line method, A-6
Load cell characteristics, table, 6-20
Low-pass flter:
4-pole, 5-16
recommended component values table, 5-16
M
Medical EKG monitor circuit, 6-19
Medical instrumentation, in-amp, 1-6
Micropower in-amp, RFI circuit, 5-11
Monitoring, in-amp, 1-6
N
Noise:
ground, 6-9, 6-10
in-amp, 1-9
low, in-amp, 1-8
Noise error, 5-8
Nonlinearity:
in-amp, A-6
low, in-amp, 1-8
O
Offset current, in-amp, A-4
Offset current error, in-amp, 1-8
Offset error, 5-8
Op amp:
CMR, 1-3
in-amp difference amplifer circuit,
block diagram, 2-1
subtractor, as in-amp, 2-1
vs. in-amp, 1-1 to 1-5
OP27, transfer function, 6-10
OP177, integrator, 6-13
Operating voltage range, in-amp, A-4
Output buffer, for low power in-amp, 6-23
Output swing, in-amp, 1-9
Overload:
steady state, 5-3
transient, 5-3
P
Photodiode sensor characteristics, table, 6-20
Power, in-amp, 1-9
Power controlling, in-amp, 1-6
Power distribution bus:
output vs. input linearity, 6-16
precision remote voltage measurement, 6-15
temperature drift, 6-16
Power supply bypassing, 5-1
Pulse Engineering, common-mode choke, 5-14
Q
Quiescent supply current, in-amp, A-4, A-5
R
Rail-to-rail input, in-amp, 1-9
RC component matching, 5-2
Receiver circuit, 6-23
Referred-to-input, see RTI
Referred-to-output, see RTO
Remote load sensing circuit, 6-21
Resistance temperature detector characteristics, table, 6-20
Resistor, error source, 5-6
Resistor thermocouple EMF values table, 5-7
Resistor values for in-amps, table, 5-5
RFI:
circuit, 5-9
flter, design, 5-8 to 5-10
input flter component values, selecting, 5-10
rectifcation error, reducing, 5-8 to 5-17
RFI attenuation, X2Y vs. conventional RC
common-mode flter, 5-13
RFI flter, 5-9, 5-12 to 5-16
RFI suppression, using common-mode RF choke, 5-14
RFI testing, 5-15
RTI, in-amp, A-4
RTI error, 5-7, 5-8
RTO, in-amp, A-4
RTO error, 5-7, 5-8
S
Schottky diode, 5-5
Settling time, 5-17
Signal voltage, in op amp circuit, 1-3
Signal-to-noise ratio, see SNR
Silicon diode, 5-5
Single-supply bridge confguration, characteristics
table, 6-20
Single-supply circuit:
high CMR, 6-13 to 6-17
high common-mode rejection, 6-14
performance, 6-14
Slew rate, in-amp, 1-9
SNR, 3-1, 5-15
Software programming, in-amp, 1-6
Specifcations, in-amp, A-3
C-5
SSM2019, audio preamplifer, 6-24
SSM2141, diff line receiver, 6-24
SSM2143, diff line receiver, 6-24
Strain gage, measurement, with AC excitation, 6-2, 6-3
Strain gage bridge characteristics, table, 6-20
Subtractor amplifer, circuit, 1-5
Subtractor circuit:
buffered, 2-2
input buffering, 2-1
Summing amplifer:
circuit, 6-12
high input impedance, 6-12
frequency response, 6-13
high speed noninverting, 6-11, 6-12
Switches:
high-side, 6-17
low-side, 6-16
T
2-op amp in-amp:
architecture, 2-5
circuit, 2-4
common-mode design, 2-5, 2-6
limitations
CMR, 2-6
output swing, 2-5
3-op amp in-amp, 2-2, 2-3
circuit, 2-2
CMRR trim circuit, 5-17
design considerations, 2-3, 2-4
feedback resistors, design, 5-6
reduced CMV range, circuit, 2-3
Thermal gradient, error source, 5-7
Thermal sensor characteristics, table, 6-20
Thermistor characteristics, table, 6-20
Thermocouple amplifer:
single-supply in-amp, 6-24
Thermocouple characteristics, table, 6-20
Total error, in-amp, A-4
Total noise, 5-8
Total offset error, in-amp, A-4
Transducer characteristics table, 6-20
Transfer function, nonlinearity, A-6
Transformer-coupled input, DC return path, 5-2
Transient, overload protection, 5-5
V
Video applications, in-amp, 1-6
Voltage:
common-mode, 1-1
differential signal, 1-1
offset, in-amp, 1-7
Voltage drift, lowest, design, 5-6, 5-7
Voltage offset, in-amp, A-3, A-4
Voltage-to-current converter, 6-22
W
Weight measurement characteristics, table, 6-20
X
X2Y capacitor, 5-13
electrostatic model, 5-13
D-1
Device Index
Product Page
AD524 3-3
AD526 A-4
AD589 6-18
AD620 3-1, 3-2, 3-9, 5-4, 5-5, 5-7, 5-8, 5-10,
5-14, 6-18, 6-20, 6-22, B-1
AD620AR 7-2
AD621 1-8, 3-1, 3-5, 3-6, 5-4, 5-5,
5-7, 6-20, A-5, B-1
AD622 3-1, 3-8, 5-4, 5-5, 6-20, B-1
AD623 3-1, 3-8 to 3-10, 5-4, 5-5, 5-12,
6-1, 6-2, 6-18, 6-20, 6-21, A-4, B-1
AD623AR 7-3
AD626 6-20, 6-22, B-1
AD627 2-5, 2-6, 3-1, 3-11, 3-12,
5-4, 5-5, 5-11, 5-12, 6-17, 6-18,
6-20, 6-21, 6-23, 6-24, A-4 to A-6, B-1
AD627AR 7-4
AD628 1-5, 6-3 to 6-8, 6-10, 6-11, 6-20, B-1
AD629 1-5, 1-8, 2-1, 6-9, 6-10, 6-13 to 6-15, 6-20, B-1
AD630 6-3
AD630AR 6-2
AD671 7-5
AD704 5-16
AD705 6-22
AD706 5-16
AD780 6-10, 6-11
AD820 6-21, 6-23
AD822 6-18, 6-21
AD823 7-6
AD824 6-21
AD825 7-6
AD830 7-6
AD871 7-6
AD7450 6-10, 6-11
AD7453/AD7457 7-2
AD7476 6-15
AD7661 7-3
AD7663 7-2
AD7685 7-2
Product Page
AD7688 7-3
AD7776 6-18
AD7825 6-2
AD7862/AD7684 7-3
AD7863/AD7865 7-3
AD7890/AD7891/AD7892 7-3
AD7895 7-2
AD7920 7-4
AD7923/AD7927 7-4
AD7940 7-3
AD8130 6-12
AD8202 6-20, B-1
AD8205 6-16, 6-17, 6-20
AD8221 1-1, 3-1 to 3-3, 5-3 to 5-5, 5-9, 5-10,
5-12, 5-13, 6-1 to 6-3, 6-20, 6-21,
A-1 to A-3, A-5
AD8221AR 7-2, B-1
AD8221ARM B-1
AD8221BR B-1
AD8225 3-1, 3-7, 5-5, 5-7, 5-12, 6-1, 6-20, 7-3, B-1
AD8230 2-7, 2-8, A-5
AD8555 2-9
AD8698 2-1, 2-2, 2-4
AD9240 7-6
AD22057 B-1
ADR425 6-15
ADuC812 6-23
AMP01 6-21
AMP03 6-21, 7-6, B-1
OP27 6-9, 6-10
OP97 6-15
OP177 6-13
OP297 5-16
OP497 5-16
OP1177 2-1, 2-2, 6-2
OP2177 2-1, 2-2, 2-4
SSM2019 6-24
SSM2141 6-24
SSM2143 6-24
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