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Chisel

Chisel is an open source hardware description language developed at UC Berkeley that allows designing hardware using Scala. It provides object orientation, functional programming, parameterized types, and type inference to raise the level of abstraction. Chisel designs can be simulated using a high speed C++ simulator and synthesized to Verilog for implementation in FPGAs or ASICs. Chisel supports highly parameterized circuit generators and is built on the Scala programming language to provide powerful abstraction capabilities compared to traditional HDLs like Verilog.

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Gopinathan Muthusamy
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214 views5 pages

Chisel

Chisel is an open source hardware description language developed at UC Berkeley that allows designing hardware using Scala. It provides object orientation, functional programming, parameterized types, and type inference to raise the level of abstraction. Chisel designs can be simulated using a high speed C++ simulator and synthesized to Verilog for implementation in FPGAs or ASICs. Chisel supports highly parameterized circuit generators and is built on the Scala programming language to provide powerful abstraction capabilities compared to traditional HDLs like Verilog.

Uploaded by

Gopinathan Muthusamy
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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CHISEL(Constructing Hardware In a Scala Embedding Language)

A new open source hardware constructive language developed at UC Berkely which supports Hardware design using highly parameterised generators and layered domain specific hardware languages Embedded in the scala programming language which raises the abstraction by providing concepts like

-->Object orientation -->Functional Programming -->Parameterized types -->Type inference Currently Chisel 2.0 is the recent version which has simplified types and support multiple clock domains.

Chisel

High Speed C++ Based cycle-accurate software Simulator

Low level Verilog to pass ASIC or FPGA tools

Y not others??? Y Chisel


Lack Powerful abstraction facilities => Difficult to reuse components => Low Designer Productivity Initially Verilog were developed as H/w simulation Language and later a basis for H/w synthesis Many of the constructs are not synthesizable like
Initial Events Real Time Force & Release Assign & Deassign Primitives

and some are non-intuitive which may yield a highly inefficient hardware structures. Chisel supports highly parameterized circuit generators. Chisel is built in a Domain Specific language - Scala.

Chisel Installation
Following packages to be installed in Ubuntu 13.04: 1) git 2) g++ 3) openjdk-7-jre 4) openjdk-7-jdk 5) sbt (version 12.3) 6) scala (version 2.10.2) 7) gcc (version 4.8)

Files For My Project


Build.sbt Myproject.scala Make file (if necessary)

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