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PART A - (10 ×2 20 Marks)

The document contains questions from a digital logic exam covering topics such as: - Boolean algebra and logic gates - Flip-flops and sequential circuits - Adders and multipliers - Code converters It asks the student to prove theorems, derive equations, design circuits, explain concepts, and minimize logic functions. Solutions involve techniques like Quine-McClusky, K-maps, and designing circuits using flip-flops, gates, adders and multipliers.

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selva_raj215414
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51 views2 pages

PART A - (10 ×2 20 Marks)

The document contains questions from a digital logic exam covering topics such as: - Boolean algebra and logic gates - Flip-flops and sequential circuits - Adders and multipliers - Code converters It asks the student to prove theorems, derive equations, design circuits, explain concepts, and minimize logic functions. Solutions involve techniques like Quine-McClusky, K-maps, and designing circuits using flip-flops, gates, adders and multipliers.

Uploaded by

selva_raj215414
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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PART A (10 2 = 20 Marks) 1. Prove that the logical sum of all minterms of a Boolean function of 2 variable is 1. 2.

. Show that a positive logic NAND gate is a negative logic NOR gate. 3. Suggest a solution to overcome the limitation on the speed of an adder. 4. Differentiate a decoder from a Demultiplexer. 5. Write down the characteristic equation for JK flip-flop. 6. Distinguish between synchronous and asynchronous sequential circuits. 7. Compare and contrast static RAM and dynamic RAM. 8. What is PAL? How does it differ from PLA? 9. What are Hazards? 10. Draw the block diagram for Moore model. PART B 11. (a) (i) Express the Boolean function as (1) POS form and (2) SOP form D = (A + B) (B + C) (4) (ii) Minimize the given terms m (0, 1, 4, 11, 13, 15) + d (5, 7, 8) using QuineMcClusky methods and verify the results using K-map methods. (12) Or (b) (i) Implement the following function using NOR gates. (8) Output = 1 when the inputs are m(0,1,2,3,4) = 0 when the inputs are m(5,6,7) . (ii) Reduce the following function using K-map technique f (A ,B, C ,D)= (0,3,4,7,8,10,12,14) + d (2,6 ). (8)

12. (a) (i) Design and derive the equation for a 4-bit look ahead carry adder circuit. (6) (ii) Draw and explain the block diagram of a 4-bit serial adder to add the contents of two registers. (8) Or (b) (i) Multiply (1011)2 by (1101)2 using addition and shifting operation also draw block diagram of the 4-bit by 4 bit parallel multiplier. (8) (ii) Design and implement the conversion circuits for Binary code to gray code. (8)

13. (a) (i) How will you convert a D flipflop into JK flipflop? (8) (ii) Explain the operation of a JK master slave flipflop. (8) Or (b) Explain in detail the operation of a 4 bit binary ripple counter. (16) 15. (a) Design a three bit binary counter using T flipflops. (16) Or (b) Design a negative-edge triggered T flipflop. (16)

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