Scribd
Upload
61 views5 pages

DSP Design Flow: v8.2 System Generator

This two-day course teaches attendees how to design digital signal processing (DSP) systems using Xilinx FPGAs. On day one, attendees will learn about DSP design flows, creating a multiplier-accumulator (MAC) using System Generator, HDL co-simulation, and digital filtering. Day two covers quantization, overflow, data path management, controlling systems, multi-rate systems, and sample rate changing blocks. By the end of the course, attendees will be able to design DSP functions from algorithm to hardware simulation using Xilinx tools.

Uploaded by

sgrupnar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
61 views5 pages

DSP Design Flow: v8.2 System Generator

This two-day course teaches attendees how to design digital signal processing (DSP) systems using Xilinx FPGAs. On day one, attendees will learn about DSP design flows, creating a multiplier-accumulator (MAC) using System Generator, HDL co-simulation, and digital filtering. Day two covers quantization, overflow, data path management, controlling systems, multi-rate systems, and sample rate changing blocks. By the end of the course, attendees will be able to design DSP functions from algorithm to hardware simulation using Xilinx tools.

Uploaded by

sgrupnar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 5

DSP Design Flow

v8.2 System Generator

This material exempt per Department of Commerce license exception TSU

Schedule

Start @ 9am Break @ 10:30am Lunch @ noon Break @ 3:00pm End @ 5pm

Objectives
After completing this course, you will be able to:

Describe the different design flows for implementing DSP functions, with a large focus on the System Generator Understand the Xilinx FPGA capabilities and know how to implement a design from algorithm concept to hardware simulation Perform Hardware in the Loop targeting a hardware platform

Day 1 Agenda
Introduction
Power of Parallelism Platform FPGA Virtex-II/ Virtex-II Pro Series Spartan-3 Architecture

DSP Design Flows in FPGA


Using the Xilinx System Generator for DSP Hardware in the Loop Accelerated Verification Lab 1: Creating a 12x8 MAC using System Generator for DSP

HDL Co-Simulation
Co-Simulation support blocks Co-Simulation process Lab 2: MAC FIR Filter Verification using HDL Co-Simulation

Digital Filtering
Digital Filtering Blocks Use the FDA Tool in Conjunction with the Xilinx Blockset Lab 3: Designing a FIR Filter

Day 2
Looking Under the Hood

Quantization and Overflow Hardware Cost Data Path Management Lab 4: Looking under the hood

Controlling the System


Control Mechanism Control Blocks Lab 5: Controlling the System

Multi-rate Systems

Sample Rates Sample Rate Changing Blocks Hardware Realization of Sample Rate Changing Blocks Lab 6: Designing a MAC FIR

You might also like