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Vlsi Flow

This document outlines the VLSI design flow process which includes specifying requirements, developing block and register transfer level (RTL) code using hardware description languages like VHDL or Verilog, simulating the design, synthesizing the RTL code to produce a netlist, and implementing the netlist on an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA). The flow involves moving from high level specifications down to lower level hardware implementation and validation through simulation and synthesis.

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Praveen Kumar
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119 views14 pages

Vlsi Flow

This document outlines the VLSI design flow process which includes specifying requirements, developing block and register transfer level (RTL) code using hardware description languages like VHDL or Verilog, simulating the design, synthesizing the RTL code to produce a netlist, and implementing the netlist on an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA). The flow involves moving from high level specifications down to lower level hardware implementation and validation through simulation and synthesis.

Uploaded by

Praveen Kumar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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VLSI FLOW

Specification

Block

RTL Code

VHDL / Verilog / System C

Simulation

Synthesis

Net list

Specifications

Time

Area

Block Level

RTL Code

C / C++ VERILOG /VHDL

Why HDL

C - HDL
C is a sequential language. This code is used only for functional verification. HDL is concurrent language. This HDL code can be converted into hardware. We can include time delays.

Specification

Block

RTL Code

VHDL / Verilog / System C

Simulation

Synthesis

Net list

Simulation

Functional verification

Synthesis
HDL to Hardware

Lib file
RTL Code

constraints

Synthesis

Net List

Net List

F-C

S-C

ASIC

FPGA

ASIC / FPGA

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