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Module-2, Session-1 HDL Design Concepts and RTL Coding With VHDL

The document discusses an advanced training program on VLSI semi-custom design using FPGAs. It covers fundamentals of hardware description languages like VHDL for register-transfer level design. It also outlines an ASIC or FPGA design flow involving writing RTL code, simulation, synthesis to gates, and meeting timing constraints and testing before backend processing. Finally, it discusses using VHDL at different levels including specification, simulation and synthesis, and different VHDL design styles.

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Praveen Kumar
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144 views7 pages

Module-2, Session-1 HDL Design Concepts and RTL Coding With VHDL

The document discusses an advanced training program on VLSI semi-custom design using FPGAs. It covers fundamentals of hardware description languages like VHDL for register-transfer level design. It also outlines an ASIC or FPGA design flow involving writing RTL code, simulation, synthesis to gates, and meeting timing constraints and testing before backend processing. Finally, it discusses using VHDL at different levels including specification, simulation and synthesis, and different VHDL design styles.

Uploaded by

Praveen Kumar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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VLSI semi custom design with FPGAs

Fundamentals of Hardware Description Languages VHDL RTL based design

Advanced Training Programme on

VLSI semi custom design with FPGA

www.unistring.com www.stringtechnologies.net

Write RTL HDL Code

ASIC of FPGA design flow


No Simulate OK Yes Synthesize RTL Code to Gates Gate Level Netlist No Constraints Met? Yes No Gate Level Testing OK?

Yes
Proceed with Backend Processing

Advanced Training Programme on

VLSI semi custom design with FPGA

www.unistring.com www.stringtechnologies.net

Architecture design Write RTL HDL Code

ASIC of FPGA design flow


No Simulate OK Yes Synthesize RTL Code to Gates

The role of front end designers


No

Gate Level Netlist Constraints Met? Yes No Gate Level Testing OK?

Most critical part

Yes
Proceed with Backend Processing

Advanced Training Programme on

VLSI semi custom design with FPGA

www.unistring.com www.stringtechnologies.net

Achieving Performance at various stages

Advanced Training Programme on

VLSI semi custom design with FPGA

www.unistring.com www.stringtechnologies.net

Register Transfer Logic (RTL)

Combinational Logic

Combinational Logic

Registers
Slide taken from K.Gaj lectures at GMU

Advanced Training Programme on

VLSI semi custom design with FPGA

www.unistring.com www.stringtechnologies.net

Levels at which VHDL can be used


VHDL for Specification
VHDL for Simulation

VHDL for Synthesis

Slide taken from K.Gaj lectures at GMU

Advanced Training Programme on

VLSI semi custom design with FPGA

www.unistring.com www.stringtechnologies.net

VHDL Design Styles


VHDL Design Styles

dataflow
Concurrent statements

structural
Components and interconnects

behavioral
Sequential statements Registers State machines Test benches

Subset most suitable for synthesis


Advanced Training Programme on

VLSI semi custom design with FPGA

www.unistring.com www.stringtechnologies.net

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