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LC4 Single Cycle Diagram

This document summarizes the single cycle implementation of the LC4 instruction set architecture. It shows the control signals and datapath for decoding instructions and performing arithmetic, logical, shift, load/store, branch, and test operations in a single clock cycle using a register file, ALU, shifter, program counter, and data memory. Key components include the instruction decoder, register file, ALU multiplexers, and control units for arithmetic, logical, shift, and test operations.

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Adnaan Mukadam
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835 views

LC4 Single Cycle Diagram

This document summarizes the single cycle implementation of the LC4 instruction set architecture. It shows the control signals and datapath for decoding instructions and performing arithmetic, logical, shift, load/store, branch, and test operations in a single clock cycle using a register file, ALU, shifter, program counter, and data memory. Key components include the instruction decoder, register file, ALU multiplexers, and control units for arithmetic, logical, shift, and test operations.

Uploaded by

Adnaan Mukadam
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Single Cycle Implementation of the LC4 ISA

ALL CTL SIGNALS


Decode

ALU
Arith.CTL

regFile.WE I[8:6] 0x07 I[11:9] I[2:0] I[11:9]


rsMux.CTL

ArithMux.CTL

Arithmetic Ops
ALUMux.CTL

SEXT(I[4:0])

0 1 2
LOGIC.CTL

0 1 2

rs.addr
Register File

SEXT(I[5:0])

regInputMux.CTL
Logical Ops
0

RS[15:0]

rtMux.CTL
0 1

LogicMux.CTL

rt.adddr
SEXT(I[4:0])

1 0 1
SHIFT.CTL

DATA.WE
Shifter

PC

Instruction Address PC[15:0]

I[11:9]
Program Memory

rdMux.CTL
0

I[15:0]

rd.addr
Write Input

RT[15:0]

Data Address
2 0

Instruction

0x07

I[3:0]
CONST.CTL

Data Output
DATA Memory

Constants
3

I[8:0]
NZP.WE
CMP.CTL

I[11:9]
TEST

Data Input
NZP Register NZP Tester

PCMux.CTL

I[6:0]
0 0 1

Comparator

SEXT(I[8:0])

2 RS[15:0]

SEXT(I[10:0])

3 (0x8000 | UIMM8) 4
(PC & 0x8000) | (IMM11<<4)

I[7:0]

I[10:0]

Branch Unit
+1

PC+1

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